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path: root/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h
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Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h152495
1 files changed, 152495 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h
new file mode 100644
index 000000000000..e27fdc0c643c
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h
@@ -0,0 +1,152495 @@
+
+/*
+ * Copyright (C) 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _nbio_7_2_0_SH_MASK_HEADER
+#define _nbio_7_2_0_SH_MASK_HEADER
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+//BIF_CFG_DEV0_RC_VENDOR_ID
+#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC_DEVICE_ID
+#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC_COMMAND
+#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_RC_STATUS
+#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_RC_REVISION_ID
+#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_RC_PROG_INTERFACE
+#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_RC_SUB_CLASS
+#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_RC_BASE_CLASS
+#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_RC_CACHE_LINE
+#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_RC_LATENCY
+#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_RC_HEADER
+#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_RC_BIST
+#define BIF_CFG_DEV0_RC_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_RC_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_RC_BASE_ADDR_1
+#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_BASE_ADDR_2
+#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV0_RC_SECONDARY_STATUS
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_RC_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC_CAP_PTR
+#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_RC_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_INTERRUPT_LINE
+#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_RC_INTERRUPT_PIN
+#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIF_CFG_DEV0_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV0_RC_PMI_CAP_LIST
+#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_PMI_CAP
+#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_RC_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_PCIE_CAP
+#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_RC_DEVICE_CAP
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_RC_DEVICE_CNTL
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV0_RC_DEVICE_STATUS
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_RC_LINK_CAP
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC_LINK_CNTL
+#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_RC_LINK_STATUS
+#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_RC_SLOT_CAP
+#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV0_RC_SLOT_CNTL
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIF_CFG_DEV0_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIF_CFG_DEV0_RC_SLOT_STATUS
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV0_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV0_RC_ROOT_CNTL
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV0_RC_ROOT_CAP
+#define BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV0_RC_ROOT_STATUS
+#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV0_RC_DEVICE_CAP2
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_RC_DEVICE_CNTL2
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_RC_DEVICE_STATUS2
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC_LINK_CAP2
+#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_RC_LINK_CNTL2
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_RC_LINK_STATUS2
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC_SLOT_CAP2
+#define BIF_CFG_DEV0_RC_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_SLOT_CNTL2
+#define BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC_SLOT_STATUS2
+#define BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC_MSI_CAP_LIST
+#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_MSI_MSG_DATA
+#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC_SSID_CAP_LIST
+#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_SSID_CAP
+#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_MSI_MAP_CAP
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV0_RC_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC_LINK_CAP_16GT
+#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
+//BIF_CFG_DEV1_RC_VENDOR_ID
+#define BIF_CFG_DEV1_RC_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC_DEVICE_ID
+#define BIF_CFG_DEV1_RC_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC_COMMAND
+#define BIF_CFG_DEV1_RC_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_RC_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_RC_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_RC_STATUS
+#define BIF_CFG_DEV1_RC_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_RC_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_RC_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_RC_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_RC_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_RC_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_RC_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_RC_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_RC_REVISION_ID
+#define BIF_CFG_DEV1_RC_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_RC_PROG_INTERFACE
+#define BIF_CFG_DEV1_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_RC_SUB_CLASS
+#define BIF_CFG_DEV1_RC_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_RC_BASE_CLASS
+#define BIF_CFG_DEV1_RC_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_RC_CACHE_LINE
+#define BIF_CFG_DEV1_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_RC_LATENCY
+#define BIF_CFG_DEV1_RC_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_RC_HEADER
+#define BIF_CFG_DEV1_RC_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_RC_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_RC_BIST
+#define BIF_CFG_DEV1_RC_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_RC_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_RC_BASE_ADDR_1
+#define BIF_CFG_DEV1_RC_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_BASE_ADDR_2
+#define BIF_CFG_DEV1_RC_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_RC_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC_IO_BASE_LIMIT
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV1_RC_SECONDARY_STATUS
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_RC_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_RC_MEM_BASE_LIMIT
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC_PREF_BASE_LIMIT
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC_PREF_BASE_UPPER
+#define BIF_CFG_DEV1_RC_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV1_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC_CAP_PTR
+#define BIF_CFG_DEV1_RC_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV1_RC_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_INTERRUPT_LINE
+#define BIF_CFG_DEV1_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_RC_INTERRUPT_PIN
+#define BIF_CFG_DEV1_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIF_CFG_DEV1_RC_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV1_RC_PMI_CAP_LIST
+#define BIF_CFG_DEV1_RC_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_PMI_CAP
+#define BIF_CFG_DEV1_RC_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_RC_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_RC_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_RC_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_RC_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_PCIE_CAP
+#define BIF_CFG_DEV1_RC_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_RC_DEVICE_CAP
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_RC_DEVICE_CNTL
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV1_RC_DEVICE_STATUS
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV1_RC_LINK_CAP
+#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_RC_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_RC_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC_LINK_CNTL
+#define BIF_CFG_DEV1_RC_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV1_RC_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV1_RC_LINK_STATUS
+#define BIF_CFG_DEV1_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_RC_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_RC_SLOT_CAP
+#define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_RC_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV1_RC_SLOT_CNTL
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIF_CFG_DEV1_RC_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIF_CFG_DEV1_RC_SLOT_STATUS
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV1_RC_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV1_RC_ROOT_CNTL
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV1_RC_ROOT_CAP
+#define BIF_CFG_DEV1_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV1_RC_ROOT_STATUS
+#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV1_RC_DEVICE_CAP2
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV1_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_RC_DEVICE_CNTL2
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_RC_DEVICE_STATUS2
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC_LINK_CAP2
+#define BIF_CFG_DEV1_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV1_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV1_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_RC_LINK_CNTL2
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_RC_LINK_STATUS2
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV1_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC_SLOT_CAP2
+#define BIF_CFG_DEV1_RC_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_SLOT_CNTL2
+#define BIF_CFG_DEV1_RC_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC_SLOT_STATUS2
+#define BIF_CFG_DEV1_RC_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC_MSI_CAP_LIST
+#define BIF_CFG_DEV1_RC_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV1_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_MSI_MSG_DATA
+#define BIF_CFG_DEV1_RC_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC_SSID_CAP_LIST
+#define BIF_CFG_DEV1_RC_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_SSID_CAP
+#define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_MSI_MAP_CAP
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV1_RC_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV1_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV1_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV1_RC_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV1_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC_LINK_CAP_16GT
+#define BIF_CFG_DEV1_RC_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_LINK_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC_LINK_STATUS_16GT
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC_MARGINING_PORT_CAP
+#define BIF_CFG_DEV1_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV1_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec
+
+
+// addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_COMMAND
+#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_STATUS
+#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_LATENCY
+#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_HEADER
+#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_BIST
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_COMMAND
+#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_STATUS
+#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_LATENCY
+#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_HEADER
+#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_BIST
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_COMMAND
+#define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_STATUS
+#define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_LATENCY
+#define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_HEADER
+#define BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_BIST
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF2_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF2_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_SBRN
+#define BIF_CFG_DEV0_EPF2_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_FLADJ
+#define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF2_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF2_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_COMMAND
+#define BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_STATUS
+#define BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_LATENCY
+#define BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_HEADER
+#define BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF3_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_BIST
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF3_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF3_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_SBRN
+#define BIF_CFG_DEV0_EPF3_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_FLADJ
+#define BIF_CFG_DEV0_EPF3_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF3_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF3_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF3_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF3_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF3_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF3_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF4_VENDOR_ID
+#define BIF_CFG_DEV0_EPF4_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_DEVICE_ID
+#define BIF_CFG_DEV0_EPF4_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_COMMAND
+#define BIF_CFG_DEV0_EPF4_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF4_STATUS
+#define BIF_CFG_DEV0_EPF4_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_REVISION_ID
+#define BIF_CFG_DEV0_EPF4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF4_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_SUB_CLASS
+#define BIF_CFG_DEV0_EPF4_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_BASE_CLASS
+#define BIF_CFG_DEV0_EPF4_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_CACHE_LINE
+#define BIF_CFG_DEV0_EPF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_LATENCY
+#define BIF_CFG_DEV0_EPF4_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_HEADER
+#define BIF_CFG_DEV0_EPF4_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF4_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF4_BIST
+#define BIF_CFG_DEV0_EPF4_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF4_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF4_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_CAP_PTR
+#define BIF_CFG_DEV0_EPF4_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_MIN_GRANT
+#define BIF_CFG_DEV0_EPF4_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF4_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF4_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF4_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PMI_CAP
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_SBRN
+#define BIF_CFG_DEV0_EPF4_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_FLADJ
+#define BIF_CFG_DEV0_EPF4_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF4_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF4_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF4_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF4_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF4_LINK_CAP
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_LINK_CNTL
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF4_LINK_STATUS
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF4_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_LINK_CAP2
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF4_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF4_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_MASK
+#define BIF_CFG_DEV0_EPF4_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF4_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_PENDING
+#define BIF_CFG_DEV0_EPF4_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_MSIX_PBA
+#define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF5_VENDOR_ID
+#define BIF_CFG_DEV0_EPF5_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_DEVICE_ID
+#define BIF_CFG_DEV0_EPF5_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_COMMAND
+#define BIF_CFG_DEV0_EPF5_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF5_STATUS
+#define BIF_CFG_DEV0_EPF5_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_REVISION_ID
+#define BIF_CFG_DEV0_EPF5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF5_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_SUB_CLASS
+#define BIF_CFG_DEV0_EPF5_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_BASE_CLASS
+#define BIF_CFG_DEV0_EPF5_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_CACHE_LINE
+#define BIF_CFG_DEV0_EPF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_LATENCY
+#define BIF_CFG_DEV0_EPF5_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_HEADER
+#define BIF_CFG_DEV0_EPF5_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF5_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF5_BIST
+#define BIF_CFG_DEV0_EPF5_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF5_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF5_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_CAP_PTR
+#define BIF_CFG_DEV0_EPF5_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_MIN_GRANT
+#define BIF_CFG_DEV0_EPF5_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF5_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF5_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF5_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PMI_CAP
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_SBRN
+#define BIF_CFG_DEV0_EPF5_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_FLADJ
+#define BIF_CFG_DEV0_EPF5_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF5_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF5_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF5_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF5_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF5_LINK_CAP
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_LINK_CNTL
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF5_LINK_STATUS
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF5_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_LINK_CAP2
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF5_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF5_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_MASK
+#define BIF_CFG_DEV0_EPF5_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF5_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_PENDING
+#define BIF_CFG_DEV0_EPF5_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_MSIX_PBA
+#define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF6_VENDOR_ID
+#define BIF_CFG_DEV0_EPF6_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_DEVICE_ID
+#define BIF_CFG_DEV0_EPF6_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_COMMAND
+#define BIF_CFG_DEV0_EPF6_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF6_STATUS
+#define BIF_CFG_DEV0_EPF6_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF6_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_REVISION_ID
+#define BIF_CFG_DEV0_EPF6_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF6_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_SUB_CLASS
+#define BIF_CFG_DEV0_EPF6_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_BASE_CLASS
+#define BIF_CFG_DEV0_EPF6_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_CACHE_LINE
+#define BIF_CFG_DEV0_EPF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_LATENCY
+#define BIF_CFG_DEV0_EPF6_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_HEADER
+#define BIF_CFG_DEV0_EPF6_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF6_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF6_BIST
+#define BIF_CFG_DEV0_EPF6_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF6_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF6_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_CAP_PTR
+#define BIF_CFG_DEV0_EPF6_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_MIN_GRANT
+#define BIF_CFG_DEV0_EPF6_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF6_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF6_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF6_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PMI_CAP
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_SBRN
+#define BIF_CFG_DEV0_EPF6_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_FLADJ
+#define BIF_CFG_DEV0_EPF6_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF6_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF6_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF6_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF6_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF6_LINK_CAP
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_LINK_CNTL
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF6_LINK_STATUS
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF6_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_LINK_CAP2
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF6_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF6_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_MASK
+#define BIF_CFG_DEV0_EPF6_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF6_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_PENDING
+#define BIF_CFG_DEV0_EPF6_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_MSIX_PBA
+#define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_pcie0_bifplr0_cfgdecp
+//BIFPLR0_VENDOR_ID
+#define BIFPLR0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR0_DEVICE_ID
+#define BIFPLR0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR0_COMMAND
+#define BIFPLR0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR0_STATUS
+#define BIFPLR0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR0_REVISION_ID
+#define BIFPLR0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR0_PROG_INTERFACE
+#define BIFPLR0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR0_SUB_CLASS
+#define BIFPLR0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR0_BASE_CLASS
+#define BIFPLR0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR0_CACHE_LINE
+#define BIFPLR0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR0_LATENCY
+#define BIFPLR0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR0_HEADER
+#define BIFPLR0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR0_BIST
+#define BIFPLR0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR0_IO_BASE_LIMIT
+#define BIFPLR0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR0_SECONDARY_STATUS
+#define BIFPLR0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR0_MEM_BASE_LIMIT
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR0_PREF_BASE_LIMIT
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR0_PREF_BASE_UPPER
+#define BIFPLR0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR0_PREF_LIMIT_UPPER
+#define BIFPLR0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR0_IO_BASE_LIMIT_HI
+#define BIFPLR0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR0_CAP_PTR
+#define BIFPLR0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR0_ROM_BASE_ADDR
+#define BIFPLR0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR0_INTERRUPT_LINE
+#define BIFPLR0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR0_INTERRUPT_PIN
+#define BIFPLR0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR0_IRQ_BRIDGE_CNTL
+#define BIFPLR0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR0_EXT_BRIDGE_CNTL
+#define BIFPLR0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR0_VENDOR_CAP_LIST
+#define BIFPLR0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR0_ADAPTER_ID_W
+#define BIFPLR0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR0_PMI_CAP_LIST
+#define BIFPLR0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_PMI_CAP
+#define BIFPLR0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR0_PMI_STATUS_CNTL
+#define BIFPLR0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR0_PCIE_CAP_LIST
+#define BIFPLR0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_PCIE_CAP
+#define BIFPLR0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR0_DEVICE_CAP
+#define BIFPLR0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR0_DEVICE_CNTL
+#define BIFPLR0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR0_DEVICE_STATUS
+#define BIFPLR0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR0_LINK_CAP
+#define BIFPLR0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR0_LINK_CNTL
+#define BIFPLR0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR0_LINK_STATUS
+#define BIFPLR0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR0_SLOT_CAP
+#define BIFPLR0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR0_SLOT_CNTL
+#define BIFPLR0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR0_SLOT_STATUS
+#define BIFPLR0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR0_ROOT_CNTL
+#define BIFPLR0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR0_ROOT_CAP
+#define BIFPLR0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR0_ROOT_STATUS
+#define BIFPLR0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR0_DEVICE_CAP2
+#define BIFPLR0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR0_DEVICE_CNTL2
+#define BIFPLR0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR0_DEVICE_STATUS2
+#define BIFPLR0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_LINK_CAP2
+#define BIFPLR0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR0_LINK_CNTL2
+#define BIFPLR0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR0_LINK_STATUS2
+#define BIFPLR0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR0_SLOT_CAP2
+#define BIFPLR0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_SLOT_CNTL2
+#define BIFPLR0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_SLOT_STATUS2
+#define BIFPLR0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_MSI_CAP_LIST
+#define BIFPLR0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_MSI_MSG_CNTL
+#define BIFPLR0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR0_MSI_MSG_ADDR_LO
+#define BIFPLR0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR0_MSI_MSG_ADDR_HI
+#define BIFPLR0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_MSI_MSG_DATA
+#define BIFPLR0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR0_MSI_MSG_DATA_64
+#define BIFPLR0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR0_SSID_CAP_LIST
+#define BIFPLR0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_SSID_CAP
+#define BIFPLR0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR0_MSI_MAP_CAP_LIST
+#define BIFPLR0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_MSI_MAP_CAP
+#define BIFPLR0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_PCIE_PORT_VC_CNTL
+#define BIFPLR0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR0_PCIE_PORT_VC_STATUS
+#define BIFPLR0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR0_PCIE_CORR_ERR_STATUS
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR0_PCIE_CORR_ERR_MASK
+#define BIFPLR0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR0_PCIE_HDR_LOG0
+#define BIFPLR0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_HDR_LOG1
+#define BIFPLR0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_HDR_LOG2
+#define BIFPLR0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_HDR_LOG3
+#define BIFPLR0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_ROOT_ERR_CMD
+#define BIFPLR0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR0_PCIE_ERR_SRC_ID
+#define BIFPLR0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_PCIE_LINK_CNTL3
+#define BIFPLR0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_PCIE_ACS_CAP
+#define BIFPLR0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR0_PCIE_ACS_CNTL
+#define BIFPLR0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_PCIE_MC_CAP
+#define BIFPLR0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR0_PCIE_MC_CNTL
+#define BIFPLR0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR0_PCIE_MC_ADDR0
+#define BIFPLR0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR0_PCIE_MC_ADDR1
+#define BIFPLR0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_RCV0
+#define BIFPLR0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_RCV1
+#define BIFPLR0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_PCIE_DPC_CAP_LIST
+#define BIFPLR0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR0_PCIE_DPC_CNTL
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR0_PCIE_DPC_STATUS
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR0_PCIE_RP_PIO_STATUS
+#define BIFPLR0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_PCIE_RP_PIO_MASK
+#define BIFPLR0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_ESM_CAP_LIST
+#define BIFPLR0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_PCIE_ESM_HEADER_1
+#define BIFPLR0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR0_PCIE_ESM_HEADER_2
+#define BIFPLR0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR0_PCIE_ESM_STATUS
+#define BIFPLR0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR0_PCIE_ESM_CTRL
+#define BIFPLR0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR0_PCIE_ESM_CAP_1
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR0_PCIE_ESM_CAP_2
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR0_PCIE_ESM_CAP_3
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR0_PCIE_ESM_CAP_4
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR0_PCIE_ESM_CAP_5
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR0_PCIE_ESM_CAP_6
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR0_PCIE_ESM_CAP_7
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_DATA_LINK_FEATURE_CAP
+#define BIFPLR0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_LINK_CAP_16GT
+#define BIFPLR0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_LINK_CNTL_16GT
+#define BIFPLR0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_LINK_STATUS_16GT
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_MARGINING_PORT_CAP
+#define BIFPLR0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR0_MARGINING_PORT_STATUS
+#define BIFPLR0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_PCIE_CCIX_CAP_LIST
+#define BIFPLR0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_PCIE_CCIX_HEADER_1
+#define BIFPLR0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR0_PCIE_CCIX_HEADER_2
+#define BIFPLR0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR0_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR0_PCIE_CCIX_CAP
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr1_cfgdecp
+//BIFPLR1_VENDOR_ID
+#define BIFPLR1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR1_DEVICE_ID
+#define BIFPLR1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR1_COMMAND
+#define BIFPLR1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR1_STATUS
+#define BIFPLR1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR1_REVISION_ID
+#define BIFPLR1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR1_PROG_INTERFACE
+#define BIFPLR1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR1_SUB_CLASS
+#define BIFPLR1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR1_BASE_CLASS
+#define BIFPLR1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR1_CACHE_LINE
+#define BIFPLR1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR1_LATENCY
+#define BIFPLR1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR1_HEADER
+#define BIFPLR1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR1_BIST
+#define BIFPLR1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR1_IO_BASE_LIMIT
+#define BIFPLR1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR1_SECONDARY_STATUS
+#define BIFPLR1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR1_MEM_BASE_LIMIT
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR1_PREF_BASE_LIMIT
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR1_PREF_BASE_UPPER
+#define BIFPLR1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR1_PREF_LIMIT_UPPER
+#define BIFPLR1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR1_IO_BASE_LIMIT_HI
+#define BIFPLR1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR1_CAP_PTR
+#define BIFPLR1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR1_ROM_BASE_ADDR
+#define BIFPLR1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR1_INTERRUPT_LINE
+#define BIFPLR1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR1_INTERRUPT_PIN
+#define BIFPLR1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR1_IRQ_BRIDGE_CNTL
+#define BIFPLR1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR1_EXT_BRIDGE_CNTL
+#define BIFPLR1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR1_VENDOR_CAP_LIST
+#define BIFPLR1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR1_ADAPTER_ID_W
+#define BIFPLR1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR1_PMI_CAP_LIST
+#define BIFPLR1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_PMI_CAP
+#define BIFPLR1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR1_PMI_STATUS_CNTL
+#define BIFPLR1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR1_PCIE_CAP_LIST
+#define BIFPLR1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_PCIE_CAP
+#define BIFPLR1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR1_DEVICE_CAP
+#define BIFPLR1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR1_DEVICE_CNTL
+#define BIFPLR1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR1_DEVICE_STATUS
+#define BIFPLR1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR1_LINK_CAP
+#define BIFPLR1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR1_LINK_CNTL
+#define BIFPLR1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR1_LINK_STATUS
+#define BIFPLR1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR1_SLOT_CAP
+#define BIFPLR1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR1_SLOT_CNTL
+#define BIFPLR1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR1_SLOT_STATUS
+#define BIFPLR1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR1_ROOT_CNTL
+#define BIFPLR1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR1_ROOT_CAP
+#define BIFPLR1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR1_ROOT_STATUS
+#define BIFPLR1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR1_DEVICE_CAP2
+#define BIFPLR1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR1_DEVICE_CNTL2
+#define BIFPLR1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR1_DEVICE_STATUS2
+#define BIFPLR1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_LINK_CAP2
+#define BIFPLR1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR1_LINK_CNTL2
+#define BIFPLR1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR1_LINK_STATUS2
+#define BIFPLR1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR1_SLOT_CAP2
+#define BIFPLR1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_SLOT_CNTL2
+#define BIFPLR1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_SLOT_STATUS2
+#define BIFPLR1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_MSI_CAP_LIST
+#define BIFPLR1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_MSI_MSG_CNTL
+#define BIFPLR1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR1_MSI_MSG_ADDR_LO
+#define BIFPLR1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR1_MSI_MSG_ADDR_HI
+#define BIFPLR1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_MSI_MSG_DATA
+#define BIFPLR1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR1_MSI_MSG_DATA_64
+#define BIFPLR1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR1_SSID_CAP_LIST
+#define BIFPLR1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_SSID_CAP
+#define BIFPLR1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR1_MSI_MAP_CAP_LIST
+#define BIFPLR1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_MSI_MAP_CAP
+#define BIFPLR1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_PCIE_PORT_VC_CNTL
+#define BIFPLR1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR1_PCIE_PORT_VC_STATUS
+#define BIFPLR1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR1_PCIE_CORR_ERR_STATUS
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR1_PCIE_CORR_ERR_MASK
+#define BIFPLR1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR1_PCIE_HDR_LOG0
+#define BIFPLR1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_HDR_LOG1
+#define BIFPLR1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_HDR_LOG2
+#define BIFPLR1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_HDR_LOG3
+#define BIFPLR1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_ROOT_ERR_CMD
+#define BIFPLR1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR1_PCIE_ERR_SRC_ID
+#define BIFPLR1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_PCIE_LINK_CNTL3
+#define BIFPLR1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_PCIE_ACS_CAP
+#define BIFPLR1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR1_PCIE_ACS_CNTL
+#define BIFPLR1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_PCIE_MC_CAP
+#define BIFPLR1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR1_PCIE_MC_CNTL
+#define BIFPLR1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR1_PCIE_MC_ADDR0
+#define BIFPLR1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR1_PCIE_MC_ADDR1
+#define BIFPLR1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_RCV0
+#define BIFPLR1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_RCV1
+#define BIFPLR1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_PCIE_DPC_CAP_LIST
+#define BIFPLR1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR1_PCIE_DPC_CNTL
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR1_PCIE_DPC_STATUS
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR1_PCIE_RP_PIO_STATUS
+#define BIFPLR1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_PCIE_RP_PIO_MASK
+#define BIFPLR1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_ESM_CAP_LIST
+#define BIFPLR1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_PCIE_ESM_HEADER_1
+#define BIFPLR1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR1_PCIE_ESM_HEADER_2
+#define BIFPLR1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR1_PCIE_ESM_STATUS
+#define BIFPLR1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR1_PCIE_ESM_CTRL
+#define BIFPLR1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR1_PCIE_ESM_CAP_1
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR1_PCIE_ESM_CAP_2
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR1_PCIE_ESM_CAP_3
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR1_PCIE_ESM_CAP_4
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR1_PCIE_ESM_CAP_5
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR1_PCIE_ESM_CAP_6
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR1_PCIE_ESM_CAP_7
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_DATA_LINK_FEATURE_CAP
+#define BIFPLR1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_LINK_CAP_16GT
+#define BIFPLR1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_LINK_CNTL_16GT
+#define BIFPLR1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_LINK_STATUS_16GT
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_MARGINING_PORT_CAP
+#define BIFPLR1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR1_MARGINING_PORT_STATUS
+#define BIFPLR1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_PCIE_CCIX_CAP_LIST
+#define BIFPLR1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_PCIE_CCIX_HEADER_1
+#define BIFPLR1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR1_PCIE_CCIX_HEADER_2
+#define BIFPLR1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR1_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR1_PCIE_CCIX_CAP
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr2_cfgdecp
+//BIFPLR2_VENDOR_ID
+#define BIFPLR2_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR2_DEVICE_ID
+#define BIFPLR2_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR2_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR2_COMMAND
+#define BIFPLR2_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR2_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR2_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR2_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR2_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR2_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR2_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR2_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR2_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR2_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR2_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR2_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR2_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR2_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR2_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR2_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR2_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR2_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR2_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR2_STATUS
+#define BIFPLR2_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR2_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR2_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR2_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR2_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR2_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR2_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR2_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR2_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR2_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR2_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR2_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR2_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR2_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR2_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR2_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR2_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR2_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR2_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR2_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR2_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR2_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR2_REVISION_ID
+#define BIFPLR2_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR2_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR2_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR2_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR2_PROG_INTERFACE
+#define BIFPLR2_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR2_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR2_SUB_CLASS
+#define BIFPLR2_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR2_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR2_BASE_CLASS
+#define BIFPLR2_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR2_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR2_CACHE_LINE
+#define BIFPLR2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR2_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR2_LATENCY
+#define BIFPLR2_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR2_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR2_HEADER
+#define BIFPLR2_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR2_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR2_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR2_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR2_BIST
+#define BIFPLR2_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR2_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR2_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR2_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR2_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR2_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR2_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR2_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR2_IO_BASE_LIMIT
+#define BIFPLR2_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR2_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR2_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR2_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR2_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR2_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR2_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR2_SECONDARY_STATUS
+#define BIFPLR2_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR2_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR2_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR2_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR2_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR2_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR2_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR2_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR2_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR2_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR2_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR2_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR2_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR2_MEM_BASE_LIMIT
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR2_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR2_PREF_BASE_LIMIT
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR2_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR2_PREF_BASE_UPPER
+#define BIFPLR2_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR2_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR2_PREF_LIMIT_UPPER
+#define BIFPLR2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR2_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR2_IO_BASE_LIMIT_HI
+#define BIFPLR2_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR2_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR2_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR2_CAP_PTR
+#define BIFPLR2_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR2_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR2_ROM_BASE_ADDR
+#define BIFPLR2_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR2_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR2_INTERRUPT_LINE
+#define BIFPLR2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR2_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR2_INTERRUPT_PIN
+#define BIFPLR2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR2_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR2_IRQ_BRIDGE_CNTL
+#define BIFPLR2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR2_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR2_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR2_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR2_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR2_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR2_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR2_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR2_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR2_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR2_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR2_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR2_EXT_BRIDGE_CNTL
+#define BIFPLR2_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR2_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR2_VENDOR_CAP_LIST
+#define BIFPLR2_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR2_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR2_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR2_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR2_ADAPTER_ID_W
+#define BIFPLR2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR2_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR2_PMI_CAP_LIST
+#define BIFPLR2_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_PMI_CAP
+#define BIFPLR2_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR2_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR2_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR2_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR2_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR2_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR2_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR2_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR2_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR2_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR2_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR2_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR2_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR2_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR2_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR2_PMI_STATUS_CNTL
+#define BIFPLR2_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR2_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR2_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR2_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR2_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR2_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR2_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR2_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR2_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR2_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR2_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR2_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR2_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR2_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR2_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR2_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR2_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR2_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR2_PCIE_CAP_LIST
+#define BIFPLR2_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_PCIE_CAP
+#define BIFPLR2_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR2_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR2_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR2_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR2_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR2_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR2_DEVICE_CAP
+#define BIFPLR2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR2_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR2_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR2_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR2_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR2_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR2_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR2_DEVICE_CNTL
+#define BIFPLR2_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR2_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR2_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR2_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR2_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR2_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR2_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR2_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR2_DEVICE_STATUS
+#define BIFPLR2_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR2_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR2_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR2_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR2_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR2_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR2_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR2_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR2_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR2_LINK_CAP
+#define BIFPLR2_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR2_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR2_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR2_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR2_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR2_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR2_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR2_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR2_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR2_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR2_LINK_CNTL
+#define BIFPLR2_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR2_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR2_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR2_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR2_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR2_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR2_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR2_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR2_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR2_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR2_LINK_STATUS
+#define BIFPLR2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR2_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR2_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR2_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR2_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR2_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR2_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR2_SLOT_CAP
+#define BIFPLR2_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR2_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR2_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR2_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR2_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR2_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR2_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR2_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR2_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR2_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR2_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR2_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR2_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR2_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR2_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR2_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR2_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR2_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR2_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR2_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR2_SLOT_CNTL
+#define BIFPLR2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR2_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR2_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR2_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR2_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR2_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR2_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR2_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR2_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR2_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR2_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR2_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR2_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR2_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR2_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR2_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR2_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR2_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR2_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR2_SLOT_STATUS
+#define BIFPLR2_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR2_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR2_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR2_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR2_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR2_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR2_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR2_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR2_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR2_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR2_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR2_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR2_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR2_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR2_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR2_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR2_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR2_ROOT_CNTL
+#define BIFPLR2_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR2_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR2_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR2_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR2_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR2_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR2_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR2_ROOT_CAP
+#define BIFPLR2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR2_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR2_ROOT_STATUS
+#define BIFPLR2_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR2_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR2_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR2_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR2_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR2_DEVICE_CAP2
+#define BIFPLR2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR2_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR2_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR2_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR2_DEVICE_CNTL2
+#define BIFPLR2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR2_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR2_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR2_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR2_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR2_DEVICE_STATUS2
+#define BIFPLR2_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR2_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_LINK_CAP2
+#define BIFPLR2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR2_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR2_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR2_LINK_CNTL2
+#define BIFPLR2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR2_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR2_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR2_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR2_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR2_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR2_LINK_STATUS2
+#define BIFPLR2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR2_SLOT_CAP2
+#define BIFPLR2_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR2_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_SLOT_CNTL2
+#define BIFPLR2_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR2_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_SLOT_STATUS2
+#define BIFPLR2_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR2_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_MSI_CAP_LIST
+#define BIFPLR2_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_MSI_MSG_CNTL
+#define BIFPLR2_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR2_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR2_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR2_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR2_MSI_MSG_ADDR_LO
+#define BIFPLR2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR2_MSI_MSG_ADDR_HI
+#define BIFPLR2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_MSI_MSG_DATA
+#define BIFPLR2_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR2_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR2_MSI_MSG_DATA_64
+#define BIFPLR2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR2_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR2_SSID_CAP_LIST
+#define BIFPLR2_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_SSID_CAP
+#define BIFPLR2_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR2_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR2_MSI_MAP_CAP_LIST
+#define BIFPLR2_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_MSI_MAP_CAP
+#define BIFPLR2_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR2_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR2_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR2_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR2_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR2_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR2_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR2_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR2_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_PCIE_PORT_VC_CNTL
+#define BIFPLR2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR2_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR2_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR2_PCIE_PORT_VC_STATUS
+#define BIFPLR2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR2_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR2_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR2_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR2_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR2_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR2_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR2_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR2_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR2_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR2_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR2_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR2_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR2_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR2_PCIE_UNCORR_ERR_MASK
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR2_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR2_PCIE_CORR_ERR_STATUS
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR2_PCIE_CORR_ERR_MASK
+#define BIFPLR2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR2_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR2_PCIE_HDR_LOG0
+#define BIFPLR2_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_HDR_LOG1
+#define BIFPLR2_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_HDR_LOG2
+#define BIFPLR2_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_HDR_LOG3
+#define BIFPLR2_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_ROOT_ERR_CMD
+#define BIFPLR2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR2_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR2_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR2_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR2_PCIE_ROOT_ERR_STATUS
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR2_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR2_PCIE_ERR_SRC_ID
+#define BIFPLR2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR2_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR2_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_PCIE_LINK_CNTL3
+#define BIFPLR2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR2_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR2_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR2_PCIE_LANE_ERROR_STATUS
+#define BIFPLR2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR2_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_PCIE_ACS_CAP
+#define BIFPLR2_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR2_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR2_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR2_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR2_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR2_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR2_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR2_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR2_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR2_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR2_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR2_PCIE_ACS_CNTL
+#define BIFPLR2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR2_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR2_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR2_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR2_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR2_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR2_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR2_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR2_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR2_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_PCIE_MC_CAP
+#define BIFPLR2_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR2_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR2_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR2_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR2_PCIE_MC_CNTL
+#define BIFPLR2_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR2_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR2_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR2_PCIE_MC_ADDR0
+#define BIFPLR2_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR2_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR2_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR2_PCIE_MC_ADDR1
+#define BIFPLR2_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_RCV0
+#define BIFPLR2_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_RCV1
+#define BIFPLR2_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_BLOCK_ALL0
+#define BIFPLR2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_BLOCK_ALL1
+#define BIFPLR2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR2_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR2_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR2_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_PCIE_L1_PM_SUB_CAP
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR2_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR2_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR2_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR2_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR2_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR2_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_PCIE_DPC_CAP_LIST
+#define BIFPLR2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR2_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR2_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR2_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR2_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR2_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR2_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR2_PCIE_DPC_CNTL
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR2_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR2_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR2_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR2_PCIE_DPC_STATUS
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR2_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR2_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR2_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR2_PCIE_RP_PIO_STATUS
+#define BIFPLR2_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR2_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_PCIE_RP_PIO_MASK
+#define BIFPLR2_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR2_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_PCIE_RP_PIO_SEVERITY
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_PCIE_RP_PIO_SYSERROR
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_ESM_CAP_LIST
+#define BIFPLR2_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_PCIE_ESM_HEADER_1
+#define BIFPLR2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR2_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR2_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR2_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR2_PCIE_ESM_HEADER_2
+#define BIFPLR2_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR2_PCIE_ESM_STATUS
+#define BIFPLR2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR2_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR2_PCIE_ESM_CTRL
+#define BIFPLR2_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR2_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR2_PCIE_ESM_CAP_1
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR2_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR2_PCIE_ESM_CAP_2
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR2_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR2_PCIE_ESM_CAP_3
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR2_PCIE_ESM_CAP_4
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR2_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR2_PCIE_ESM_CAP_5
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR2_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR2_PCIE_ESM_CAP_6
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR2_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR2_PCIE_ESM_CAP_7
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR2_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR2_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR2_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_DATA_LINK_FEATURE_CAP
+#define BIFPLR2_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR2_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR2_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR2_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR2_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR2_DATA_LINK_FEATURE_STATUS
+#define BIFPLR2_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR2_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR2_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_LINK_CAP_16GT
+#define BIFPLR2_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR2_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_LINK_CNTL_16GT
+#define BIFPLR2_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR2_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_LINK_STATUS_16GT
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR2_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR2_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR2_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR2_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR2_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR2_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_MARGINING_PORT_CAP
+#define BIFPLR2_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR2_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR2_MARGINING_PORT_STATUS
+#define BIFPLR2_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR2_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR2_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR2_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR2_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_PCIE_CCIX_CAP_LIST
+#define BIFPLR2_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_PCIE_CCIX_HEADER_1
+#define BIFPLR2_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR2_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR2_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR2_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR2_PCIE_CCIX_HEADER_2
+#define BIFPLR2_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR2_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR2_PCIE_CCIX_CAP
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR2_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR2_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR2_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR2_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR2_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR2_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_PCIE_CCIX_ESM_STATUS
+#define BIFPLR2_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR2_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR2_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR2_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR2_PCIE_CCIX_ESM_CNTL
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR2_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_PCIE_CCIX_TRANS_CAP
+#define BIFPLR2_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR2_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR2_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR2_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR2_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr3_cfgdecp
+//BIFPLR3_VENDOR_ID
+#define BIFPLR3_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR3_DEVICE_ID
+#define BIFPLR3_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR3_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR3_COMMAND
+#define BIFPLR3_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR3_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR3_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR3_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR3_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR3_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR3_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR3_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR3_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR3_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR3_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR3_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR3_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR3_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR3_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR3_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR3_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR3_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR3_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR3_STATUS
+#define BIFPLR3_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR3_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR3_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR3_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR3_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR3_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR3_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR3_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR3_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR3_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR3_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR3_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR3_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR3_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR3_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR3_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR3_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR3_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR3_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR3_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR3_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR3_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR3_REVISION_ID
+#define BIFPLR3_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR3_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR3_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR3_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR3_PROG_INTERFACE
+#define BIFPLR3_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR3_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR3_SUB_CLASS
+#define BIFPLR3_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR3_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR3_BASE_CLASS
+#define BIFPLR3_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR3_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR3_CACHE_LINE
+#define BIFPLR3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR3_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR3_LATENCY
+#define BIFPLR3_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR3_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR3_HEADER
+#define BIFPLR3_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR3_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR3_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR3_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR3_BIST
+#define BIFPLR3_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR3_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR3_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR3_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR3_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR3_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR3_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR3_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR3_IO_BASE_LIMIT
+#define BIFPLR3_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR3_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR3_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR3_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR3_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR3_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR3_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR3_SECONDARY_STATUS
+#define BIFPLR3_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR3_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR3_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR3_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR3_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR3_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR3_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR3_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR3_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR3_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR3_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR3_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR3_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR3_MEM_BASE_LIMIT
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR3_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR3_PREF_BASE_LIMIT
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR3_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR3_PREF_BASE_UPPER
+#define BIFPLR3_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR3_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR3_PREF_LIMIT_UPPER
+#define BIFPLR3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR3_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR3_IO_BASE_LIMIT_HI
+#define BIFPLR3_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR3_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR3_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR3_CAP_PTR
+#define BIFPLR3_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR3_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR3_ROM_BASE_ADDR
+#define BIFPLR3_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR3_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR3_INTERRUPT_LINE
+#define BIFPLR3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR3_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR3_INTERRUPT_PIN
+#define BIFPLR3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR3_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR3_IRQ_BRIDGE_CNTL
+#define BIFPLR3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR3_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR3_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR3_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR3_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR3_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR3_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR3_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR3_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR3_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR3_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR3_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR3_EXT_BRIDGE_CNTL
+#define BIFPLR3_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR3_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR3_VENDOR_CAP_LIST
+#define BIFPLR3_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR3_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR3_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR3_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR3_ADAPTER_ID_W
+#define BIFPLR3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR3_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR3_PMI_CAP_LIST
+#define BIFPLR3_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_PMI_CAP
+#define BIFPLR3_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR3_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR3_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR3_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR3_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR3_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR3_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR3_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR3_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR3_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR3_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR3_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR3_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR3_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR3_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR3_PMI_STATUS_CNTL
+#define BIFPLR3_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR3_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR3_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR3_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR3_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR3_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR3_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR3_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR3_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR3_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR3_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR3_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR3_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR3_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR3_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR3_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR3_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR3_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR3_PCIE_CAP_LIST
+#define BIFPLR3_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_PCIE_CAP
+#define BIFPLR3_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR3_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR3_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR3_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR3_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR3_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR3_DEVICE_CAP
+#define BIFPLR3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR3_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR3_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR3_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR3_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR3_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR3_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR3_DEVICE_CNTL
+#define BIFPLR3_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR3_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR3_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR3_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR3_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR3_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR3_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR3_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR3_DEVICE_STATUS
+#define BIFPLR3_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR3_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR3_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR3_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR3_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR3_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR3_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR3_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR3_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR3_LINK_CAP
+#define BIFPLR3_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR3_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR3_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR3_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR3_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR3_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR3_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR3_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR3_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR3_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR3_LINK_CNTL
+#define BIFPLR3_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR3_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR3_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR3_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR3_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR3_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR3_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR3_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR3_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR3_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR3_LINK_STATUS
+#define BIFPLR3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR3_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR3_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR3_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR3_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR3_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR3_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR3_SLOT_CAP
+#define BIFPLR3_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR3_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR3_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR3_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR3_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR3_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR3_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR3_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR3_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR3_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR3_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR3_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR3_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR3_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR3_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR3_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR3_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR3_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR3_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR3_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR3_SLOT_CNTL
+#define BIFPLR3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR3_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR3_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR3_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR3_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR3_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR3_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR3_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR3_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR3_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR3_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR3_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR3_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR3_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR3_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR3_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR3_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR3_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR3_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR3_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR3_SLOT_STATUS
+#define BIFPLR3_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR3_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR3_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR3_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR3_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR3_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR3_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR3_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR3_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR3_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR3_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR3_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR3_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR3_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR3_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR3_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR3_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR3_ROOT_CNTL
+#define BIFPLR3_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR3_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR3_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR3_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR3_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR3_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR3_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR3_ROOT_CAP
+#define BIFPLR3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR3_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR3_ROOT_STATUS
+#define BIFPLR3_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR3_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR3_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR3_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR3_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR3_DEVICE_CAP2
+#define BIFPLR3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR3_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR3_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR3_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR3_DEVICE_CNTL2
+#define BIFPLR3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR3_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR3_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR3_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR3_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR3_DEVICE_STATUS2
+#define BIFPLR3_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR3_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_LINK_CAP2
+#define BIFPLR3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR3_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR3_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR3_LINK_CNTL2
+#define BIFPLR3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR3_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR3_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR3_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR3_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR3_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR3_LINK_STATUS2
+#define BIFPLR3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR3_SLOT_CAP2
+#define BIFPLR3_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR3_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_SLOT_CNTL2
+#define BIFPLR3_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR3_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_SLOT_STATUS2
+#define BIFPLR3_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR3_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_MSI_CAP_LIST
+#define BIFPLR3_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_MSI_MSG_CNTL
+#define BIFPLR3_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR3_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR3_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR3_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR3_MSI_MSG_ADDR_LO
+#define BIFPLR3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR3_MSI_MSG_ADDR_HI
+#define BIFPLR3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_MSI_MSG_DATA
+#define BIFPLR3_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR3_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR3_MSI_MSG_DATA_64
+#define BIFPLR3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR3_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR3_SSID_CAP_LIST
+#define BIFPLR3_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_SSID_CAP
+#define BIFPLR3_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR3_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR3_MSI_MAP_CAP_LIST
+#define BIFPLR3_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_MSI_MAP_CAP
+#define BIFPLR3_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR3_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR3_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR3_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR3_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR3_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR3_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR3_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR3_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_PCIE_PORT_VC_CNTL
+#define BIFPLR3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR3_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR3_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR3_PCIE_PORT_VC_STATUS
+#define BIFPLR3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR3_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR3_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR3_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR3_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR3_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR3_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR3_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR3_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR3_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR3_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR3_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR3_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR3_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR3_PCIE_UNCORR_ERR_MASK
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR3_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR3_PCIE_CORR_ERR_STATUS
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR3_PCIE_CORR_ERR_MASK
+#define BIFPLR3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR3_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR3_PCIE_HDR_LOG0
+#define BIFPLR3_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_HDR_LOG1
+#define BIFPLR3_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_HDR_LOG2
+#define BIFPLR3_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_HDR_LOG3
+#define BIFPLR3_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_ROOT_ERR_CMD
+#define BIFPLR3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR3_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR3_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR3_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR3_PCIE_ROOT_ERR_STATUS
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR3_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR3_PCIE_ERR_SRC_ID
+#define BIFPLR3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR3_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR3_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_PCIE_LINK_CNTL3
+#define BIFPLR3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR3_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR3_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR3_PCIE_LANE_ERROR_STATUS
+#define BIFPLR3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR3_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_PCIE_ACS_CAP
+#define BIFPLR3_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR3_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR3_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR3_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR3_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR3_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR3_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR3_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR3_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR3_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR3_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR3_PCIE_ACS_CNTL
+#define BIFPLR3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR3_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR3_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR3_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR3_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR3_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR3_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR3_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR3_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR3_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_PCIE_MC_CAP
+#define BIFPLR3_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR3_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR3_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR3_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR3_PCIE_MC_CNTL
+#define BIFPLR3_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR3_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR3_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR3_PCIE_MC_ADDR0
+#define BIFPLR3_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR3_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR3_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR3_PCIE_MC_ADDR1
+#define BIFPLR3_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_RCV0
+#define BIFPLR3_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_RCV1
+#define BIFPLR3_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_BLOCK_ALL0
+#define BIFPLR3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_BLOCK_ALL1
+#define BIFPLR3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR3_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR3_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR3_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_PCIE_L1_PM_SUB_CAP
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR3_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR3_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR3_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR3_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR3_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR3_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_PCIE_DPC_CAP_LIST
+#define BIFPLR3_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR3_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR3_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR3_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR3_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR3_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR3_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR3_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR3_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR3_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR3_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR3_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR3_PCIE_DPC_CNTL
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR3_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR3_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR3_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR3_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR3_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR3_PCIE_DPC_STATUS
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR3_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR3_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR3_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR3_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR3_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR3_PCIE_RP_PIO_STATUS
+#define BIFPLR3_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR3_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_PCIE_RP_PIO_MASK
+#define BIFPLR3_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR3_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_PCIE_RP_PIO_SEVERITY
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_PCIE_RP_PIO_SYSERROR
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_ESM_CAP_LIST
+#define BIFPLR3_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_PCIE_ESM_HEADER_1
+#define BIFPLR3_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR3_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR3_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR3_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR3_PCIE_ESM_HEADER_2
+#define BIFPLR3_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR3_PCIE_ESM_STATUS
+#define BIFPLR3_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR3_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR3_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR3_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR3_PCIE_ESM_CTRL
+#define BIFPLR3_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR3_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR3_PCIE_ESM_CAP_1
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR3_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR3_PCIE_ESM_CAP_2
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR3_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR3_PCIE_ESM_CAP_3
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR3_PCIE_ESM_CAP_4
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR3_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR3_PCIE_ESM_CAP_5
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR3_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR3_PCIE_ESM_CAP_6
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR3_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR3_PCIE_ESM_CAP_7
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR3_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR3_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR3_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_DATA_LINK_FEATURE_CAP
+#define BIFPLR3_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR3_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR3_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR3_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR3_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR3_DATA_LINK_FEATURE_STATUS
+#define BIFPLR3_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR3_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR3_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_LINK_CAP_16GT
+#define BIFPLR3_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR3_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_LINK_CNTL_16GT
+#define BIFPLR3_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR3_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_LINK_STATUS_16GT
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR3_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR3_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR3_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR3_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR3_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR3_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_MARGINING_PORT_CAP
+#define BIFPLR3_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR3_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR3_MARGINING_PORT_STATUS
+#define BIFPLR3_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR3_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR3_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR3_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR3_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_PCIE_CCIX_CAP_LIST
+#define BIFPLR3_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_PCIE_CCIX_HEADER_1
+#define BIFPLR3_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR3_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR3_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR3_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR3_PCIE_CCIX_HEADER_2
+#define BIFPLR3_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR3_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR3_PCIE_CCIX_CAP
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR3_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR3_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR3_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR3_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR3_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR3_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_PCIE_CCIX_ESM_STATUS
+#define BIFPLR3_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR3_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR3_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR3_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR3_PCIE_CCIX_ESM_CNTL
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR3_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_PCIE_CCIX_TRANS_CAP
+#define BIFPLR3_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR3_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR3_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR3_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR3_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr4_cfgdecp
+//BIFPLR4_VENDOR_ID
+#define BIFPLR4_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR4_DEVICE_ID
+#define BIFPLR4_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR4_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR4_COMMAND
+#define BIFPLR4_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR4_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR4_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR4_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR4_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR4_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR4_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR4_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR4_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR4_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR4_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR4_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR4_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR4_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR4_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR4_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR4_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR4_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR4_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR4_STATUS
+#define BIFPLR4_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR4_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR4_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR4_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR4_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR4_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR4_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR4_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR4_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR4_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR4_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR4_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR4_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR4_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR4_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR4_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR4_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR4_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR4_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR4_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR4_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR4_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR4_REVISION_ID
+#define BIFPLR4_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR4_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR4_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR4_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR4_PROG_INTERFACE
+#define BIFPLR4_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR4_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR4_SUB_CLASS
+#define BIFPLR4_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR4_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR4_BASE_CLASS
+#define BIFPLR4_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR4_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR4_CACHE_LINE
+#define BIFPLR4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR4_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR4_LATENCY
+#define BIFPLR4_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR4_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR4_HEADER
+#define BIFPLR4_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR4_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR4_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR4_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR4_BIST
+#define BIFPLR4_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR4_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR4_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR4_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR4_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR4_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR4_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR4_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR4_IO_BASE_LIMIT
+#define BIFPLR4_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR4_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR4_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR4_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR4_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR4_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR4_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR4_SECONDARY_STATUS
+#define BIFPLR4_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR4_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR4_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR4_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR4_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR4_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR4_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR4_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR4_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR4_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR4_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR4_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR4_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR4_MEM_BASE_LIMIT
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR4_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR4_PREF_BASE_LIMIT
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR4_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR4_PREF_BASE_UPPER
+#define BIFPLR4_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR4_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR4_PREF_LIMIT_UPPER
+#define BIFPLR4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR4_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR4_IO_BASE_LIMIT_HI
+#define BIFPLR4_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR4_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR4_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR4_CAP_PTR
+#define BIFPLR4_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR4_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR4_ROM_BASE_ADDR
+#define BIFPLR4_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR4_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR4_INTERRUPT_LINE
+#define BIFPLR4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR4_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR4_INTERRUPT_PIN
+#define BIFPLR4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR4_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR4_IRQ_BRIDGE_CNTL
+#define BIFPLR4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR4_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR4_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR4_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR4_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR4_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR4_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR4_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR4_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR4_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR4_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR4_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR4_EXT_BRIDGE_CNTL
+#define BIFPLR4_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR4_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR4_VENDOR_CAP_LIST
+#define BIFPLR4_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR4_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR4_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR4_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR4_ADAPTER_ID_W
+#define BIFPLR4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR4_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR4_PMI_CAP_LIST
+#define BIFPLR4_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_PMI_CAP
+#define BIFPLR4_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR4_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR4_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR4_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR4_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR4_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR4_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR4_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR4_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR4_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR4_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR4_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR4_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR4_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR4_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR4_PMI_STATUS_CNTL
+#define BIFPLR4_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR4_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR4_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR4_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR4_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR4_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR4_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR4_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR4_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR4_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR4_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR4_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR4_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR4_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR4_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR4_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR4_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR4_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR4_PCIE_CAP_LIST
+#define BIFPLR4_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_PCIE_CAP
+#define BIFPLR4_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR4_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR4_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR4_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR4_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR4_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR4_DEVICE_CAP
+#define BIFPLR4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR4_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR4_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR4_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR4_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR4_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR4_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR4_DEVICE_CNTL
+#define BIFPLR4_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR4_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR4_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR4_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR4_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR4_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR4_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR4_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR4_DEVICE_STATUS
+#define BIFPLR4_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR4_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR4_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR4_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR4_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR4_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR4_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR4_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR4_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR4_LINK_CAP
+#define BIFPLR4_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR4_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR4_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR4_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR4_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR4_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR4_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR4_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR4_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR4_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR4_LINK_CNTL
+#define BIFPLR4_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR4_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR4_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR4_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR4_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR4_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR4_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR4_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR4_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR4_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR4_LINK_STATUS
+#define BIFPLR4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR4_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR4_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR4_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR4_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR4_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR4_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR4_SLOT_CAP
+#define BIFPLR4_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR4_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR4_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR4_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR4_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR4_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR4_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR4_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR4_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR4_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR4_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR4_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR4_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR4_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR4_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR4_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR4_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR4_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR4_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR4_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR4_SLOT_CNTL
+#define BIFPLR4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR4_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR4_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR4_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR4_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR4_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR4_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR4_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR4_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR4_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR4_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR4_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR4_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR4_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR4_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR4_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR4_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR4_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR4_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR4_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR4_SLOT_STATUS
+#define BIFPLR4_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR4_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR4_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR4_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR4_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR4_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR4_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR4_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR4_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR4_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR4_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR4_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR4_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR4_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR4_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR4_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR4_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR4_ROOT_CNTL
+#define BIFPLR4_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR4_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR4_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR4_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR4_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR4_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR4_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR4_ROOT_CAP
+#define BIFPLR4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR4_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR4_ROOT_STATUS
+#define BIFPLR4_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR4_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR4_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR4_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR4_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR4_DEVICE_CAP2
+#define BIFPLR4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR4_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR4_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR4_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR4_DEVICE_CNTL2
+#define BIFPLR4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR4_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR4_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR4_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR4_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR4_DEVICE_STATUS2
+#define BIFPLR4_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR4_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_LINK_CAP2
+#define BIFPLR4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR4_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR4_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR4_LINK_CNTL2
+#define BIFPLR4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR4_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR4_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR4_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR4_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR4_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR4_LINK_STATUS2
+#define BIFPLR4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR4_SLOT_CAP2
+#define BIFPLR4_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR4_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_SLOT_CNTL2
+#define BIFPLR4_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR4_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_SLOT_STATUS2
+#define BIFPLR4_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR4_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_MSI_CAP_LIST
+#define BIFPLR4_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_MSI_MSG_CNTL
+#define BIFPLR4_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR4_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR4_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR4_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR4_MSI_MSG_ADDR_LO
+#define BIFPLR4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR4_MSI_MSG_ADDR_HI
+#define BIFPLR4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_MSI_MSG_DATA
+#define BIFPLR4_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR4_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR4_MSI_MSG_DATA_64
+#define BIFPLR4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR4_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR4_SSID_CAP_LIST
+#define BIFPLR4_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_SSID_CAP
+#define BIFPLR4_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR4_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR4_MSI_MAP_CAP_LIST
+#define BIFPLR4_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_MSI_MAP_CAP
+#define BIFPLR4_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR4_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR4_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR4_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR4_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR4_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR4_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR4_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR4_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_PCIE_PORT_VC_CNTL
+#define BIFPLR4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR4_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR4_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR4_PCIE_PORT_VC_STATUS
+#define BIFPLR4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR4_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR4_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR4_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR4_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR4_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR4_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR4_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR4_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR4_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR4_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR4_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR4_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR4_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR4_PCIE_UNCORR_ERR_MASK
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR4_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR4_PCIE_CORR_ERR_STATUS
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR4_PCIE_CORR_ERR_MASK
+#define BIFPLR4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR4_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR4_PCIE_HDR_LOG0
+#define BIFPLR4_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_HDR_LOG1
+#define BIFPLR4_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_HDR_LOG2
+#define BIFPLR4_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_HDR_LOG3
+#define BIFPLR4_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_ROOT_ERR_CMD
+#define BIFPLR4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR4_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR4_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR4_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR4_PCIE_ROOT_ERR_STATUS
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR4_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR4_PCIE_ERR_SRC_ID
+#define BIFPLR4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR4_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR4_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_PCIE_LINK_CNTL3
+#define BIFPLR4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR4_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR4_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR4_PCIE_LANE_ERROR_STATUS
+#define BIFPLR4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR4_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_PCIE_ACS_CAP
+#define BIFPLR4_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR4_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR4_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR4_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR4_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR4_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR4_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR4_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR4_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR4_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR4_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR4_PCIE_ACS_CNTL
+#define BIFPLR4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR4_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR4_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR4_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR4_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR4_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR4_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR4_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR4_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR4_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_PCIE_MC_CAP
+#define BIFPLR4_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR4_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR4_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR4_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR4_PCIE_MC_CNTL
+#define BIFPLR4_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR4_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR4_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR4_PCIE_MC_ADDR0
+#define BIFPLR4_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR4_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR4_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR4_PCIE_MC_ADDR1
+#define BIFPLR4_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_RCV0
+#define BIFPLR4_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_RCV1
+#define BIFPLR4_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_BLOCK_ALL0
+#define BIFPLR4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_BLOCK_ALL1
+#define BIFPLR4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR4_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR4_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR4_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_PCIE_L1_PM_SUB_CAP
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR4_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR4_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR4_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR4_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR4_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR4_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_PCIE_DPC_CAP_LIST
+#define BIFPLR4_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR4_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR4_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR4_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR4_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR4_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR4_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR4_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR4_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR4_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR4_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR4_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR4_PCIE_DPC_CNTL
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR4_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR4_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR4_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR4_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR4_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR4_PCIE_DPC_STATUS
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR4_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR4_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR4_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR4_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR4_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR4_PCIE_RP_PIO_STATUS
+#define BIFPLR4_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR4_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_PCIE_RP_PIO_MASK
+#define BIFPLR4_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR4_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_PCIE_RP_PIO_SEVERITY
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_PCIE_RP_PIO_SYSERROR
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_ESM_CAP_LIST
+#define BIFPLR4_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_PCIE_ESM_HEADER_1
+#define BIFPLR4_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR4_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR4_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR4_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR4_PCIE_ESM_HEADER_2
+#define BIFPLR4_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR4_PCIE_ESM_STATUS
+#define BIFPLR4_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR4_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR4_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR4_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR4_PCIE_ESM_CTRL
+#define BIFPLR4_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR4_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR4_PCIE_ESM_CAP_1
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR4_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR4_PCIE_ESM_CAP_2
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR4_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR4_PCIE_ESM_CAP_3
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR4_PCIE_ESM_CAP_4
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR4_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR4_PCIE_ESM_CAP_5
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR4_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR4_PCIE_ESM_CAP_6
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR4_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR4_PCIE_ESM_CAP_7
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR4_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR4_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR4_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_DATA_LINK_FEATURE_CAP
+#define BIFPLR4_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR4_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR4_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR4_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR4_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR4_DATA_LINK_FEATURE_STATUS
+#define BIFPLR4_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR4_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR4_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_LINK_CAP_16GT
+#define BIFPLR4_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR4_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_LINK_CNTL_16GT
+#define BIFPLR4_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR4_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_LINK_STATUS_16GT
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR4_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR4_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR4_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR4_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR4_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR4_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_MARGINING_PORT_CAP
+#define BIFPLR4_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR4_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR4_MARGINING_PORT_STATUS
+#define BIFPLR4_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR4_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR4_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR4_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR4_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_PCIE_CCIX_CAP_LIST
+#define BIFPLR4_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_PCIE_CCIX_HEADER_1
+#define BIFPLR4_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR4_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR4_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR4_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR4_PCIE_CCIX_HEADER_2
+#define BIFPLR4_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR4_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR4_PCIE_CCIX_CAP
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR4_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR4_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR4_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR4_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR4_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR4_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_PCIE_CCIX_ESM_STATUS
+#define BIFPLR4_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR4_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR4_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR4_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR4_PCIE_CCIX_ESM_CNTL
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR4_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_PCIE_CCIX_TRANS_CAP
+#define BIFPLR4_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR4_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR4_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR4_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR4_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr5_cfgdecp
+//BIFPLR5_VENDOR_ID
+#define BIFPLR5_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR5_DEVICE_ID
+#define BIFPLR5_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR5_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR5_COMMAND
+#define BIFPLR5_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR5_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR5_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR5_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR5_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR5_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR5_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR5_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR5_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR5_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR5_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR5_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR5_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR5_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR5_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR5_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR5_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR5_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR5_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR5_STATUS
+#define BIFPLR5_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR5_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR5_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR5_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR5_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR5_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR5_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR5_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR5_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR5_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR5_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR5_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR5_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR5_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR5_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR5_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR5_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR5_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR5_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR5_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR5_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR5_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR5_REVISION_ID
+#define BIFPLR5_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR5_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR5_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR5_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR5_PROG_INTERFACE
+#define BIFPLR5_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR5_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR5_SUB_CLASS
+#define BIFPLR5_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR5_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR5_BASE_CLASS
+#define BIFPLR5_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR5_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR5_CACHE_LINE
+#define BIFPLR5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR5_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR5_LATENCY
+#define BIFPLR5_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR5_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR5_HEADER
+#define BIFPLR5_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR5_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR5_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR5_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR5_BIST
+#define BIFPLR5_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR5_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR5_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR5_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR5_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR5_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR5_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR5_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR5_IO_BASE_LIMIT
+#define BIFPLR5_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR5_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR5_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR5_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR5_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR5_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR5_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR5_SECONDARY_STATUS
+#define BIFPLR5_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR5_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR5_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR5_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR5_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR5_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR5_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR5_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR5_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR5_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR5_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR5_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR5_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR5_MEM_BASE_LIMIT
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR5_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR5_PREF_BASE_LIMIT
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR5_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR5_PREF_BASE_UPPER
+#define BIFPLR5_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR5_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR5_PREF_LIMIT_UPPER
+#define BIFPLR5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR5_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR5_IO_BASE_LIMIT_HI
+#define BIFPLR5_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR5_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR5_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR5_CAP_PTR
+#define BIFPLR5_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR5_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR5_ROM_BASE_ADDR
+#define BIFPLR5_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR5_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR5_INTERRUPT_LINE
+#define BIFPLR5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR5_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR5_INTERRUPT_PIN
+#define BIFPLR5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR5_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR5_IRQ_BRIDGE_CNTL
+#define BIFPLR5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR5_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR5_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR5_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR5_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR5_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR5_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR5_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR5_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR5_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR5_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR5_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR5_EXT_BRIDGE_CNTL
+#define BIFPLR5_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR5_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR5_VENDOR_CAP_LIST
+#define BIFPLR5_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR5_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR5_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR5_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR5_ADAPTER_ID_W
+#define BIFPLR5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR5_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR5_PMI_CAP_LIST
+#define BIFPLR5_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_PMI_CAP
+#define BIFPLR5_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR5_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR5_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR5_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR5_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR5_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR5_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR5_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR5_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR5_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR5_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR5_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR5_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR5_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR5_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR5_PMI_STATUS_CNTL
+#define BIFPLR5_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR5_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR5_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR5_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR5_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR5_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR5_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR5_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR5_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR5_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR5_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR5_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR5_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR5_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR5_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR5_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR5_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR5_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR5_PCIE_CAP_LIST
+#define BIFPLR5_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_PCIE_CAP
+#define BIFPLR5_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR5_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR5_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR5_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR5_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR5_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR5_DEVICE_CAP
+#define BIFPLR5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR5_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR5_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR5_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR5_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR5_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR5_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR5_DEVICE_CNTL
+#define BIFPLR5_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR5_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR5_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR5_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR5_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR5_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR5_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR5_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR5_DEVICE_STATUS
+#define BIFPLR5_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR5_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR5_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR5_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR5_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR5_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR5_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR5_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR5_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR5_LINK_CAP
+#define BIFPLR5_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR5_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR5_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR5_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR5_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR5_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR5_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR5_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR5_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR5_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR5_LINK_CNTL
+#define BIFPLR5_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR5_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR5_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR5_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR5_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR5_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR5_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR5_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR5_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR5_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR5_LINK_STATUS
+#define BIFPLR5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR5_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR5_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR5_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR5_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR5_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR5_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR5_SLOT_CAP
+#define BIFPLR5_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR5_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR5_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR5_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR5_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR5_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR5_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR5_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR5_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR5_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR5_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR5_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR5_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR5_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR5_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR5_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR5_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR5_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR5_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR5_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR5_SLOT_CNTL
+#define BIFPLR5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR5_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR5_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR5_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR5_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR5_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR5_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR5_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR5_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR5_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR5_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR5_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR5_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR5_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR5_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR5_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR5_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR5_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR5_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR5_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR5_SLOT_STATUS
+#define BIFPLR5_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR5_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR5_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR5_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR5_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR5_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR5_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR5_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR5_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR5_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR5_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR5_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR5_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR5_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR5_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR5_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR5_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR5_ROOT_CNTL
+#define BIFPLR5_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR5_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR5_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR5_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR5_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR5_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR5_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR5_ROOT_CAP
+#define BIFPLR5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR5_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR5_ROOT_STATUS
+#define BIFPLR5_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR5_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR5_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR5_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR5_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR5_DEVICE_CAP2
+#define BIFPLR5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR5_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR5_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR5_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR5_DEVICE_CNTL2
+#define BIFPLR5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR5_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR5_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR5_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR5_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR5_DEVICE_STATUS2
+#define BIFPLR5_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR5_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_LINK_CAP2
+#define BIFPLR5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR5_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR5_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR5_LINK_CNTL2
+#define BIFPLR5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR5_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR5_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR5_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR5_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR5_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR5_LINK_STATUS2
+#define BIFPLR5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR5_SLOT_CAP2
+#define BIFPLR5_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR5_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_SLOT_CNTL2
+#define BIFPLR5_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR5_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_SLOT_STATUS2
+#define BIFPLR5_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR5_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_MSI_CAP_LIST
+#define BIFPLR5_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_MSI_MSG_CNTL
+#define BIFPLR5_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR5_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR5_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR5_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR5_MSI_MSG_ADDR_LO
+#define BIFPLR5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR5_MSI_MSG_ADDR_HI
+#define BIFPLR5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_MSI_MSG_DATA
+#define BIFPLR5_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR5_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR5_MSI_MSG_DATA_64
+#define BIFPLR5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR5_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR5_SSID_CAP_LIST
+#define BIFPLR5_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_SSID_CAP
+#define BIFPLR5_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR5_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR5_MSI_MAP_CAP_LIST
+#define BIFPLR5_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_MSI_MAP_CAP
+#define BIFPLR5_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR5_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR5_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR5_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR5_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR5_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR5_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR5_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR5_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_PCIE_PORT_VC_CNTL
+#define BIFPLR5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR5_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR5_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR5_PCIE_PORT_VC_STATUS
+#define BIFPLR5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR5_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR5_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR5_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR5_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR5_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR5_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR5_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR5_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR5_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR5_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR5_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR5_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR5_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR5_PCIE_UNCORR_ERR_MASK
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR5_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR5_PCIE_CORR_ERR_STATUS
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR5_PCIE_CORR_ERR_MASK
+#define BIFPLR5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR5_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR5_PCIE_HDR_LOG0
+#define BIFPLR5_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_HDR_LOG1
+#define BIFPLR5_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_HDR_LOG2
+#define BIFPLR5_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_HDR_LOG3
+#define BIFPLR5_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_ROOT_ERR_CMD
+#define BIFPLR5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR5_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR5_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR5_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR5_PCIE_ROOT_ERR_STATUS
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR5_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR5_PCIE_ERR_SRC_ID
+#define BIFPLR5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR5_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR5_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_PCIE_LINK_CNTL3
+#define BIFPLR5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR5_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR5_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR5_PCIE_LANE_ERROR_STATUS
+#define BIFPLR5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR5_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_PCIE_ACS_CAP
+#define BIFPLR5_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR5_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR5_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR5_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR5_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR5_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR5_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR5_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR5_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR5_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR5_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR5_PCIE_ACS_CNTL
+#define BIFPLR5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR5_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR5_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR5_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR5_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR5_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR5_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR5_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR5_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR5_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_PCIE_MC_CAP
+#define BIFPLR5_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR5_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR5_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR5_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR5_PCIE_MC_CNTL
+#define BIFPLR5_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR5_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR5_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR5_PCIE_MC_ADDR0
+#define BIFPLR5_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR5_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR5_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR5_PCIE_MC_ADDR1
+#define BIFPLR5_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_RCV0
+#define BIFPLR5_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_RCV1
+#define BIFPLR5_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_BLOCK_ALL0
+#define BIFPLR5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_BLOCK_ALL1
+#define BIFPLR5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR5_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR5_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR5_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_PCIE_L1_PM_SUB_CAP
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR5_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR5_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR5_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR5_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR5_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR5_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_PCIE_DPC_CAP_LIST
+#define BIFPLR5_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR5_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR5_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR5_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR5_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR5_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR5_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR5_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR5_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR5_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR5_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR5_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR5_PCIE_DPC_CNTL
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR5_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR5_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR5_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR5_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR5_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR5_PCIE_DPC_STATUS
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR5_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR5_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR5_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR5_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR5_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR5_PCIE_RP_PIO_STATUS
+#define BIFPLR5_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR5_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_PCIE_RP_PIO_MASK
+#define BIFPLR5_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR5_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_PCIE_RP_PIO_SEVERITY
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_PCIE_RP_PIO_SYSERROR
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_ESM_CAP_LIST
+#define BIFPLR5_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_PCIE_ESM_HEADER_1
+#define BIFPLR5_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR5_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR5_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR5_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR5_PCIE_ESM_HEADER_2
+#define BIFPLR5_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR5_PCIE_ESM_STATUS
+#define BIFPLR5_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR5_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR5_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR5_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR5_PCIE_ESM_CTRL
+#define BIFPLR5_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR5_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR5_PCIE_ESM_CAP_1
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR5_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR5_PCIE_ESM_CAP_2
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR5_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR5_PCIE_ESM_CAP_3
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR5_PCIE_ESM_CAP_4
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR5_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR5_PCIE_ESM_CAP_5
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR5_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR5_PCIE_ESM_CAP_6
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR5_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR5_PCIE_ESM_CAP_7
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR5_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR5_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR5_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_DATA_LINK_FEATURE_CAP
+#define BIFPLR5_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR5_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR5_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR5_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR5_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR5_DATA_LINK_FEATURE_STATUS
+#define BIFPLR5_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR5_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR5_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_LINK_CAP_16GT
+#define BIFPLR5_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR5_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_LINK_CNTL_16GT
+#define BIFPLR5_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR5_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_LINK_STATUS_16GT
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR5_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR5_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR5_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR5_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR5_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR5_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_MARGINING_PORT_CAP
+#define BIFPLR5_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR5_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR5_MARGINING_PORT_STATUS
+#define BIFPLR5_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR5_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR5_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR5_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR5_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_PCIE_CCIX_CAP_LIST
+#define BIFPLR5_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_PCIE_CCIX_HEADER_1
+#define BIFPLR5_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR5_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR5_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR5_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR5_PCIE_CCIX_HEADER_2
+#define BIFPLR5_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR5_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR5_PCIE_CCIX_CAP
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR5_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR5_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR5_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR5_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR5_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR5_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_PCIE_CCIX_ESM_STATUS
+#define BIFPLR5_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR5_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR5_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR5_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR5_PCIE_CCIX_ESM_CNTL
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR5_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_PCIE_CCIX_TRANS_CAP
+#define BIFPLR5_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR5_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR5_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR5_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR5_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr6_cfgdecp
+//BIFPLR6_VENDOR_ID
+#define BIFPLR6_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR6_DEVICE_ID
+#define BIFPLR6_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR6_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR6_COMMAND
+#define BIFPLR6_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR6_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR6_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR6_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR6_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR6_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR6_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR6_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR6_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR6_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR6_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR6_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR6_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR6_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR6_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR6_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR6_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR6_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR6_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR6_STATUS
+#define BIFPLR6_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR6_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR6_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR6_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR6_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR6_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR6_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR6_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR6_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR6_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR6_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR6_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR6_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR6_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR6_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR6_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR6_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR6_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR6_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR6_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR6_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR6_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR6_REVISION_ID
+#define BIFPLR6_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR6_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR6_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR6_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR6_PROG_INTERFACE
+#define BIFPLR6_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR6_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR6_SUB_CLASS
+#define BIFPLR6_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR6_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR6_BASE_CLASS
+#define BIFPLR6_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR6_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR6_CACHE_LINE
+#define BIFPLR6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR6_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR6_LATENCY
+#define BIFPLR6_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR6_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR6_HEADER
+#define BIFPLR6_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR6_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR6_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR6_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR6_BIST
+#define BIFPLR6_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR6_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR6_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR6_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR6_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR6_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR6_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR6_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR6_IO_BASE_LIMIT
+#define BIFPLR6_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR6_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR6_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR6_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR6_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR6_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR6_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR6_SECONDARY_STATUS
+#define BIFPLR6_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR6_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR6_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR6_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR6_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR6_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR6_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR6_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR6_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR6_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR6_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR6_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR6_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR6_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR6_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR6_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR6_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR6_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR6_MEM_BASE_LIMIT
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR6_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR6_PREF_BASE_LIMIT
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR6_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR6_PREF_BASE_UPPER
+#define BIFPLR6_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR6_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR6_PREF_LIMIT_UPPER
+#define BIFPLR6_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR6_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR6_IO_BASE_LIMIT_HI
+#define BIFPLR6_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR6_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR6_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR6_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR6_CAP_PTR
+#define BIFPLR6_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR6_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR6_ROM_BASE_ADDR
+#define BIFPLR6_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR6_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR6_INTERRUPT_LINE
+#define BIFPLR6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR6_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR6_INTERRUPT_PIN
+#define BIFPLR6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR6_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR6_IRQ_BRIDGE_CNTL
+#define BIFPLR6_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR6_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR6_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR6_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR6_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR6_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR6_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR6_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR6_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR6_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR6_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR6_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR6_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR6_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR6_EXT_BRIDGE_CNTL
+#define BIFPLR6_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR6_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR6_VENDOR_CAP_LIST
+#define BIFPLR6_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR6_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR6_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR6_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR6_ADAPTER_ID_W
+#define BIFPLR6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR6_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR6_PMI_CAP_LIST
+#define BIFPLR6_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_PMI_CAP
+#define BIFPLR6_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR6_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR6_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR6_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR6_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR6_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR6_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR6_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR6_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR6_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR6_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR6_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR6_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR6_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR6_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR6_PMI_STATUS_CNTL
+#define BIFPLR6_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR6_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR6_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR6_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR6_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR6_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR6_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR6_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR6_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR6_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR6_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR6_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR6_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR6_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR6_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR6_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR6_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR6_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR6_PCIE_CAP_LIST
+#define BIFPLR6_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_PCIE_CAP
+#define BIFPLR6_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR6_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR6_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR6_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR6_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR6_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR6_DEVICE_CAP
+#define BIFPLR6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR6_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR6_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR6_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR6_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR6_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR6_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR6_DEVICE_CNTL
+#define BIFPLR6_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR6_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR6_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR6_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR6_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR6_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR6_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR6_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR6_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR6_DEVICE_STATUS
+#define BIFPLR6_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR6_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR6_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR6_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR6_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR6_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR6_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR6_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR6_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR6_LINK_CAP
+#define BIFPLR6_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR6_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR6_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR6_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR6_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR6_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR6_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR6_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR6_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR6_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR6_LINK_CNTL
+#define BIFPLR6_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR6_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR6_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR6_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR6_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR6_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR6_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR6_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR6_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR6_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR6_LINK_STATUS
+#define BIFPLR6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR6_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR6_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR6_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR6_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR6_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR6_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR6_SLOT_CAP
+#define BIFPLR6_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR6_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR6_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR6_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR6_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR6_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR6_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR6_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR6_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR6_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR6_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR6_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR6_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR6_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR6_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR6_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR6_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR6_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR6_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR6_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR6_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR6_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR6_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR6_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR6_SLOT_CNTL
+#define BIFPLR6_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR6_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR6_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR6_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR6_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR6_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR6_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR6_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR6_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR6_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR6_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR6_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR6_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR6_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR6_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR6_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR6_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR6_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR6_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR6_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR6_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR6_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR6_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR6_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR6_SLOT_STATUS
+#define BIFPLR6_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR6_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR6_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR6_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR6_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR6_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR6_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR6_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR6_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR6_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR6_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR6_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR6_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR6_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR6_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR6_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR6_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR6_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR6_ROOT_CNTL
+#define BIFPLR6_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR6_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR6_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR6_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR6_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR6_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR6_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR6_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR6_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR6_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR6_ROOT_CAP
+#define BIFPLR6_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR6_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR6_ROOT_STATUS
+#define BIFPLR6_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR6_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR6_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR6_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR6_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR6_DEVICE_CAP2
+#define BIFPLR6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR6_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR6_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR6_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR6_DEVICE_CNTL2
+#define BIFPLR6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR6_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR6_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR6_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR6_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR6_DEVICE_STATUS2
+#define BIFPLR6_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR6_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_LINK_CAP2
+#define BIFPLR6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR6_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR6_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR6_LINK_CNTL2
+#define BIFPLR6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR6_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR6_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR6_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR6_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR6_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR6_LINK_STATUS2
+#define BIFPLR6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR6_SLOT_CAP2
+#define BIFPLR6_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR6_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_SLOT_CNTL2
+#define BIFPLR6_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR6_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_SLOT_STATUS2
+#define BIFPLR6_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR6_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_MSI_CAP_LIST
+#define BIFPLR6_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_MSI_MSG_CNTL
+#define BIFPLR6_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR6_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR6_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR6_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR6_MSI_MSG_ADDR_LO
+#define BIFPLR6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR6_MSI_MSG_ADDR_HI
+#define BIFPLR6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_MSI_MSG_DATA
+#define BIFPLR6_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR6_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR6_MSI_MSG_DATA_64
+#define BIFPLR6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR6_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR6_SSID_CAP_LIST
+#define BIFPLR6_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_SSID_CAP
+#define BIFPLR6_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR6_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR6_MSI_MAP_CAP_LIST
+#define BIFPLR6_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_MSI_MAP_CAP
+#define BIFPLR6_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR6_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR6_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR6_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR6_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR6_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR6_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR6_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR6_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_PCIE_PORT_VC_CNTL
+#define BIFPLR6_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR6_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR6_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR6_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR6_PCIE_PORT_VC_STATUS
+#define BIFPLR6_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR6_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR6_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR6_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR6_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR6_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR6_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR6_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR6_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR6_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR6_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR6_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR6_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR6_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR6_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR6_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR6_PCIE_UNCORR_ERR_MASK
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR6_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR6_PCIE_CORR_ERR_STATUS
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR6_PCIE_CORR_ERR_MASK
+#define BIFPLR6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR6_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR6_PCIE_HDR_LOG0
+#define BIFPLR6_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_HDR_LOG1
+#define BIFPLR6_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_HDR_LOG2
+#define BIFPLR6_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_HDR_LOG3
+#define BIFPLR6_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_ROOT_ERR_CMD
+#define BIFPLR6_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR6_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR6_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR6_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR6_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR6_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR6_PCIE_ROOT_ERR_STATUS
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR6_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR6_PCIE_ERR_SRC_ID
+#define BIFPLR6_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR6_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR6_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_PCIE_LINK_CNTL3
+#define BIFPLR6_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR6_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR6_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR6_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR6_PCIE_LANE_ERROR_STATUS
+#define BIFPLR6_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR6_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_PCIE_ACS_CAP
+#define BIFPLR6_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR6_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR6_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR6_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR6_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR6_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR6_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR6_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR6_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR6_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR6_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR6_PCIE_ACS_CNTL
+#define BIFPLR6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR6_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR6_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR6_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR6_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR6_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR6_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR6_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR6_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR6_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_PCIE_MC_CAP
+#define BIFPLR6_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR6_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR6_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR6_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR6_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR6_PCIE_MC_CNTL
+#define BIFPLR6_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR6_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR6_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR6_PCIE_MC_ADDR0
+#define BIFPLR6_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR6_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR6_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR6_PCIE_MC_ADDR1
+#define BIFPLR6_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_RCV0
+#define BIFPLR6_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_RCV1
+#define BIFPLR6_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_BLOCK_ALL0
+#define BIFPLR6_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_BLOCK_ALL1
+#define BIFPLR6_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR6_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR6_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR6_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR6_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR6_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR6_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_PCIE_L1_PM_SUB_CAP
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR6_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR6_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR6_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR6_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR6_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR6_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_PCIE_DPC_CAP_LIST
+#define BIFPLR6_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR6_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR6_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR6_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR6_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR6_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR6_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR6_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR6_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR6_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR6_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR6_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR6_PCIE_DPC_CNTL
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR6_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR6_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR6_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR6_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR6_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR6_PCIE_DPC_STATUS
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR6_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR6_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR6_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR6_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR6_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR6_PCIE_RP_PIO_STATUS
+#define BIFPLR6_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR6_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_PCIE_RP_PIO_MASK
+#define BIFPLR6_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR6_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_PCIE_RP_PIO_SEVERITY
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_PCIE_RP_PIO_SYSERROR
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_ESM_CAP_LIST
+#define BIFPLR6_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_PCIE_ESM_HEADER_1
+#define BIFPLR6_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR6_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR6_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR6_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR6_PCIE_ESM_HEADER_2
+#define BIFPLR6_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR6_PCIE_ESM_STATUS
+#define BIFPLR6_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR6_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR6_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR6_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR6_PCIE_ESM_CTRL
+#define BIFPLR6_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR6_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR6_PCIE_ESM_CAP_1
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR6_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR6_PCIE_ESM_CAP_2
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR6_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR6_PCIE_ESM_CAP_3
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR6_PCIE_ESM_CAP_4
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR6_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR6_PCIE_ESM_CAP_5
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR6_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR6_PCIE_ESM_CAP_6
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR6_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR6_PCIE_ESM_CAP_7
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR6_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR6_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR6_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_DATA_LINK_FEATURE_CAP
+#define BIFPLR6_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR6_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR6_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR6_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR6_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR6_DATA_LINK_FEATURE_STATUS
+#define BIFPLR6_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR6_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR6_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_LINK_CAP_16GT
+#define BIFPLR6_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR6_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_LINK_CNTL_16GT
+#define BIFPLR6_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR6_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_LINK_STATUS_16GT
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR6_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR6_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR6_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR6_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR6_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR6_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR6_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_MARGINING_PORT_CAP
+#define BIFPLR6_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR6_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR6_MARGINING_PORT_STATUS
+#define BIFPLR6_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR6_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR6_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR6_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR6_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_PCIE_CCIX_CAP_LIST
+#define BIFPLR6_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_PCIE_CCIX_HEADER_1
+#define BIFPLR6_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR6_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR6_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR6_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR6_PCIE_CCIX_HEADER_2
+#define BIFPLR6_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR6_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR6_PCIE_CCIX_CAP
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR6_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR6_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR6_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR6_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR6_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR6_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_PCIE_CCIX_ESM_STATUS
+#define BIFPLR6_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR6_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR6_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR6_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR6_PCIE_CCIX_ESM_CNTL
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR6_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_PCIE_CCIX_TRANS_CAP
+#define BIFPLR6_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR6_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR6_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR6_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR6_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1
+//BIF_BX_PF0_MM_INDEX
+#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_PF0_MM_DATA
+#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_MM_INDEX_HI
+#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_RSMU_INDEX
+#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT 0x0
+#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_RSMU_DATA
+#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT 0x0
+#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC:1
+//BIF_BX0_PCIE_INDEX
+#define BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX0_PCIE_DATA
+#define BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define BIF_BX0_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL
+//BIF_BX0_PCIE_INDEX2
+#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
+#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL
+//BIF_BX0_PCIE_DATA2
+#define BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
+#define BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_0
+#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_1
+#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_2
+#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_3
+#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_0
+#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_1
+#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_2
+#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_3
+#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_4
+#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_5
+#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_6
+#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_7
+#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_8
+#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_9
+#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_10
+#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_11
+#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_12
+#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_13
+#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_14
+#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_15
+#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_BX0_BIF_RLC_INTR_CNTL
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX0_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX0_BIF_VCE_INTR_CNTL
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX0_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX0_BIF_UVD_INTR_CNTL
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT 0x1c
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L
+#define BIF_BX0_BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK 0xF0000000L
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL
+//BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL
+
+
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+//RCC_STRAP0_RCC_BIF_STRAP0
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK 0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP1
+#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d
+#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L
+//RCC_STRAP0_RCC_BIF_STRAP2
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa
+#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L
+#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP3
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_BIF_STRAP4
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_BIF_STRAP5
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L
+//RCC_STRAP0_RCC_BIF_STRAP6
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x001FFFE0L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x000C0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0x0000003EL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0003FFFCL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP10
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP11
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP12
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK 0x0000FFFFL
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0003FFFCL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP7
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1:1
+//RCC_EP_DEV0_0_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_0_EP_PCIE_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_0_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1:1
+//RCC_DWN_DEV0_0_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_0_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1:1
+//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV0_0_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1
+//RCC_DEV0_EPF0_0_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_0_RCC_ERR_LOG_1
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_1__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_1__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_1__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_1__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_0_RCC_ERR_LOG_2
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_2__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_2__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_2__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_0_RCC_ERR_LOG_2__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_1
+#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_1__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_1__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_2
+#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_2__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN_2__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_1
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_1__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_1__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_2
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_2__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE_2__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_1
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_1__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_1__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_2
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_2__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_CONFIG_RESERVED_2__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+//RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_1__IOV_ENABLE_MASK 0x80000000L
+//RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_0_RCC_IOV_FUNC_IDENTIFIER_2__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1:1
+//RCC_DEV0_0_RCC_ERR_INT_CNTL
+#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0
+#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L
+//RCC_DEV0_0_RCC_BACO_CNTL_MISC
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L
+//RCC_DEV0_0_RCC_RESET_EN
+#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
+#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L
+//RCC_DEV0_0_RCC_VDM_SUPPORT
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L
+//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L
+//RCC_DEV0_0_RCC_GPUIOV_REGION
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//RCC_DEV0_0_RCC_GPU_HOSTVM_EN
+#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0
+#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L
+//RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L
+//RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL
+//RCC_DEV0_0_RCC_PEER_REG_RANGE0
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L
+//RCC_DEV0_0_RCC_PEER_REG_RANGE1
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L
+//RCC_DEV0_0_RCC_BUS_CNTL
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_DEV0_0_RCC_CONFIG_CNTL
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L
+//RCC_DEV0_0_RCC_CONFIG_F0_BASE
+#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL
+//RCC_DEV0_0_RCC_CONFIG_APER_SIZE
+#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE
+#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL
+//RCC_DEV0_0_RCC_XDMA_LO
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L
+//RCC_DEV0_0_RCC_XDMA_HI
+#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL
+//RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_DEV0_0_RCC_BUSNUM_CNTL1
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL
+//RCC_DEV0_0_RCC_BUSNUM_LIST0
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L
+//RCC_DEV0_0_RCC_BUSNUM_LIST1
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L
+//RCC_DEV0_0_RCC_BUSNUM_CNTL2
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L
+//RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM
+#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L
+//RCC_DEV0_0_RCC_HOST_BUSNUM
+#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0
+#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL
+//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L
+//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L
+//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L
+//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L
+//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L
+//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L
+//RCC_DEV0_0_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L
+//RCC_DEV0_0_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_DEV0_0_RCC_MH_ARB_CNTL
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1:1
+//BIF_BX0_CC_BIF_BX_STRAP0
+#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19
+#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L
+//BIF_BX0_CC_BIF_BX_PINSTRAP0
+//BIF_BX0_BIF_MM_INDACCESS_CNTL
+#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L
+//BIF_BX0_BUS_CNTL
+#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a
+#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c
+#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f
+#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L
+#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L
+#define BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L
+#define BIF_BX0_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L
+#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L
+#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L
+#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L
+#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L
+#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L
+//BIF_BX0_BIF_SCRATCH0
+#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL
+//BIF_BX0_BIF_SCRATCH1
+#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL
+//BIF_BX0_BX_RESET_EN
+#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L
+//BIF_BX0_MM_CFGREGS_CNTL
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L
+//BIF_BX0_BX_RESET_CNTL
+#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L
+//BIF_BX0_INTERRUPT_CNTL
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10
+#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
+#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
+#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L
+#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L
+#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L
+//BIF_BX0_INTERRUPT_CNTL2
+#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL
+//BIF_BX0_CLKREQB_PAD_CNTL
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L
+//BIF_BX0_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x00FF0000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L
+//BIF_BX0_BIF_DOORBELL_CNTL
+#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L
+#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L
+#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L
+#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L
+//BIF_BX0_BIF_DOORBELL_INT_CNTL
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L
+//BIF_BX0_BIF_FB_EN
+#define BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+//BIF_BX0_BIF_INTR_CNTL
+#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0
+#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L
+//BIF_BX0_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL
+//BIF_BX0_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL
+//BIF_BX0_MEM_TYPE_CNTL
+#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L
+//BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L
+//BIF_BX0_NBIF_GFX_ADDR_LUT_0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_1
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_2
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_3
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_4
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_5
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_6
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_7
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_8
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_9
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_10
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_11
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_12
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_13
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_14
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_15
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL
+//BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX0_BIF_RB_CNTL
+#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d
+#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e
+#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L
+#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L
+#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L
+#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//BIF_BX0_BIF_RB_BASE
+#define BIF_BX0_BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_BX0_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//BIF_BX0_BIF_RB_RPTR
+#define BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_BX0_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX0_BIF_RB_WPTR
+#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L
+#define BIF_BX0_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX0_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL
+//BIF_BX0_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1:1
+//BIF_BX_PF0_BIF_BME_STATUS
+#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF0_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF0_BIF_TRANS_PENDING
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_1__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_1__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_2__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_LO_2__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_1__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_1__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_2__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_ADDR_HI_2__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_1__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_1__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_2__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_MSG_DATA_2__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_1__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_1__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_2__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT0_CONTROL_2__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_1__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_1__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_2__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_LO_2__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_1__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_1__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_2__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_ADDR_HI_2__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_1__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_1__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_2__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_MSG_DATA_2__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_1__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_1__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_2__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT1_CONTROL_2__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_1__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_1__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_2__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_LO_2__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_1__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_1__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_2__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_ADDR_HI_2__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_1__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_1__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_2__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_MSG_DATA_2__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_1__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_1__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_2__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT2_CONTROL_2__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_1__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_1__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_2__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_LO_2__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_1__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_1__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_2__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_ADDR_HI_2__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_1__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_1__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_2__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_MSG_DATA_2__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_1__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_1__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_2__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_VECT3_CONTROL_2__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_0_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+//RCC_DEV0_EPF0_0_GFXMSIX_PBA_1
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_1__MSIX_PENDING_BITS_3_MASK 0x00000008L
+//RCC_DEV0_EPF0_0_GFXMSIX_PBA_2
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_0_GFXMSIX_PBA_2__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+//GDC0_NGDC_SDP_PORT_CTRL
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define GDC0_NGDC_SDP_PORT_CTRL__NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN__SHIFT 0xf
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT 0x10
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL
+#define GDC0_NGDC_SDP_PORT_CTRL__NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN_MASK 0x00008000L
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L
+//GDC0_SHUB_REGS_IF_CTL
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//GDC0_NGDC_SDP_PORT_CTRL_SOCCLK
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_POOL_NUM_SOCCLK__SHIFT 0x8
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC0_RSV__SHIFT 0x10
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC5_RSV__SHIFT 0x14
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC6_RSV__SHIFT 0x18
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_H__SHIFT 0x1c
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x000000FFL
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_POOL_NUM_SOCCLK_MASK 0x0000FF00L
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC0_RSV_MASK 0x000F0000L
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC5_RSV_MASK 0x00F00000L
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC6_RSV_MASK 0x0F000000L
+#define GDC0_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_H_MASK 0xF0000000L
+//GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC0_RSV__SHIFT 0x0
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC1_RSV__SHIFT 0x4
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC5_RSV__SHIFT 0x8
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC6_RSV__SHIFT 0xc
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC0_RSV__SHIFT 0x10
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC1_RSV__SHIFT 0x14
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC0_RSV_MASK 0x0000000FL
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC1_RSV_MASK 0x000000F0L
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC5_RSV_MASK 0x00000F00L
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC6_RSV_MASK 0x0000F000L
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC0_RSV_MASK 0x000F0000L
+#define GDC0_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC1_RSV_MASK 0x00F00000L
+//GDC0_NBIF_GFX_DOORBELL_STATUS
+#define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0
+#define GDC0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x00000001L
+//GDC0_BIF_SDMA0_DOORBELL_RANGE
+#define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC0_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC0_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC0_BIF_IH_DOORBELL_RANGE
+#define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC0_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC0_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC0_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC0_BIF_VCN0_DOORBELL_RANGE
+#define GDC0_BIF_VCN0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC0_BIF_VCN0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC0_BIF_VCN0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC0_BIF_VCN0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC0_BIF_RLC_DOORBELL_RANGE
+#define GDC0_BIF_RLC_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC0_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC0_BIF_RLC_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC0_ATDMA_MISC_CNTL
+#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0
+#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1
+#define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT 0x2
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT 0x8
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18
+#define GDC0_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L
+#define GDC0_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L
+#define GDC0_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK 0x0000000CL
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK 0x0000FF00L
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L
+#define GDC0_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L
+//GDC0_BIF_DOORBELL_FENCE_CNTL
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT 0x0
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT 0x1
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT 0x2
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE__SHIFT 0x4
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE__SHIFT 0x5
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE__SHIFT 0x6
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE__SHIFT 0x7
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE__SHIFT 0x8
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x10
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK 0x00000001L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK 0x00000002L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK 0x00000004L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE_MASK 0x00000010L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE_MASK 0x00000020L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE_MASK 0x00000040L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE_MASK 0x00000080L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE_MASK 0x00000100L
+#define GDC0_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00010000L
+//GDC0_S2A_MISC_CNTL
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS__SHIFT 0x5
+#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8
+#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa
+#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc
+#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS__SHIFT 0x18
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS__SHIFT 0x19
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS__SHIFT 0x1a
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS__SHIFT 0x1b
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS_MASK 0x00000020L
+#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L
+#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L
+#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L
+#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS_MASK 0x01000000L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS_MASK 0x02000000L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS_MASK 0x04000000L
+#define GDC0_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS_MASK 0x08000000L
+//GDC0_SHUBCLK_DPM_CTRL
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_MODE__SHIFT 0x0
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_ENABLE__SHIFT 0x1
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMAWR_QUANT__SHIFT 0x2
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMARD_QUANT__SHIFT 0xa
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_CLEAR__SHIFT 0x12
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_MODE_MASK 0x00000001L
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_ENABLE_MASK 0x00000002L
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMAWR_QUANT_MASK 0x000003FCL
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMARD_QUANT_MASK 0x0003FC00L
+#define GDC0_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_CLEAR_MASK 0x00040000L
+//GDC0_SHUBCLK_DPM_WR_WEIGHT
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_4B__SHIFT 0x0
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_8B__SHIFT 0x5
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_16B__SHIFT 0xa
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_32B__SHIFT 0xf
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_64B__SHIFT 0x14
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_4B_MASK 0x0000001FL
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_8B_MASK 0x000003E0L
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_16B_MASK 0x00007C00L
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_32B_MASK 0x000F8000L
+#define GDC0_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_64B_MASK 0x01F00000L
+//GDC0_SHUBCLK_DPM_RD_WEIGHT
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_4B__SHIFT 0x0
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_8B__SHIFT 0x5
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_16B__SHIFT 0xa
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_32B__SHIFT 0xf
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_64B__SHIFT 0x14
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_4B_MASK 0x0000001FL
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_8B_MASK 0x000003E0L
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_16B_MASK 0x00007C00L
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_32B_MASK 0x000F8000L
+#define GDC0_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_64B_MASK 0x01F00000L
+//GDC0_SHUBCLK_DPM_WR_CNT
+#define GDC0_SHUBCLK_DPM_WR_CNT__SHUBCLK_DPM_WR_COUNTER__SHIFT 0x0
+#define GDC0_SHUBCLK_DPM_WR_CNT__SHUBCLK_DPM_WR_COUNTER_MASK 0xFFFFFFFFL
+//GDC0_SHUBCLK_DPM_RD_CNT
+#define GDC0_SHUBCLK_DPM_RD_CNT__SHUBCLK_DPM_RD_COUNTER__SHIFT 0x0
+#define GDC0_SHUBCLK_DPM_RD_CNT__SHUBCLK_DPM_RD_COUNTER_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdirect
+//OBFF_EMU_CFG_SOCCLK
+#define OBFF_EMU_CFG_SOCCLK__OBFF_EMU_DMA_EN__SHIFT 0x0
+#define OBFF_EMU_CFG_SOCCLK__ATHUB_URGENT_MODE__SHIFT 0x1
+#define OBFF_EMU_CFG_SOCCLK__OBFF_EMU_DMA_EN_MASK 0x00000001L
+#define OBFF_EMU_CFG_SOCCLK__ATHUB_URGENT_MODE_MASK 0x00000006L
+//HST_CLK0_SW0_CL0_CNTL
+#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//HST_CLK0_SW0_CL1_CNTL
+#define HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//HST_CLK0_SW0_CL2_CNTL
+#define HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//HST_CLK0_SW1_CL0_CNTL
+#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//HST_CLK0_SW1_CL1_CNTL
+#define HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//OBFF_EMU_CFG_SHUBCLK
+#define OBFF_EMU_CFG_SHUBCLK__URGENT_MERGE_CTRL0__SHIFT 0x0
+#define OBFF_EMU_CFG_SHUBCLK__URGENT_MERGE_CTRL0_MASK 0x00000001L
+//HST_CLK1_SW0_CL0_CNTL
+#define HST_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+//OBFF_EMU_CFG_NICCLK
+//HST_CLK2_SW0_CL0_CNTL
+#define HST_CLK2_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0
+#define HST_CLK2_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1
+#define HST_CLK2_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK 0x00000001L
+#define HST_CLK2_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK 0x00000002L
+
+
+// addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk
+//GDCSOC_ERR_RSP_CNTL
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS__SHIFT 0x0
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL__SHIFT 0x1
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN__SHIFT 0x2
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA__SHIFT 0x3
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN__SHIFT 0x4
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN__SHIFT 0x5
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS_MASK 0x00000001L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL_MASK 0x00000002L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN_MASK 0x00000004L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA_MASK 0x00000008L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN_MASK 0x00000010L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN_MASK 0x00000020L
+//GDCSOC_RAS_CENTRAL_STATUS
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det__SHIFT 0x0
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det__SHIFT 0x1
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det__SHIFT 0x2
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det__SHIFT 0x3
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det_MASK 0x00000001L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det_MASK 0x00000002L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det_MASK 0x00000004L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det_MASK 0x00000008L
+//GDCSOC_RAS_LEAF0_CTRL
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSOC_RAS_LEAF1_CTRL
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSOC_RAS_LEAF2_CTRL
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSOC_RAS_LEAF3_CTRL
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSOC_RAS_LEAF4_CTRL
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSOC_RAS_LEAF5_CTRL
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSOC_RAS_LEAF0_STATUS
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF1_STATUS
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF2_STATUS
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF3_STATUS
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF4_STATUS
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSOC_RAS_LEAF5_STATUS
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSHUB_ERR_RSP_CNTL
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_BYPASS__SHIFT 0x0
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_ACCUM_SEL__SHIFT 0x1
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_FORCE_EN__SHIFT 0x2
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_FORCE_DATA__SHIFT 0x3
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_STATUS_ACCUM_EN__SHIFT 0x4
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_DATASTATUS_ACCUM_EN__SHIFT 0x5
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_BYPASS_MASK 0x00000001L
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_ACCUM_SEL_MASK 0x00000002L
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_FORCE_EN_MASK 0x00000004L
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_FORCE_DATA_MASK 0x00000008L
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_STATUS_ACCUM_EN_MASK 0x00000010L
+#define GDCSHUB_ERR_RSP_CNTL__GDCSHUB_RDRSP_DATASTATUS_ACCUM_EN_MASK 0x00000020L
+//GDCSHUB_RAS_CENTRAL_STATUS
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_EgStall_det__SHIFT 0x0
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_ErrEvent_det__SHIFT 0x1
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_EgStall_det__SHIFT 0x2
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_ErrEvent_det__SHIFT 0x3
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_EgStall_det_MASK 0x00000001L
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_L2C_ErrEvent_det_MASK 0x00000002L
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_EgStall_det_MASK 0x00000004L
+#define GDCSHUB_RAS_CENTRAL_STATUS__GDCSHUB_C2L_ErrEvent_det_MASK 0x00000008L
+//GDCSHUB_RAS_LEAF0_CTRL
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSHUB_RAS_LEAF0_CTRL__GDCSHUB_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSHUB_RAS_LEAF1_CTRL
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSHUB_RAS_LEAF1_CTRL__GDCSHUB_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSHUB_RAS_LEAF2_CTRL
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSHUB_RAS_LEAF2_CTRL__GDCSHUB_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSHUB_RAS_LEAF3_CTRL
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCSHUB_RAS_LEAF3_CTRL__GDCSHUB_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCSHUB_RAS_LEAF0_STATUS
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSHUB_RAS_LEAF0_STATUS__GDCSHUB_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSHUB_RAS_LEAF1_STATUS
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSHUB_RAS_LEAF1_STATUS__GDCSHUB_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSHUB_RAS_LEAF2_STATUS
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSHUB_RAS_LEAF2_STATUS__GDCSHUB_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCSHUB_RAS_LEAF3_STATUS
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCSHUB_RAS_LEAF3_STATUS__GDCSHUB_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCNIC_ERR_RSP_CNTL
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_BYPASS__SHIFT 0x0
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_ACCUM_SEL__SHIFT 0x1
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_FORCE_EN__SHIFT 0x2
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_FORCE_DATA__SHIFT 0x3
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_STATUS_ACCUM_EN__SHIFT 0x4
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_DATASTATUS_ACCUM_EN__SHIFT 0x5
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_BYPASS_MASK 0x00000001L
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_ACCUM_SEL_MASK 0x00000002L
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_FORCE_EN_MASK 0x00000004L
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_FORCE_DATA_MASK 0x00000008L
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_STATUS_ACCUM_EN_MASK 0x00000010L
+#define GDCNIC_ERR_RSP_CNTL__GDCNIC_RDRSP_DATASTATUS_ACCUM_EN_MASK 0x00000020L
+//GDCNIC_RAS_CENTRAL_STATUS
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_L2C_EgStall_det__SHIFT 0x0
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_L2C_ErrEvent_det__SHIFT 0x1
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_C2L_EgStall_det__SHIFT 0x2
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_C2L_ErrEvent_det__SHIFT 0x3
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_L2C_EgStall_det_MASK 0x00000001L
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_L2C_ErrEvent_det_MASK 0x00000002L
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_C2L_EgStall_det_MASK 0x00000004L
+#define GDCNIC_RAS_CENTRAL_STATUS__GDCNIC_C2L_ErrEvent_det_MASK 0x00000008L
+//GDCNIC_RAS_LEAF0_CTRL
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCNIC_RAS_LEAF0_CTRL__GDCNIC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCNIC_RAS_LEAF1_CTRL
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCNIC_RAS_LEAF1_CTRL__GDCNIC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCNIC_RAS_LEAF2_CTRL
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT 0x0
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT 0x1
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT 0x2
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT 0x3
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT 0x4
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT 0x6
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT 0xa
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK 0x00000001L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK 0x00000002L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK 0x00000004L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK 0x00000008L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK 0x00000010L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define GDCNIC_RAS_LEAF2_CTRL__GDCNIC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK 0x00000800L
+//GDCNIC_RAS_LEAF0_STATUS
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCNIC_RAS_LEAF0_STATUS__GDCNIC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCNIC_RAS_LEAF1_STATUS
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCNIC_RAS_LEAF1_STATUS__GDCNIC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//GDCNIC_RAS_LEAF2_STATUS
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT 0x0
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT 0x1
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT 0x2
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK 0x00000001L
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK 0x00000002L
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK 0x00000004L
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define GDCNIC_RAS_LEAF2_STATUS__GDCNIC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+
+
+// addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC
+//SHUB_PF_FLR_RST
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1
+#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2
+#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3
+#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4
+#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5
+#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6
+#define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7
+#define SHUB_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT 0x8
+#define SHUB_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT 0x9
+#define SHUB_PF_FLR_RST__DEV2_PF0_FLR_RST__SHIFT 0x10
+#define SHUB_PF_FLR_RST__DEV2_PF1_FLR_RST__SHIFT 0x11
+#define SHUB_PF_FLR_RST__DEV2_PF2_FLR_RST__SHIFT 0x12
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L
+#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L
+#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L
+#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L
+#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L
+#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L
+#define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L
+#define SHUB_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK 0x00000100L
+#define SHUB_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK 0x00000200L
+#define SHUB_PF_FLR_RST__DEV2_PF0_FLR_RST_MASK 0x00010000L
+#define SHUB_PF_FLR_RST__DEV2_PF1_FLR_RST_MASK 0x00020000L
+#define SHUB_PF_FLR_RST__DEV2_PF2_FLR_RST_MASK 0x00040000L
+//SHUB_GFX_DRV_VPU_RST
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT 0x0
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK 0x00000001L
+//SHUB_LINK_RESET
+#define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT 0x0
+#define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT 0x1
+#define SHUB_LINK_RESET__LINK_P2_RESET__SHIFT 0x2
+#define SHUB_LINK_RESET__LINK_P3_RESET__SHIFT 0x3
+#define SHUB_LINK_RESET__LINK_P0_RESET_MASK 0x00000001L
+#define SHUB_LINK_RESET__LINK_P1_RESET_MASK 0x00000002L
+#define SHUB_LINK_RESET__LINK_P2_RESET_MASK 0x00000004L
+#define SHUB_LINK_RESET__LINK_P3_RESET_MASK 0x00000008L
+//SHUB_HARD_RST_CTRL
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
+#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK 0x00000001L
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK 0x00000002L
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK 0x00000004L
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L
+#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L
+//SHUB_SOFT_RST_CTRL
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4
+#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT 0x5
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK 0x00000001L
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK 0x00000002L
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK 0x00000004L
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000010L
+#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000020L
+//SHUB_SDP_PORT_RST
+#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT 0x1
+#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT 0x2
+#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT 0x3
+#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT 0x4
+#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT 0x6
+#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST__SHIFT 0x7
+#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT 0x8
+#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT 0x9
+#define SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT 0x18
+#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK 0x00000002L
+#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK 0x00000004L
+#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK 0x00000008L
+#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK 0x00000010L
+#define SHUB_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK 0x00000040L
+#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST_MASK 0x00000080L
+#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK 0x00000100L
+#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK 0x00000200L
+#define SHUB_SDP_PORT_RST__SION_AON_RST_MASK 0x01000000L
+
+
+
+
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+//BIF_CFG_DEV0_RC0_VENDOR_ID
+#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_DEVICE_ID
+#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_COMMAND
+#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_RC0_STATUS
+#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_REVISION_ID
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_PROG_INTERFACE
+#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_SUB_CLASS
+#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_BASE_CLASS
+#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_CACHE_LINE
+#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_LATENCY
+#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_HEADER
+#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_RC0_BIST
+#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_RC0_BASE_ADDR_1
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_BASE_ADDR_2
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV0_RC0_SECONDARY_STATUS
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC0_CAP_PTR
+#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV0_RC0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_PMI_CAP
+#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_PCIE_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_RC0_DEVICE_CAP
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_RC0_DEVICE_CNTL
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_DEVICE_STATUS
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_RC0_LINK_CAP
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC0_LINK_CNTL
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_RC0_LINK_STATUS
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_SLOT_CAP
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV0_RC0_SLOT_CNTL
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIF_CFG_DEV0_RC0_SLOT_STATUS
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV0_RC0_ROOT_CNTL
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV0_RC0_ROOT_CAP
+#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV0_RC0_ROOT_STATUS
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV0_RC0_DEVICE_CAP2
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_RC0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_LINK_CAP2
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_RC0_LINK_CNTL2
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_RC0_LINK_STATUS2
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC0_SLOT_CAP2
+#define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SLOT_CNTL2
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_SLOT_STATUS2
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC0_SSID_CAP_LIST
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_SSID_CAP
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_MSI_MAP_CAP
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
+//BIF_CFG_DEV1_RC0_VENDOR_ID
+#define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_DEVICE_ID
+#define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_COMMAND
+#define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_RC0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_RC0_STATUS
+#define BIF_CFG_DEV1_RC0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_REVISION_ID
+#define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_PROG_INTERFACE
+#define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_SUB_CLASS
+#define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_BASE_CLASS
+#define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_CACHE_LINE
+#define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_LATENCY
+#define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_HEADER
+#define BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_RC0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_RC0_BIST
+#define BIF_CFG_DEV1_RC0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_RC0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_RC0_BASE_ADDR_1
+#define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_BASE_ADDR_2
+#define BIF_CFG_DEV1_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC0_IO_BASE_LIMIT
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV1_RC0_SECONDARY_STATUS
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PREF_BASE_UPPER
+#define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC0_CAP_PTR
+#define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_INTERRUPT_LINE
+#define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_INTERRUPT_PIN
+#define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV1_RC0_PMI_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_PMI_CAP
+#define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC0_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_PCIE_CAP
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_RC0_DEVICE_CAP
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_RC0_DEVICE_CNTL
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_DEVICE_STATUS
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV1_RC0_LINK_CAP
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC0_LINK_CNTL
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV1_RC0_LINK_STATUS
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_SLOT_CAP
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV1_RC0_SLOT_CNTL
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIF_CFG_DEV1_RC0_SLOT_STATUS
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV1_RC0_ROOT_CNTL
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV1_RC0_ROOT_CAP
+#define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV1_RC0_ROOT_STATUS
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV1_RC0_DEVICE_CAP2
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_RC0_DEVICE_CNTL2
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_DEVICE_STATUS2
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_LINK_CAP2
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_RC0_LINK_CNTL2
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_RC0_LINK_STATUS2
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC0_SLOT_CAP2
+#define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_SLOT_CNTL2
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_SLOT_STATUS2
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_MSI_CAP_LIST
+#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV1_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_MSI_MSG_DATA
+#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC0_SSID_CAP_LIST
+#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_SSID_CAP
+#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_MSI_MAP_CAP
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV1_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_LINK_CAP_16GT
+#define BIF_CFG_DEV1_RC0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_LINK_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC0_LINK_STATUS_16GT
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV1_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV1_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp
+//BIF_CFG_DEV2_RC0_VENDOR_ID
+#define BIF_CFG_DEV2_RC0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC0_DEVICE_ID
+#define BIF_CFG_DEV2_RC0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC0_COMMAND
+#define BIF_CFG_DEV2_RC0_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV2_RC0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV2_RC0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_RC0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_RC0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV2_RC0_STATUS
+#define BIF_CFG_DEV2_RC0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV2_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV2_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV2_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV2_RC0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV2_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV2_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV2_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV2_RC0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV2_RC0_REVISION_ID
+#define BIF_CFG_DEV2_RC0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_PROG_INTERFACE
+#define BIF_CFG_DEV2_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV2_RC0_SUB_CLASS
+#define BIF_CFG_DEV2_RC0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_RC0_BASE_CLASS
+#define BIF_CFG_DEV2_RC0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_RC0_CACHE_LINE
+#define BIF_CFG_DEV2_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV2_RC0_LATENCY
+#define BIF_CFG_DEV2_RC0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV2_RC0_HEADER
+#define BIF_CFG_DEV2_RC0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV2_RC0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV2_RC0_BIST
+#define BIF_CFG_DEV2_RC0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV2_RC0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV2_RC0_BASE_ADDR_1
+#define BIF_CFG_DEV2_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_BASE_ADDR_2
+#define BIF_CFG_DEV2_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV2_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV2_RC0_IO_BASE_LIMIT
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV2_RC0_SECONDARY_STATUS
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV2_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC0_PREF_BASE_UPPER
+#define BIF_CFG_DEV2_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_RC0_CAP_PTR
+#define BIF_CFG_DEV2_RC0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV2_RC0_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_INTERRUPT_LINE
+#define BIF_CFG_DEV2_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV2_RC0_INTERRUPT_PIN
+#define BIF_CFG_DEV2_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIF_CFG_DEV2_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV2_RC0_PMI_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_RC0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_PMI_CAP
+#define BIF_CFG_DEV2_RC0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV2_RC0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV2_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV2_RC0_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_PCIE_CAP
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV2_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV2_RC0_DEVICE_CAP
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV2_RC0_DEVICE_CNTL
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV2_RC0_DEVICE_STATUS
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV2_RC0_LINK_CAP
+#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV2_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV2_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV2_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV2_RC0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV2_RC0_LINK_CNTL
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV2_RC0_LINK_STATUS
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV2_RC0_SLOT_CAP
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV2_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV2_RC0_SLOT_CNTL
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIF_CFG_DEV2_RC0_SLOT_STATUS
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV2_RC0_ROOT_CNTL
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV2_RC0_ROOT_CAP
+#define BIF_CFG_DEV2_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV2_RC0_ROOT_STATUS
+#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV2_RC0_DEVICE_CAP2
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_RC0_DEVICE_CNTL2
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV2_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV2_RC0_DEVICE_STATUS2
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC0_LINK_CAP2
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV2_RC0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_RC0_LINK_CNTL2
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV2_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV2_RC0_LINK_STATUS2
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV2_RC0_SLOT_CAP2
+#define BIF_CFG_DEV2_RC0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_SLOT_CNTL2
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC0_SLOT_STATUS2
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC0_MSI_CAP_LIST
+#define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_RC0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV2_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_MSI_MSG_DATA
+#define BIF_CFG_DEV2_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC0_SSID_CAP_LIST
+#define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_RC0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_SSID_CAP
+#define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_MSI_MAP_CAP
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV2_RC0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV2_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV2_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV2_RC0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV2_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC0_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV2_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC0_LINK_CAP_16GT
+#define BIF_CFG_DEV2_RC0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_LINK_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC0_LINK_STATUS_16GT
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV2_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV2_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV2_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF1_MM_INDEX
+#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_PF1_MM_DATA
+#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MM_INDEX_HI
+#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC
+//BIF_BX1_PCIE_INDEX
+#define BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX1_PCIE_DATA
+#define BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define BIF_BX1_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL
+//BIF_BX1_PCIE_INDEX2
+#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
+#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL
+//BIF_BX1_PCIE_DATA2
+#define BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
+#define BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_0
+#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_1
+#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_2
+#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_3
+#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_0
+#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_1
+#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_2
+#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_3
+#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_4
+#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_5
+#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_6
+#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_7
+#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_8
+#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_9
+#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_10
+#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_11
+#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_12
+#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_13
+#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_14
+#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_15
+#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_BX1_BIF_RLC_INTR_CNTL
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX1_BIF_VCE_INTR_CNTL
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX1_BIF_UVD_INTR_CNTL
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT 0x1c
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L
+#define BIF_BX1_BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK 0xF0000000L
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL
+//BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1:1
+//RCC_STRAP1_RCC_BIF_STRAP0
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK 0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP1
+#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d
+#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L
+//RCC_STRAP1_RCC_BIF_STRAP2
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa
+#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L
+#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP3
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_BIF_STRAP4
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_BIF_STRAP5
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L
+//RCC_STRAP1_RCC_BIF_STRAP6
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x001FFFE0L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x000C0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0x0000003EL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0003FFFCL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP10
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP11
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP12
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK 0x0000FFFFL
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0003FFFCL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP7
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+//RCC_EP_DEV0_1_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_1_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+//RCC_DWN_DEV0_1_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV0_1_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+//RCC_DEV0_1_RCC_ERR_INT_CNTL
+#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0
+#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L
+//RCC_DEV0_1_RCC_BACO_CNTL_MISC
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L
+//RCC_DEV0_1_RCC_RESET_EN
+#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
+#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L
+//RCC_DEV0_1_RCC_VDM_SUPPORT
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L
+//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L
+//RCC_DEV0_1_RCC_GPUIOV_REGION
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//RCC_DEV0_1_RCC_GPU_HOSTVM_EN
+#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0
+#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L
+//RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L
+//RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL
+//RCC_DEV0_1_RCC_PEER_REG_RANGE0
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L
+//RCC_DEV0_1_RCC_PEER_REG_RANGE1
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L
+//RCC_DEV0_1_RCC_BUS_CNTL
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_DEV0_1_RCC_CONFIG_CNTL
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L
+//RCC_DEV0_1_RCC_CONFIG_F0_BASE
+#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL
+//RCC_DEV0_1_RCC_CONFIG_APER_SIZE
+#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE
+#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL
+//RCC_DEV0_1_RCC_XDMA_LO
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L
+//RCC_DEV0_1_RCC_XDMA_HI
+#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL
+//RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_DEV0_1_RCC_BUSNUM_CNTL1
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL
+//RCC_DEV0_1_RCC_BUSNUM_LIST0
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L
+//RCC_DEV0_1_RCC_BUSNUM_LIST1
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L
+//RCC_DEV0_1_RCC_BUSNUM_CNTL2
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L
+//RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM
+#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L
+//RCC_DEV0_1_RCC_HOST_BUSNUM
+#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0
+#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL
+//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L
+//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L
+//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L
+//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L
+//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L
+//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L
+//RCC_DEV0_1_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L
+//RCC_DEV0_1_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_DEV0_1_RCC_MH_ARB_CNTL
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
+//BIF_BX1_CC_BIF_BX_STRAP0
+#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19
+#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L
+//BIF_BX1_CC_BIF_BX_PINSTRAP0
+//BIF_BX1_BIF_MM_INDACCESS_CNTL
+#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L
+//BIF_BX1_BUS_CNTL
+#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a
+#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c
+#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f
+#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L
+#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L
+#define BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L
+#define BIF_BX1_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L
+#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L
+#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L
+#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L
+#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L
+#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L
+//BIF_BX1_BIF_SCRATCH0
+#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL
+//BIF_BX1_BIF_SCRATCH1
+#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL
+//BIF_BX1_BX_RESET_EN
+#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L
+//BIF_BX1_MM_CFGREGS_CNTL
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L
+//BIF_BX1_BX_RESET_CNTL
+#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L
+//BIF_BX1_INTERRUPT_CNTL
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10
+#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
+#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
+#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L
+#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L
+#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L
+//BIF_BX1_INTERRUPT_CNTL2
+#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL
+//BIF_BX1_CLKREQB_PAD_CNTL
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L
+//BIF_BX1_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x00FF0000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L
+//BIF_BX1_BIF_DOORBELL_CNTL
+#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L
+#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L
+#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L
+#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L
+//BIF_BX1_BIF_DOORBELL_INT_CNTL
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L
+//BIF_BX1_BIF_FB_EN
+#define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+//BIF_BX1_BIF_INTR_CNTL
+#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0
+#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L
+//BIF_BX1_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL
+//BIF_BX1_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL
+//BIF_BX1_MEM_TYPE_CNTL
+#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L
+//BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L
+//BIF_BX1_NBIF_GFX_ADDR_LUT_0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_1
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_2
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_3
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_4
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_5
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_6
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_7
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_8
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_9
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_10
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_11
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_12
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_13
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_14
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_15
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL
+//BIF_BX1_VF_REGWR_EN
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT 0x0
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT 0x1
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT 0x2
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT 0x3
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT 0x4
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT 0x5
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT 0x6
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT 0x7
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT 0x8
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT 0x9
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT 0xa
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT 0xb
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT 0xc
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT 0xd
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT 0xe
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT 0xf
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT 0x10
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT 0x11
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT 0x12
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT 0x13
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT 0x14
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT 0x15
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT 0x16
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT 0x17
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT 0x18
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT 0x19
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT 0x1a
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT 0x1b
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT 0x1c
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT 0x1d
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT 0x1e
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK 0x00000001L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK 0x00000002L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK 0x00000004L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK 0x00000008L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK 0x00000010L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK 0x00000020L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK 0x00000040L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK 0x00000080L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK 0x00000100L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK 0x00000200L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK 0x00000400L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK 0x00000800L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK 0x00001000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK 0x00002000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK 0x00004000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK 0x00008000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK 0x00010000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK 0x00020000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK 0x00040000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK 0x00080000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK 0x00100000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK 0x00200000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK 0x00400000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK 0x00800000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK 0x01000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK 0x02000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK 0x04000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK 0x08000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK 0x10000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK 0x20000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK 0x40000000L
+//BIF_BX1_VF_DOORBELL_EN
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT 0x0
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT 0x1
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT 0x2
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT 0x3
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT 0x4
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT 0x5
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT 0x6
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT 0x7
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT 0x8
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT 0x9
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT 0xa
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT 0xb
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT 0xc
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT 0xd
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT 0xe
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT 0xf
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT 0x10
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT 0x11
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT 0x12
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT 0x13
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT 0x14
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT 0x15
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT 0x16
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT 0x17
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT 0x18
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT 0x19
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT 0x1a
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT 0x1b
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT 0x1c
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT 0x1d
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT 0x1e
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT 0x1f
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK 0x00000001L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK 0x00000002L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK 0x00000004L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK 0x00000008L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK 0x00000010L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK 0x00000020L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK 0x00000040L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK 0x00000080L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK 0x00000100L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK 0x00000200L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK 0x00000400L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK 0x00000800L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK 0x00001000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK 0x00002000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK 0x00004000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK 0x00008000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK 0x00010000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK 0x00020000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK 0x00040000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK 0x00080000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK 0x00100000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK 0x00200000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK 0x00400000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK 0x00800000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK 0x01000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK 0x02000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK 0x04000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK 0x08000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK 0x10000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK 0x20000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK 0x40000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK 0x80000000L
+//BIF_BX1_VF_FB_EN
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT 0x0
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT 0x1
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT 0x2
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT 0x3
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT 0x4
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT 0x5
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT 0x6
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT 0x7
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT 0x8
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT 0x9
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT 0xa
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT 0xb
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT 0xc
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT 0xd
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT 0xe
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT 0xf
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT 0x10
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT 0x11
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT 0x12
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT 0x13
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT 0x14
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT 0x15
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT 0x16
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT 0x17
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT 0x18
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT 0x19
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT 0x1a
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT 0x1b
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT 0x1c
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT 0x1d
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT 0x1e
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK 0x00000001L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK 0x00000002L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK 0x00000004L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK 0x00000008L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK 0x00000010L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK 0x00000020L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK 0x00000040L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK 0x00000080L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK 0x00000100L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK 0x00000200L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK 0x00000400L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK 0x00000800L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK 0x00001000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK 0x00002000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK 0x00004000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK 0x00008000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK 0x00010000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK 0x00020000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK 0x00040000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK 0x00080000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK 0x00100000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK 0x00200000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK 0x00400000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK 0x00800000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK 0x01000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK 0x02000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK 0x04000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK 0x08000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK 0x10000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK 0x20000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK 0x40000000L
+//BIF_BX1_VF_REGWR_STATUS
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT 0x0
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT 0x1
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT 0x2
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT 0x3
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT 0x4
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT 0x5
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT 0x6
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT 0x7
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT 0x8
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT 0x9
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT 0xa
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT 0xb
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT 0xc
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT 0xd
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT 0xe
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT 0xf
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT 0x10
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT 0x11
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT 0x12
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT 0x13
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT 0x14
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT 0x15
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT 0x16
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT 0x17
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT 0x18
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT 0x19
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT 0x1a
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT 0x1b
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT 0x1c
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT 0x1d
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT 0x1e
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK 0x00000001L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK 0x00000002L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK 0x00000004L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK 0x00000008L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK 0x00000010L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK 0x00000020L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK 0x00000040L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK 0x00000080L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK 0x00000100L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK 0x00000200L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK 0x00000400L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK 0x00000800L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK 0x00001000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK 0x00002000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK 0x00004000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK 0x00008000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK 0x00010000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK 0x00020000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK 0x00040000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK 0x00080000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK 0x00100000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK 0x00200000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK 0x00400000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK 0x00800000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK 0x01000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK 0x02000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK 0x04000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK 0x08000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK 0x10000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK 0x20000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK 0x40000000L
+//BIF_BX1_VF_DOORBELL_STATUS
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT 0x0
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT 0x1
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT 0x2
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT 0x3
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT 0x4
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT 0x5
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT 0x6
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT 0x7
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT 0x8
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT 0x9
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT 0xa
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT 0xb
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT 0xc
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT 0xd
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT 0xe
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT 0xf
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT 0x10
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT 0x11
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT 0x12
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT 0x13
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT 0x14
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT 0x15
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT 0x16
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT 0x17
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT 0x18
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT 0x19
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT 0x1a
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT 0x1b
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT 0x1c
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT 0x1d
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT 0x1e
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK 0x00000001L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK 0x00000002L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK 0x00000004L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK 0x00000008L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK 0x00000010L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK 0x00000020L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK 0x00000040L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK 0x00000080L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK 0x00000100L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK 0x00000200L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK 0x00000400L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK 0x00000800L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK 0x00001000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK 0x00002000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK 0x00004000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK 0x00008000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK 0x00010000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK 0x00020000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK 0x00040000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK 0x00080000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK 0x00100000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK 0x00200000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK 0x00400000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK 0x00800000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK 0x01000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK 0x02000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK 0x04000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK 0x08000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK 0x10000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK 0x20000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK 0x40000000L
+//BIF_BX1_VF_FB_STATUS
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT 0x0
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT 0x1
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT 0x2
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT 0x3
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT 0x4
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT 0x5
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT 0x6
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT 0x7
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT 0x8
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT 0x9
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT 0xa
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT 0xb
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT 0xc
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT 0xd
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT 0xe
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT 0xf
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT 0x10
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT 0x11
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT 0x12
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT 0x13
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT 0x14
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT 0x15
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT 0x16
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT 0x17
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT 0x18
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT 0x19
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT 0x1a
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT 0x1b
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT 0x1c
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT 0x1d
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT 0x1e
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK 0x00000001L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK 0x00000002L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK 0x00000004L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK 0x00000008L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK 0x00000010L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK 0x00000020L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK 0x00000040L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK 0x00000080L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK 0x00000100L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK 0x00000200L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK 0x00000400L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK 0x00000800L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK 0x00001000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK 0x00002000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK 0x00004000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK 0x00008000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK 0x00010000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK 0x00020000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK 0x00040000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK 0x00080000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK 0x00100000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK 0x00200000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK 0x00400000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK 0x00800000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK 0x01000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK 0x02000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK 0x04000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK 0x08000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK 0x10000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK 0x20000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK 0x40000000L
+//BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX1_BIF_RB_CNTL
+#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d
+#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e
+#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L
+#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L
+#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L
+#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//BIF_BX1_BIF_RB_BASE
+#define BIF_BX1_BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_BX1_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//BIF_BX1_BIF_RB_RPTR
+#define BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_BX1_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX1_BIF_RB_WPTR
+#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L
+#define BIF_BX1_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX1_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL
+//BIF_BX1_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//BIF_BX1_MAILBOX_INDEX
+#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
+#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL
+//BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE
+#define BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE
+#define BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE
+#define BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX1_BIF_PERSTB_PAD_CNTL
+#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL
+//BIF_BX1_BIF_PX_EN_PAD_CNTL
+#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX1_BIF_REFPADKIN_PAD_CNTL
+#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX1_BIF_CLKREQB_PAD_CNTL
+#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL
+//BIF_BX1_BIF_PWRBRK_PAD_CNTL
+#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0
+#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX1_BIF_WAKEB_PAD_CNTL
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT 0x0
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT 0x1
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT 0x2
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT 0x3
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT 0x4
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT 0x5
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT 0x6
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT 0x7
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK 0x00000001L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK 0x00000002L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK 0x00000004L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK 0x00000008L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK 0x00000010L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK 0x00000020L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK 0x00000040L
+#define BIF_BX1_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK 0x00000080L
+//BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT 0x0
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT 0x1
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT 0x2
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT 0x3
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT 0x4
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT 0x5
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK 0x00000001L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK 0x00000002L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK 0x00000004L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK 0x00000008L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK 0x00000010L
+#define BIF_BX1_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK 0x00000020L
+//BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL
+#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID__SHIFT 0x0
+#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH__SHIFT 0x1
+#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID_MASK 0x00000001L
+#define BIF_BX1_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH_MASK 0xFFFFFFFEL
+//BIF_BX1_BIF_S5_MEM_POWER_CTRL0
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0__SHIFT 0x0
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0_MASK 0xFFFFFFFFL
+//BIF_BX1_BIF_S5_MEM_POWER_CTRL1
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32__SHIFT 0x0
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL__SHIFT 0xa
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32_MASK 0x000003FFL
+#define BIF_BX1_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL_MASK 0x00000400L
+//BIF_BX1_BIF_S5_DUMMY_REGS
+#define BIF_BX1_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS__SHIFT 0x0
+#define BIF_BX1_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF1_BIF_BME_STATUS
+#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF1_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF1_BIF_TRANS_PENDING
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_CONTROL
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_PF1_MAILBOX_INT_CNTL
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_PF1_BIF_VMHV_MAILBOX
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x001FFFE0L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x000C0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_DEV1_PORT_STRAP0
+#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__SHIFT 0x1
+#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__SHIFT 0x2
+#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__SHIFT 0x3
+#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__SHIFT 0x4
+#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__SHIFT 0x5
+#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__SHIFT 0x15
+#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__SHIFT 0x19
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__SHIFT 0x1c
+#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__SHIFT 0x1f
+#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1_MASK 0x00000002L
+#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1_MASK 0x00000004L
+#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1_MASK 0x00000008L
+#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1_MASK 0x00000010L
+#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1_MASK 0x001FFFE0L
+#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1_MASK 0x00E00000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1_MASK 0x01000000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1_MASK 0x0E000000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1_MASK 0x70000000L
+#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1_MASK 0x80000000L
+//RCC_DEV1_PORT_STRAP1
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1_MASK 0x0000FFFFL
+#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1_MASK 0xFFFF0000L
+//RCC_DEV1_PORT_STRAP2
+#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__SHIFT 0x1
+#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__SHIFT 0x2
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__SHIFT 0x3
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__SHIFT 0x4
+#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__SHIFT 0x6
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__SHIFT 0x7
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__SHIFT 0x9
+#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__SHIFT 0xc
+#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__SHIFT 0xd
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__SHIFT 0xe
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__SHIFT 0xf
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV1__SHIFT 0x11
+#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__SHIFT 0x12
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x14
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__SHIFT 0x17
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x1a
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__SHIFT 0x1d
+#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1_MASK 0x00000001L
+#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1_MASK 0x00000002L
+#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1_MASK 0x00000004L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1_MASK 0x00000008L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1_MASK 0x00000010L
+#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1_MASK 0x00000040L
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1_MASK 0x00000080L
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1_MASK 0x00000100L
+#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1_MASK 0x00000E00L
+#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1_MASK 0x00001000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1_MASK 0x00002000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1_MASK 0x00004000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1_MASK 0x00008000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1_MASK 0x00010000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV1_MASK 0x00020000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1_MASK 0x000C0000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1_MASK 0x00700000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1_MASK 0x03800000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1_MASK 0x1C000000L
+#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1_MASK 0xE0000000L
+//RCC_DEV1_PORT_STRAP3
+#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__SHIFT 0x1
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__SHIFT 0x2
+#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__SHIFT 0x3
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__SHIFT 0x6
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__SHIFT 0x7
+#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__SHIFT 0x9
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0xb
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0xe
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0x12
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0x15
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__SHIFT 0x19
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__SHIFT 0x1b
+#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__SHIFT 0x1d
+#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__SHIFT 0x1f
+#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1_MASK 0x00000001L
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1_MASK 0x00000002L
+#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1_MASK 0x00000004L
+#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1_MASK 0x00000038L
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1_MASK 0x00000040L
+#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1_MASK 0x00000080L
+#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1_MASK 0x00000100L
+#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1_MASK 0x00000600L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1_MASK 0x00003800L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1_MASK 0x0003C000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1_MASK 0x001C0000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1_MASK 0x01E00000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1_MASK 0x06000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1_MASK 0x18000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1_MASK 0x20000000L
+#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1_MASK 0x80000000L
+//RCC_DEV1_PORT_STRAP4
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1_MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1_MASK 0x0000FF00L
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1_MASK 0x00FF0000L
+#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1_MASK 0xFF000000L
+//RCC_DEV1_PORT_STRAP5
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__SHIFT 0x11
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__SHIFT 0x12
+#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__SHIFT 0x13
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__SHIFT 0x14
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__SHIFT 0x15
+#define RCC_DEV1_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV1__SHIFT 0x16
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__SHIFT 0x17
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__SHIFT 0x19
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__SHIFT 0x1a
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__SHIFT 0x1b
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__SHIFT 0x1c
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__SHIFT 0x1d
+#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__SHIFT 0x1e
+#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__SHIFT 0x1f
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1_MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1_MASK 0x0000FF00L
+#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1_MASK 0x00010000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1_MASK 0x00020000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1_MASK 0x00040000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1_MASK 0x00080000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1_MASK 0x00100000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1_MASK 0x00200000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV1_MASK 0x00400000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1_MASK 0x00800000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1_MASK 0x01000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1_MASK 0x02000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1_MASK 0x04000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1_MASK 0x08000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1_MASK 0x10000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1_MASK 0x20000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1_MASK 0x40000000L
+#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1_MASK 0x80000000L
+//RCC_DEV1_PORT_STRAP6
+#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__SHIFT 0x1
+#define RCC_DEV1_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV1__SHIFT 0x3
+#define RCC_DEV1_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV1__SHIFT 0x4
+#define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV1__SHIFT 0x5
+#define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV1__SHIFT 0x6
+#define RCC_DEV1_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV1__SHIFT 0x7
+#define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV1__SHIFT 0xc
+#define RCC_DEV1_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV1__SHIFT 0x12
+#define RCC_DEV1_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV1__SHIFT 0x13
+#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1_MASK 0x00000001L
+#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1_MASK 0x00000002L
+#define RCC_DEV1_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV1_MASK 0x00000008L
+#define RCC_DEV1_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV1_MASK 0x00000010L
+#define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV1_MASK 0x00000020L
+#define RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV1_MASK 0x00000040L
+#define RCC_DEV1_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV1_MASK 0x00000080L
+#define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV1_MASK 0x00000F00L
+#define RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV1_MASK 0x0000F000L
+#define RCC_DEV1_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV1_MASK 0x00030000L
+#define RCC_DEV1_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV1_MASK 0x00040000L
+#define RCC_DEV1_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV1_MASK 0x00080000L
+//RCC_DEV1_PORT_STRAP7
+#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__SHIFT 0xc
+#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__SHIFT 0x1d
+#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1_MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1_MASK 0x00000F00L
+#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1_MASK 0x0000F000L
+#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1_MASK 0x00FF0000L
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1_MASK 0x1F000000L
+#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1_MASK 0xE0000000L
+//RCC_DEV1_PORT_STRAP8
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV1__SHIFT 0x18
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV1_MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV1_MASK 0x0000FF00L
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV1_MASK 0x00FF0000L
+#define RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV1_MASK 0xFF000000L
+//RCC_DEV1_PORT_STRAP9
+#define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV1__SHIFT 0x0
+#define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV1__SHIFT 0x8
+#define RCC_DEV1_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV1__SHIFT 0x10
+#define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV1_MASK 0x000000FFL
+#define RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV1_MASK 0x0000FF00L
+#define RCC_DEV1_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV1_MASK 0xFFFF0000L
+//RCC_DEV2_PORT_STRAP0
+#define RCC_DEV2_PORT_STRAP0__STRAP_ARI_EN_DN_DEV2__SHIFT 0x1
+#define RCC_DEV2_PORT_STRAP0__STRAP_ACS_EN_DN_DEV2__SHIFT 0x2
+#define RCC_DEV2_PORT_STRAP0__STRAP_AER_EN_DN_DEV2__SHIFT 0x3
+#define RCC_DEV2_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV2__SHIFT 0x4
+#define RCC_DEV2_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV2__SHIFT 0x5
+#define RCC_DEV2_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV2__SHIFT 0x15
+#define RCC_DEV2_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV2__SHIFT 0x18
+#define RCC_DEV2_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV2__SHIFT 0x19
+#define RCC_DEV2_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV2__SHIFT 0x1c
+#define RCC_DEV2_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV2__SHIFT 0x1f
+#define RCC_DEV2_PORT_STRAP0__STRAP_ARI_EN_DN_DEV2_MASK 0x00000002L
+#define RCC_DEV2_PORT_STRAP0__STRAP_ACS_EN_DN_DEV2_MASK 0x00000004L
+#define RCC_DEV2_PORT_STRAP0__STRAP_AER_EN_DN_DEV2_MASK 0x00000008L
+#define RCC_DEV2_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV2_MASK 0x00000010L
+#define RCC_DEV2_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV2_MASK 0x001FFFE0L
+#define RCC_DEV2_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV2_MASK 0x00E00000L
+#define RCC_DEV2_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV2_MASK 0x01000000L
+#define RCC_DEV2_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV2_MASK 0x0E000000L
+#define RCC_DEV2_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV2_MASK 0x70000000L
+#define RCC_DEV2_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV2_MASK 0x80000000L
+//RCC_DEV2_PORT_STRAP1
+#define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV2_MASK 0x0000FFFFL
+#define RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV2_MASK 0xFFFF0000L
+//RCC_DEV2_PORT_STRAP2
+#define RCC_DEV2_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP2__STRAP_DSN_EN_DN_DEV2__SHIFT 0x1
+#define RCC_DEV2_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV2__SHIFT 0x2
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECN1P1_EN_DEV2__SHIFT 0x3
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV2__SHIFT 0x4
+#define RCC_DEV2_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV2__SHIFT 0x6
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV2__SHIFT 0x7
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV2__SHIFT 0x9
+#define RCC_DEV2_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV2__SHIFT 0xc
+#define RCC_DEV2_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV2__SHIFT 0xd
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV2__SHIFT 0xe
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_EN_DEV2__SHIFT 0xf
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV2__SHIFT 0x11
+#define RCC_DEV2_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV2__SHIFT 0x12
+#define RCC_DEV2_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV2__SHIFT 0x14
+#define RCC_DEV2_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV2__SHIFT 0x17
+#define RCC_DEV2_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV2__SHIFT 0x1a
+#define RCC_DEV2_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV2__SHIFT 0x1d
+#define RCC_DEV2_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV2_MASK 0x00000001L
+#define RCC_DEV2_PORT_STRAP2__STRAP_DSN_EN_DN_DEV2_MASK 0x00000002L
+#define RCC_DEV2_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV2_MASK 0x00000004L
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECN1P1_EN_DEV2_MASK 0x00000008L
+#define RCC_DEV2_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV2_MASK 0x00000010L
+#define RCC_DEV2_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV2_MASK 0x00000040L
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV2_MASK 0x00000080L
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV2_MASK 0x00000100L
+#define RCC_DEV2_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV2_MASK 0x00000E00L
+#define RCC_DEV2_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV2_MASK 0x00001000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV2_MASK 0x00002000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV2_MASK 0x00004000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN2_EN_DEV2_MASK 0x00008000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV2_MASK 0x00010000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV2_MASK 0x00020000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV2_MASK 0x000C0000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV2_MASK 0x00700000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV2_MASK 0x03800000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV2_MASK 0x1C000000L
+#define RCC_DEV2_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV2_MASK 0xE0000000L
+//RCC_DEV2_PORT_STRAP3
+#define RCC_DEV2_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DEV2__SHIFT 0x1
+#define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DN_DEV2__SHIFT 0x2
+#define RCC_DEV2_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV2__SHIFT 0x3
+#define RCC_DEV2_PORT_STRAP3__STRAP_MSI_EN_DN_DEV2__SHIFT 0x6
+#define RCC_DEV2_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV2__SHIFT 0x7
+#define RCC_DEV2_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV2__SHIFT 0x9
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV2__SHIFT 0xb
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV2__SHIFT 0xe
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV2__SHIFT 0x12
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV2__SHIFT 0x15
+#define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DEV2__SHIFT 0x19
+#define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV2__SHIFT 0x1b
+#define RCC_DEV2_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV2__SHIFT 0x1d
+#define RCC_DEV2_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV2__SHIFT 0x1f
+#define RCC_DEV2_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV2_MASK 0x00000001L
+#define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DEV2_MASK 0x00000002L
+#define RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DN_DEV2_MASK 0x00000004L
+#define RCC_DEV2_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV2_MASK 0x00000038L
+#define RCC_DEV2_PORT_STRAP3__STRAP_MSI_EN_DN_DEV2_MASK 0x00000040L
+#define RCC_DEV2_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV2_MASK 0x00000080L
+#define RCC_DEV2_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV2_MASK 0x00000100L
+#define RCC_DEV2_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV2_MASK 0x00000600L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV2_MASK 0x00003800L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV2_MASK 0x0003C000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV2_MASK 0x001C0000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV2_MASK 0x01E00000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DEV2_MASK 0x06000000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV2_MASK 0x18000000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV2_MASK 0x20000000L
+#define RCC_DEV2_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV2_MASK 0x80000000L
+//RCC_DEV2_PORT_STRAP4
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV2__SHIFT 0x18
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV2_MASK 0x000000FFL
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV2_MASK 0x0000FF00L
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV2_MASK 0x00FF0000L
+#define RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV2_MASK 0xFF000000L
+//RCC_DEV2_PORT_STRAP5
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV2__SHIFT 0x11
+#define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV2__SHIFT 0x12
+#define RCC_DEV2_PORT_STRAP5__STRAP_VC_EN_DN_DEV2__SHIFT 0x13
+#define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DEV2__SHIFT 0x14
+#define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV2__SHIFT 0x15
+#define RCC_DEV2_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV2__SHIFT 0x16
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV2__SHIFT 0x17
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV2__SHIFT 0x18
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV2__SHIFT 0x19
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV2__SHIFT 0x1a
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV2__SHIFT 0x1b
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV2__SHIFT 0x1c
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV2__SHIFT 0x1d
+#define RCC_DEV2_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV2__SHIFT 0x1e
+#define RCC_DEV2_PORT_STRAP5__STRAP_SSID_EN_DEV2__SHIFT 0x1f
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV2_MASK 0x000000FFL
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV2_MASK 0x0000FF00L
+#define RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV2_MASK 0x00010000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV2_MASK 0x00020000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV2_MASK 0x00040000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_VC_EN_DN_DEV2_MASK 0x00080000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DEV2_MASK 0x00100000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV2_MASK 0x00200000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV2_MASK 0x00400000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV2_MASK 0x00800000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV2_MASK 0x01000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV2_MASK 0x02000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV2_MASK 0x04000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV2_MASK 0x08000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV2_MASK 0x10000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV2_MASK 0x20000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV2_MASK 0x40000000L
+#define RCC_DEV2_PORT_STRAP5__STRAP_SSID_EN_DEV2_MASK 0x80000000L
+//RCC_DEV2_PORT_STRAP6
+#define RCC_DEV2_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV2__SHIFT 0x1
+#define RCC_DEV2_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV2__SHIFT 0x3
+#define RCC_DEV2_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV2__SHIFT 0x4
+#define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV2__SHIFT 0x5
+#define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV2__SHIFT 0x6
+#define RCC_DEV2_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV2__SHIFT 0x7
+#define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV2__SHIFT 0xc
+#define RCC_DEV2_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV2__SHIFT 0x12
+#define RCC_DEV2_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV2__SHIFT 0x13
+#define RCC_DEV2_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV2_MASK 0x00000001L
+#define RCC_DEV2_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV2_MASK 0x00000002L
+#define RCC_DEV2_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV2_MASK 0x00000008L
+#define RCC_DEV2_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV2_MASK 0x00000010L
+#define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV2_MASK 0x00000020L
+#define RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV2_MASK 0x00000040L
+#define RCC_DEV2_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV2_MASK 0x00000080L
+#define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV2_MASK 0x00000F00L
+#define RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV2_MASK 0x0000F000L
+#define RCC_DEV2_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV2_MASK 0x00030000L
+#define RCC_DEV2_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV2_MASK 0x00040000L
+#define RCC_DEV2_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV2_MASK 0x00080000L
+//RCC_DEV2_PORT_STRAP7
+#define RCC_DEV2_PORT_STRAP7__STRAP_PORT_NUMBER_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV2__SHIFT 0xc
+#define RCC_DEV2_PORT_STRAP7__STRAP_RP_BUSNUM_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP7__STRAP_DN_DEVNUM_DEV2__SHIFT 0x18
+#define RCC_DEV2_PORT_STRAP7__STRAP_DN_FUNCID_DEV2__SHIFT 0x1d
+#define RCC_DEV2_PORT_STRAP7__STRAP_PORT_NUMBER_DEV2_MASK 0x000000FFL
+#define RCC_DEV2_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV2_MASK 0x00000F00L
+#define RCC_DEV2_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV2_MASK 0x0000F000L
+#define RCC_DEV2_PORT_STRAP7__STRAP_RP_BUSNUM_DEV2_MASK 0x00FF0000L
+#define RCC_DEV2_PORT_STRAP7__STRAP_DN_DEVNUM_DEV2_MASK 0x1F000000L
+#define RCC_DEV2_PORT_STRAP7__STRAP_DN_FUNCID_DEV2_MASK 0xE0000000L
+//RCC_DEV2_PORT_STRAP8
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV2__SHIFT 0x18
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV2_MASK 0x000000FFL
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV2_MASK 0x0000FF00L
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV2_MASK 0x00FF0000L
+#define RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV2_MASK 0xFF000000L
+//RCC_DEV2_PORT_STRAP9
+#define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV2__SHIFT 0x0
+#define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV2__SHIFT 0x8
+#define RCC_DEV2_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV2__SHIFT 0x10
+#define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV2_MASK 0x000000FFL
+#define RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV2_MASK 0x0000FF00L
+#define RCC_DEV2_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV2_MASK 0xFFFF0000L
+//RCC_STRAP2_RCC_BIF_STRAP0
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT 0x0
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK 0x00000001L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L
+//RCC_STRAP2_RCC_BIF_STRAP1
+#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d
+#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L
+//RCC_STRAP2_RCC_BIF_STRAP2
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa
+#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L
+#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L
+//RCC_STRAP2_RCC_BIF_STRAP3
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP2_RCC_BIF_STRAP4
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP2_RCC_BIF_STRAP5
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L
+//RCC_STRAP2_RCC_BIF_STRAP6
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0x0000003EL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00000002L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0003FFFCL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0003FFFCL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP7
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP10
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP11
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP12
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK 0x0000FFFFL
+//RCC_DEV0_EPF2_STRAP0
+#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT 0x1c
+#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT 0x1d
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT 0x1e
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT 0x1f
+#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2_MASK 0x000F0000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2_MASK 0x00F00000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2_MASK 0x10000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2_MASK 0x20000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2_MASK 0x40000000L
+#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2_MASK 0x80000000L
+//RCC_DEV0_EPF2_STRAP2
+#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x7
+#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x8
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2__SHIFT 0x9
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0xe
+#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x11
+#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x15
+#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT 0x17
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x18
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2__SHIFT 0x1c
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2__SHIFT 0x1d
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2__SHIFT 0x1e
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2__SHIFT 0x1f
+#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK 0x00000080L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2_MASK 0x00000100L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2_MASK 0x00003E00L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_MASK 0x00004000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2_MASK 0x00010000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2_MASK 0x00020000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2_MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2_MASK 0x00200000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2_MASK 0x00800000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2_MASK 0x07000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2_MASK 0x10000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2_MASK 0x20000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2_MASK 0x40000000L
+#define RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2_MASK 0x80000000L
+//RCC_DEV0_EPF2_STRAP3
+#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT 0x1
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT 0x2
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT 0x12
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT 0x13
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT 0x18
+#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT 0x1a
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT 0x1b
+#define RCC_DEV0_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV0_F2__SHIFT 0x1d
+#define RCC_DEV0_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F2__SHIFT 0x1e
+#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2_MASK 0x00000001L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2_MASK 0x00000002L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2_MASK 0x00040000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2_MASK 0x00080000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2_MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2_MASK 0x01000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2_MASK 0x04000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2_MASK 0x08000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV0_F2_MASK 0x20000000L
+#define RCC_DEV0_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F2_MASK 0x40000000L
+//RCC_DEV0_EPF2_STRAP4
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT 0x14
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT 0x15
+#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT 0x16
+#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT 0x17
+#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT 0x1c
+#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT 0x1f
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2_MASK 0x00100000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2_MASK 0x00200000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2_MASK 0x00400000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2_MASK 0x0F800000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2_MASK 0x70000000L
+#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2_MASK 0x80000000L
+//RCC_DEV0_EPF2_STRAP5
+#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2__SHIFT 0x1e
+#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F2_MASK 0x40000000L
+//RCC_DEV0_EPF2_STRAP6
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x1
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__SHIFT 0x8
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x9
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2_MASK 0x00000001L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2_MASK 0x00000002L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2_MASK 0x00000100L
+#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2_MASK 0x00000200L
+//RCC_DEV0_EPF2_STRAP7
+//RCC_DEV0_EPF2_STRAP10
+//RCC_DEV0_EPF2_STRAP11
+//RCC_DEV0_EPF2_STRAP12
+//RCC_DEV0_EPF2_STRAP13
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT 0x8
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT 0x10
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2_MASK 0x000000FFL
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2_MASK 0x0000FF00L
+#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2_MASK 0x00FF0000L
+//RCC_DEV0_EPF2_STRAP14
+#define RCC_DEV0_EPF2_STRAP14__STRAP_VENDOR_ID_DEV0_F2__SHIFT 0x0
+#define RCC_DEV0_EPF2_STRAP14__STRAP_VENDOR_ID_DEV0_F2_MASK 0x0000FFFFL
+//RCC_DEV0_EPF3_STRAP0
+#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT 0x1c
+#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT 0x1d
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT 0x1e
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT 0x1f
+#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3_MASK 0x000F0000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3_MASK 0x00F00000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3_MASK 0x10000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3_MASK 0x20000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3_MASK 0x40000000L
+#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3_MASK 0x80000000L
+//RCC_DEV0_EPF3_STRAP2
+#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT 0x7
+#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT 0x8
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3__SHIFT 0x9
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT 0xe
+#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT 0x11
+#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT 0x15
+#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT 0x17
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT 0x18
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3__SHIFT 0x1c
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3__SHIFT 0x1d
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3__SHIFT 0x1e
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3__SHIFT 0x1f
+#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3_MASK 0x00000080L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3_MASK 0x00000100L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3_MASK 0x00003E00L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3_MASK 0x00004000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3_MASK 0x00010000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3_MASK 0x00020000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3_MASK 0x00100000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3_MASK 0x00200000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3_MASK 0x00800000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3_MASK 0x07000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3_MASK 0x10000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3_MASK 0x20000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3_MASK 0x40000000L
+#define RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3_MASK 0x80000000L
+//RCC_DEV0_EPF3_STRAP3
+#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT 0x1
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT 0x2
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT 0x12
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT 0x13
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT 0x18
+#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT 0x1a
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT 0x1b
+#define RCC_DEV0_EPF3_STRAP3__STRAP_CLK_PM_EN_DEV0_F3__SHIFT 0x1d
+#define RCC_DEV0_EPF3_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F3__SHIFT 0x1e
+#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3_MASK 0x00000001L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3_MASK 0x00000002L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3_MASK 0x00040000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3_MASK 0x00080000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3_MASK 0x00100000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3_MASK 0x01000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3_MASK 0x04000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3_MASK 0x08000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_CLK_PM_EN_DEV0_F3_MASK 0x20000000L
+#define RCC_DEV0_EPF3_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F3_MASK 0x40000000L
+//RCC_DEV0_EPF3_STRAP4
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT 0x14
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT 0x15
+#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT 0x16
+#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT 0x17
+#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT 0x1c
+#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT 0x1f
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3_MASK 0x00100000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3_MASK 0x00200000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3_MASK 0x00400000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3_MASK 0x0F800000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3_MASK 0x70000000L
+#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3_MASK 0x80000000L
+//RCC_DEV0_EPF3_STRAP5
+#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3__SHIFT 0x1e
+#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF3_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F3_MASK 0x40000000L
+//RCC_DEV0_EPF3_STRAP6
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__SHIFT 0x1
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3_MASK 0x00000001L
+#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3_MASK 0x00000002L
+//RCC_DEV0_EPF3_STRAP7
+#define RCC_DEV0_EPF3_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F3__SHIFT 0x5
+#define RCC_DEV0_EPF3_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F3_MASK 0x0000FFE0L
+//RCC_DEV0_EPF3_STRAP10
+//RCC_DEV0_EPF3_STRAP11
+//RCC_DEV0_EPF3_STRAP12
+//RCC_DEV0_EPF3_STRAP13
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT 0x8
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT 0x10
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3_MASK 0x000000FFL
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3_MASK 0x0000FF00L
+#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3_MASK 0x00FF0000L
+//RCC_DEV0_EPF3_STRAP14
+#define RCC_DEV0_EPF3_STRAP14__STRAP_VENDOR_ID_DEV0_F3__SHIFT 0x0
+#define RCC_DEV0_EPF3_STRAP14__STRAP_VENDOR_ID_DEV0_F3_MASK 0x0000FFFFL
+//RCC_DEV0_EPF4_STRAP0
+#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT 0x1c
+#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__SHIFT 0x1d
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT 0x1e
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT 0x1f
+#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4_MASK 0x000F0000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4_MASK 0x00F00000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4_MASK 0x10000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4_MASK 0x20000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4_MASK 0x40000000L
+#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4_MASK 0x80000000L
+//RCC_DEV0_EPF4_STRAP2
+#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__SHIFT 0x7
+#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__SHIFT 0x8
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F4__SHIFT 0x9
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__SHIFT 0xe
+#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT 0x11
+#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT 0x15
+#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__SHIFT 0x17
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__SHIFT 0x18
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EN_DEV0_F4__SHIFT 0x1c
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4__SHIFT 0x1d
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4__SHIFT 0x1e
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4__SHIFT 0x1f
+#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4_MASK 0x00000080L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4_MASK 0x00000100L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F4_MASK 0x00003E00L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4_MASK 0x00004000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4_MASK 0x00010000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4_MASK 0x00020000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4_MASK 0x00100000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4_MASK 0x00200000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4_MASK 0x00800000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4_MASK 0x07000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EN_DEV0_F4_MASK 0x10000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4_MASK 0x20000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4_MASK 0x40000000L
+#define RCC_DEV0_EPF4_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4_MASK 0x80000000L
+//RCC_DEV0_EPF4_STRAP3
+#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT 0x1
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__SHIFT 0x2
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__SHIFT 0x12
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__SHIFT 0x13
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT 0x18
+#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT 0x1a
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT 0x1b
+#define RCC_DEV0_EPF4_STRAP3__STRAP_CLK_PM_EN_DEV0_F4__SHIFT 0x1d
+#define RCC_DEV0_EPF4_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F4__SHIFT 0x1e
+#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4_MASK 0x00000001L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4_MASK 0x00000002L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4_MASK 0x00040000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4_MASK 0x00080000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4_MASK 0x00100000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4_MASK 0x01000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4_MASK 0x04000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4_MASK 0x08000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_CLK_PM_EN_DEV0_F4_MASK 0x20000000L
+#define RCC_DEV0_EPF4_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F4_MASK 0x40000000L
+//RCC_DEV0_EPF4_STRAP4
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__SHIFT 0x14
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__SHIFT 0x15
+#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__SHIFT 0x16
+#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__SHIFT 0x17
+#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__SHIFT 0x1c
+#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT 0x1f
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4_MASK 0x00100000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4_MASK 0x00200000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4_MASK 0x00400000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4_MASK 0x0F800000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4_MASK 0x70000000L
+#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4_MASK 0x80000000L
+//RCC_DEV0_EPF4_STRAP5
+#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F4__SHIFT 0x1e
+#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF4_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F4_MASK 0x40000000L
+//RCC_DEV0_EPF4_STRAP6
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x1
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4_MASK 0x00000001L
+#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4_MASK 0x00000002L
+//RCC_DEV0_EPF4_STRAP7
+#define RCC_DEV0_EPF4_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F4__SHIFT 0x5
+#define RCC_DEV0_EPF4_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F4_MASK 0x0000FFE0L
+//RCC_DEV0_EPF4_STRAP13
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__SHIFT 0x8
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__SHIFT 0x10
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4_MASK 0x000000FFL
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4_MASK 0x0000FF00L
+#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4_MASK 0x00FF0000L
+//RCC_DEV0_EPF4_STRAP14
+#define RCC_DEV0_EPF4_STRAP14__STRAP_VENDOR_ID_DEV0_F4__SHIFT 0x0
+#define RCC_DEV0_EPF4_STRAP14__STRAP_VENDOR_ID_DEV0_F4_MASK 0x0000FFFFL
+//RCC_DEV0_EPF5_STRAP0
+#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__SHIFT 0x10
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT 0x1c
+#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__SHIFT 0x1d
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT 0x1e
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT 0x1f
+#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5_MASK 0x000F0000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5_MASK 0x00F00000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5_MASK 0x10000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5_MASK 0x20000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5_MASK 0x40000000L
+#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5_MASK 0x80000000L
+//RCC_DEV0_EPF5_STRAP2
+#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__SHIFT 0x7
+#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__SHIFT 0x8
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F5__SHIFT 0x9
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__SHIFT 0xe
+#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT 0x10
+#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT 0x11
+#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT 0x15
+#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__SHIFT 0x17
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__SHIFT 0x18
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EN_DEV0_F5__SHIFT 0x1c
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5__SHIFT 0x1d
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5__SHIFT 0x1e
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5__SHIFT 0x1f
+#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5_MASK 0x00000080L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5_MASK 0x00000100L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F5_MASK 0x00003E00L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5_MASK 0x00004000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5_MASK 0x00010000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5_MASK 0x00020000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5_MASK 0x00100000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5_MASK 0x00200000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5_MASK 0x00800000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5_MASK 0x07000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EN_DEV0_F5_MASK 0x10000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5_MASK 0x20000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5_MASK 0x40000000L
+#define RCC_DEV0_EPF5_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5_MASK 0x80000000L
+//RCC_DEV0_EPF5_STRAP3
+#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT 0x1
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__SHIFT 0x2
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__SHIFT 0x12
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__SHIFT 0x13
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT 0x18
+#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT 0x1a
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT 0x1b
+#define RCC_DEV0_EPF5_STRAP3__STRAP_CLK_PM_EN_DEV0_F5__SHIFT 0x1d
+#define RCC_DEV0_EPF5_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F5__SHIFT 0x1e
+#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5_MASK 0x00000001L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5_MASK 0x00000002L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5_MASK 0x00040000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5_MASK 0x00080000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5_MASK 0x00100000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5_MASK 0x01000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5_MASK 0x04000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5_MASK 0x08000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_CLK_PM_EN_DEV0_F5_MASK 0x20000000L
+#define RCC_DEV0_EPF5_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F5_MASK 0x40000000L
+//RCC_DEV0_EPF5_STRAP4
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT 0x14
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT 0x15
+#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT 0x16
+#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT 0x17
+#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT 0x1c
+#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT 0x1f
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5_MASK 0x00100000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5_MASK 0x00200000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5_MASK 0x00400000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5_MASK 0x0F800000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5_MASK 0x70000000L
+#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5_MASK 0x80000000L
+//RCC_DEV0_EPF5_STRAP5
+#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F5__SHIFT 0x1e
+#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF5_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F5_MASK 0x40000000L
+//RCC_DEV0_EPF5_STRAP6
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x1
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5_MASK 0x00000001L
+#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5_MASK 0x00000002L
+//RCC_DEV0_EPF5_STRAP7
+//RCC_DEV0_EPF5_STRAP13
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__SHIFT 0x8
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__SHIFT 0x10
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5_MASK 0x000000FFL
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5_MASK 0x0000FF00L
+#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5_MASK 0x00FF0000L
+//RCC_DEV0_EPF5_STRAP14
+#define RCC_DEV0_EPF5_STRAP14__STRAP_VENDOR_ID_DEV0_F5__SHIFT 0x0
+#define RCC_DEV0_EPF5_STRAP14__STRAP_VENDOR_ID_DEV0_F5_MASK 0x0000FFFFL
+//RCC_DEV0_EPF6_STRAP0
+#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__SHIFT 0x10
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT 0x1c
+#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__SHIFT 0x1d
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT 0x1e
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT 0x1f
+#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6_MASK 0x000F0000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6_MASK 0x00F00000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6_MASK 0x10000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6_MASK 0x20000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6_MASK 0x40000000L
+#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6_MASK 0x80000000L
+//RCC_DEV0_EPF6_STRAP2
+#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__SHIFT 0x7
+#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__SHIFT 0x8
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F6__SHIFT 0x9
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__SHIFT 0xe
+#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT 0x10
+#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT 0x11
+#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT 0x15
+#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__SHIFT 0x17
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__SHIFT 0x18
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EN_DEV0_F6__SHIFT 0x1c
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6__SHIFT 0x1d
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6__SHIFT 0x1e
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6__SHIFT 0x1f
+#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6_MASK 0x00000080L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6_MASK 0x00000100L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F6_MASK 0x00003E00L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6_MASK 0x00004000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6_MASK 0x00010000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6_MASK 0x00020000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6_MASK 0x00100000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6_MASK 0x00200000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6_MASK 0x00800000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6_MASK 0x07000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EN_DEV0_F6_MASK 0x10000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6_MASK 0x20000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6_MASK 0x40000000L
+#define RCC_DEV0_EPF6_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6_MASK 0x80000000L
+//RCC_DEV0_EPF6_STRAP3
+#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT 0x1
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__SHIFT 0x2
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__SHIFT 0x12
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__SHIFT 0x13
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT 0x18
+#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT 0x1a
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT 0x1b
+#define RCC_DEV0_EPF6_STRAP3__STRAP_CLK_PM_EN_DEV0_F6__SHIFT 0x1d
+#define RCC_DEV0_EPF6_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F6__SHIFT 0x1e
+#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6_MASK 0x00000001L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6_MASK 0x00000002L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6_MASK 0x00040000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6_MASK 0x00080000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6_MASK 0x00100000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6_MASK 0x01000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6_MASK 0x04000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6_MASK 0x08000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_CLK_PM_EN_DEV0_F6_MASK 0x20000000L
+#define RCC_DEV0_EPF6_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F6_MASK 0x40000000L
+//RCC_DEV0_EPF6_STRAP4
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__SHIFT 0x14
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__SHIFT 0x15
+#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__SHIFT 0x16
+#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__SHIFT 0x17
+#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__SHIFT 0x1c
+#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT 0x1f
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6_MASK 0x00100000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6_MASK 0x00200000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6_MASK 0x00400000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6_MASK 0x0F800000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6_MASK 0x70000000L
+#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6_MASK 0x80000000L
+//RCC_DEV0_EPF6_STRAP5
+#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F6__SHIFT 0x1e
+#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF6_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F6_MASK 0x40000000L
+//RCC_DEV0_EPF6_STRAP6
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x1
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6_MASK 0x00000001L
+#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6_MASK 0x00000002L
+//RCC_DEV0_EPF6_STRAP7
+//RCC_DEV0_EPF6_STRAP13
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__SHIFT 0x8
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__SHIFT 0x10
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6_MASK 0x000000FFL
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6_MASK 0x0000FF00L
+#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6_MASK 0x00FF0000L
+//RCC_DEV0_EPF6_STRAP14
+#define RCC_DEV0_EPF6_STRAP14__STRAP_VENDOR_ID_DEV0_F6__SHIFT 0x0
+#define RCC_DEV0_EPF6_STRAP14__STRAP_VENDOR_ID_DEV0_F6_MASK 0x0000FFFFL
+//RCC_DEV0_EPF7_STRAP0
+#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__SHIFT 0x0
+#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__SHIFT 0x10
+#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__SHIFT 0x14
+#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__SHIFT 0x1c
+#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__SHIFT 0x1d
+#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__SHIFT 0x1e
+#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__SHIFT 0x1f
+#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7_MASK 0x000F0000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7_MASK 0x00F00000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7_MASK 0x10000000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7_MASK 0x20000000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7_MASK 0x40000000L
+#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7_MASK 0x80000000L
+//RCC_DEV0_EPF7_STRAP2
+#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__SHIFT 0x7
+#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__SHIFT 0x8
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F7__SHIFT 0x9
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__SHIFT 0xe
+#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__SHIFT 0x10
+#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__SHIFT 0x11
+#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__SHIFT 0x14
+#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__SHIFT 0x15
+#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__SHIFT 0x17
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__SHIFT 0x18
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_EN_DEV0_F7__SHIFT 0x1c
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F7__SHIFT 0x1d
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F7__SHIFT 0x1e
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F7__SHIFT 0x1f
+#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7_MASK 0x00000080L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7_MASK 0x00000100L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F7_MASK 0x00003E00L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7_MASK 0x00004000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7_MASK 0x00010000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7_MASK 0x00020000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7_MASK 0x00100000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7_MASK 0x00200000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7_MASK 0x00800000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7_MASK 0x07000000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_EN_DEV0_F7_MASK 0x10000000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F7_MASK 0x20000000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F7_MASK 0x40000000L
+#define RCC_DEV0_EPF7_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F7_MASK 0x80000000L
+//RCC_DEV0_EPF7_STRAP3
+#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__SHIFT 0x0
+#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__SHIFT 0x1
+#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__SHIFT 0x2
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__SHIFT 0x12
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__SHIFT 0x13
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__SHIFT 0x14
+#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__SHIFT 0x18
+#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__SHIFT 0x1a
+#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__SHIFT 0x1b
+#define RCC_DEV0_EPF7_STRAP3__STRAP_CLK_PM_EN_DEV0_F7__SHIFT 0x1d
+#define RCC_DEV0_EPF7_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F7__SHIFT 0x1e
+#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7_MASK 0x00000001L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7_MASK 0x00000002L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7_MASK 0x0003FFFCL
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7_MASK 0x00040000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7_MASK 0x00080000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7_MASK 0x00100000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7_MASK 0x01000000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7_MASK 0x04000000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7_MASK 0x08000000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_CLK_PM_EN_DEV0_F7_MASK 0x20000000L
+#define RCC_DEV0_EPF7_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F7_MASK 0x40000000L
+//RCC_DEV0_EPF7_STRAP4
+#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__SHIFT 0x14
+#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__SHIFT 0x15
+#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__SHIFT 0x16
+#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__SHIFT 0x17
+#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__SHIFT 0x1c
+#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__SHIFT 0x1f
+#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7_MASK 0x00100000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7_MASK 0x00200000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7_MASK 0x00400000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7_MASK 0x0F800000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7_MASK 0x70000000L
+#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7_MASK 0x80000000L
+//RCC_DEV0_EPF7_STRAP5
+#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__SHIFT 0x0
+#define RCC_DEV0_EPF7_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F7__SHIFT 0x1e
+#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7_MASK 0x0000FFFFL
+#define RCC_DEV0_EPF7_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F7_MASK 0x40000000L
+//RCC_DEV0_EPF7_STRAP6
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__SHIFT 0x0
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x1
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__SHIFT 0x8
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x9
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7_MASK 0x00000001L
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7_MASK 0x00000002L
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7_MASK 0x00000100L
+#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7_MASK 0x00000200L
+//RCC_DEV0_EPF7_STRAP7
+//RCC_DEV0_EPF7_STRAP13
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__SHIFT 0x0
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__SHIFT 0x8
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__SHIFT 0x10
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7_MASK 0x000000FFL
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7_MASK 0x0000FF00L
+#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7_MASK 0x00FF0000L
+//RCC_DEV0_EPF7_STRAP14
+#define RCC_DEV0_EPF7_STRAP14__STRAP_VENDOR_ID_DEV0_F7__SHIFT 0x0
+#define RCC_DEV0_EPF7_STRAP14__STRAP_VENDOR_ID_DEV0_F7_MASK 0x0000FFFFL
+//RCC_DEV1_EPF0_STRAP0
+#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__SHIFT 0x10
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__SHIFT 0x1c
+#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__SHIFT 0x1d
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__SHIFT 0x1e
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__SHIFT 0x1f
+#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0_MASK 0x0000FFFFL
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0_MASK 0x000F0000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0_MASK 0x00F00000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0_MASK 0x10000000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0_MASK 0x20000000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0_MASK 0x40000000L
+#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0_MASK 0x80000000L
+//RCC_DEV1_EPF0_STRAP2
+#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__SHIFT 0x7
+#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__SHIFT 0x8
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F0__SHIFT 0x9
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__SHIFT 0xe
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__SHIFT 0xf
+#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__SHIFT 0x10
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__SHIFT 0x11
+#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__SHIFT 0x15
+#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__SHIFT 0x17
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__SHIFT 0x18
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EN_DEV1_F0__SHIFT 0x1c
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F0__SHIFT 0x1d
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F0__SHIFT 0x1e
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F0__SHIFT 0x1f
+#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0_MASK 0x00000080L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0_MASK 0x00000100L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F0_MASK 0x00003E00L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0_MASK 0x00004000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0_MASK 0x00008000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0_MASK 0x00010000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0_MASK 0x00020000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0_MASK 0x00100000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0_MASK 0x00200000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0_MASK 0x00800000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0_MASK 0x07000000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EN_DEV1_F0_MASK 0x10000000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F0_MASK 0x20000000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F0_MASK 0x40000000L
+#define RCC_DEV1_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F0_MASK 0x80000000L
+//RCC_DEV1_EPF0_STRAP3
+#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__SHIFT 0x1
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__SHIFT 0x2
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__SHIFT 0x12
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__SHIFT 0x13
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__SHIFT 0x18
+#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__SHIFT 0x1a
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__SHIFT 0x1b
+#define RCC_DEV1_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV1_F0__SHIFT 0x1d
+#define RCC_DEV1_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV1_F0__SHIFT 0x1e
+#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0_MASK 0x00000001L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0_MASK 0x00000002L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0_MASK 0x0003FFFCL
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0_MASK 0x00040000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0_MASK 0x00080000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0_MASK 0x00100000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0_MASK 0x01000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0_MASK 0x04000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0_MASK 0x08000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV1_F0_MASK 0x20000000L
+#define RCC_DEV1_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV1_F0_MASK 0x40000000L
+//RCC_DEV1_EPF0_STRAP4
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__SHIFT 0x14
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__SHIFT 0x15
+#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__SHIFT 0x16
+#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__SHIFT 0x17
+#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__SHIFT 0x1c
+#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__SHIFT 0x1f
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0_MASK 0x00100000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0_MASK 0x00200000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0_MASK 0x00400000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0_MASK 0x0F800000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0_MASK 0x70000000L
+#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0_MASK 0x80000000L
+//RCC_DEV1_EPF0_STRAP5
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV1_F0__SHIFT 0x1e
+#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0_MASK 0x0000FFFFL
+#define RCC_DEV1_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV1_F0_MASK 0x40000000L
+//RCC_DEV1_EPF0_STRAP6
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__SHIFT 0x1
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0_MASK 0x00000001L
+#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0_MASK 0x00000002L
+//RCC_DEV1_EPF0_STRAP7
+//RCC_DEV1_EPF0_STRAP13
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__SHIFT 0x8
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__SHIFT 0x10
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0_MASK 0x000000FFL
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0_MASK 0x0000FF00L
+#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0_MASK 0x00FF0000L
+//RCC_DEV1_EPF0_STRAP14
+#define RCC_DEV1_EPF0_STRAP14__STRAP_VENDOR_ID_DEV1_F0__SHIFT 0x0
+#define RCC_DEV1_EPF0_STRAP14__STRAP_VENDOR_ID_DEV1_F0_MASK 0x0000FFFFL
+//RCC_DEV1_EPF1_STRAP0
+#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__SHIFT 0x0
+#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__SHIFT 0x10
+#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__SHIFT 0x14
+#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__SHIFT 0x1c
+#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__SHIFT 0x1d
+#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__SHIFT 0x1e
+#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__SHIFT 0x1f
+#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1_MASK 0x0000FFFFL
+#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1_MASK 0x000F0000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1_MASK 0x00F00000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1_MASK 0x10000000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1_MASK 0x20000000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1_MASK 0x40000000L
+#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1_MASK 0x80000000L
+//RCC_DEV1_EPF1_STRAP2
+#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__SHIFT 0x7
+#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__SHIFT 0x8
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F1__SHIFT 0x9
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__SHIFT 0xe
+#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__SHIFT 0x10
+#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__SHIFT 0x11
+#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__SHIFT 0x14
+#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__SHIFT 0x15
+#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__SHIFT 0x17
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__SHIFT 0x18
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_EN_DEV1_F1__SHIFT 0x1c
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F1__SHIFT 0x1d
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F1__SHIFT 0x1e
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F1__SHIFT 0x1f
+#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1_MASK 0x00000080L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1_MASK 0x00000100L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F1_MASK 0x00003E00L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1_MASK 0x00004000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1_MASK 0x00010000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1_MASK 0x00020000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1_MASK 0x00100000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1_MASK 0x00200000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1_MASK 0x00800000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1_MASK 0x07000000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_EN_DEV1_F1_MASK 0x10000000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F1_MASK 0x20000000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F1_MASK 0x40000000L
+#define RCC_DEV1_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F1_MASK 0x80000000L
+//RCC_DEV1_EPF1_STRAP3
+#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__SHIFT 0x0
+#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__SHIFT 0x1
+#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__SHIFT 0x2
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__SHIFT 0x12
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__SHIFT 0x13
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__SHIFT 0x14
+#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__SHIFT 0x18
+#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__SHIFT 0x1a
+#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__SHIFT 0x1b
+#define RCC_DEV1_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV1_F1__SHIFT 0x1d
+#define RCC_DEV1_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV1_F1__SHIFT 0x1e
+#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1_MASK 0x00000001L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1_MASK 0x00000002L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1_MASK 0x0003FFFCL
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1_MASK 0x00040000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1_MASK 0x00080000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1_MASK 0x00100000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1_MASK 0x01000000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1_MASK 0x04000000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1_MASK 0x08000000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV1_F1_MASK 0x20000000L
+#define RCC_DEV1_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV1_F1_MASK 0x40000000L
+//RCC_DEV1_EPF1_STRAP4
+#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__SHIFT 0x14
+#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__SHIFT 0x15
+#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__SHIFT 0x16
+#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__SHIFT 0x17
+#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__SHIFT 0x1c
+#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__SHIFT 0x1f
+#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1_MASK 0x00100000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1_MASK 0x00200000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1_MASK 0x00400000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1_MASK 0x0F800000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1_MASK 0x70000000L
+#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1_MASK 0x80000000L
+//RCC_DEV1_EPF1_STRAP5
+#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__SHIFT 0x0
+#define RCC_DEV1_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV1_F1__SHIFT 0x1e
+#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1_MASK 0x0000FFFFL
+#define RCC_DEV1_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV1_F1_MASK 0x40000000L
+//RCC_DEV1_EPF1_STRAP6
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__SHIFT 0x0
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x1
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__SHIFT 0x8
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x9
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__SHIFT 0x10
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x11
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1_MASK 0x00000001L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1_MASK 0x00000002L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1_MASK 0x00000100L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1_MASK 0x00000200L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1_MASK 0x00010000L
+#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1_MASK 0x00020000L
+//RCC_DEV1_EPF1_STRAP7
+#define RCC_DEV1_EPF1_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV1_F1__SHIFT 0x5
+#define RCC_DEV1_EPF1_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV1_F1_MASK 0x0000FFE0L
+//RCC_DEV1_EPF1_STRAP13
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__SHIFT 0x0
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__SHIFT 0x8
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__SHIFT 0x10
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1_MASK 0x000000FFL
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1_MASK 0x0000FF00L
+#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1_MASK 0x00FF0000L
+//RCC_DEV1_EPF1_STRAP14
+#define RCC_DEV1_EPF1_STRAP14__STRAP_VENDOR_ID_DEV1_F1__SHIFT 0x0
+#define RCC_DEV1_EPF1_STRAP14__STRAP_VENDOR_ID_DEV1_F1_MASK 0x0000FFFFL
+//RCC_DEV1_EPF2_STRAP0
+//RCC_DEV1_EPF2_STRAP2
+//RCC_DEV1_EPF2_STRAP3
+//RCC_DEV1_EPF2_STRAP4
+//RCC_DEV1_EPF2_STRAP5
+//RCC_DEV1_EPF2_STRAP6
+//RCC_DEV1_EPF2_STRAP13
+//RCC_DEV1_EPF2_STRAP14
+//RCC_DEV1_EPF3_STRAP0
+//RCC_DEV1_EPF3_STRAP2
+//RCC_DEV1_EPF3_STRAP3
+//RCC_DEV1_EPF3_STRAP4
+//RCC_DEV1_EPF3_STRAP5
+//RCC_DEV1_EPF3_STRAP6
+//RCC_DEV1_EPF3_STRAP13
+//RCC_DEV1_EPF3_STRAP14
+//RCC_DEV1_EPF4_STRAP0
+//RCC_DEV1_EPF4_STRAP2
+//RCC_DEV1_EPF4_STRAP3
+//RCC_DEV1_EPF4_STRAP4
+//RCC_DEV1_EPF4_STRAP5
+//RCC_DEV1_EPF4_STRAP6
+//RCC_DEV1_EPF4_STRAP13
+//RCC_DEV1_EPF4_STRAP14
+//RCC_DEV1_EPF5_STRAP0
+//RCC_DEV1_EPF5_STRAP2
+//RCC_DEV1_EPF5_STRAP3
+//RCC_DEV1_EPF5_STRAP4
+//RCC_DEV1_EPF5_STRAP5
+//RCC_DEV1_EPF5_STRAP6
+//RCC_DEV1_EPF5_STRAP13
+//RCC_DEV1_EPF5_STRAP14
+//RCC_DEV2_EPF0_STRAP0
+#define RCC_DEV2_EPF0_STRAP0__STRAP_DEVICE_ID_DEV2_F0__SHIFT 0x0
+#define RCC_DEV2_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F0__SHIFT 0x10
+#define RCC_DEV2_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV2_F0__SHIFT 0x14
+#define RCC_DEV2_EPF0_STRAP0__STRAP_FUNC_EN_DEV2_F0__SHIFT 0x1c
+#define RCC_DEV2_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F0__SHIFT 0x1d
+#define RCC_DEV2_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV2_F0__SHIFT 0x1e
+#define RCC_DEV2_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV2_F0__SHIFT 0x1f
+#define RCC_DEV2_EPF0_STRAP0__STRAP_DEVICE_ID_DEV2_F0_MASK 0x0000FFFFL
+#define RCC_DEV2_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F0_MASK 0x000F0000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV2_F0_MASK 0x00F00000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_FUNC_EN_DEV2_F0_MASK 0x10000000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F0_MASK 0x20000000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV2_F0_MASK 0x40000000L
+#define RCC_DEV2_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV2_F0_MASK 0x80000000L
+//RCC_DEV2_EPF0_STRAP2
+#define RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0__SHIFT 0x7
+#define RCC_DEV2_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F0__SHIFT 0x8
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F0__SHIFT 0x9
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F0__SHIFT 0xe
+#define RCC_DEV2_EPF0_STRAP2__STRAP_ARI_EN_DEV2_F0__SHIFT 0xf
+#define RCC_DEV2_EPF0_STRAP2__STRAP_AER_EN_DEV2_F0__SHIFT 0x10
+#define RCC_DEV2_EPF0_STRAP2__STRAP_ACS_EN_DEV2_F0__SHIFT 0x11
+#define RCC_DEV2_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F0__SHIFT 0x14
+#define RCC_DEV2_EPF0_STRAP2__STRAP_DPA_EN_DEV2_F0__SHIFT 0x15
+#define RCC_DEV2_EPF0_STRAP2__STRAP_VC_EN_DEV2_F0__SHIFT 0x17
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F0__SHIFT 0x18
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EN_DEV2_F0__SHIFT 0x1c
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F0__SHIFT 0x1d
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F0__SHIFT 0x1e
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F0__SHIFT 0x1f
+#define RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK 0x00000080L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F0_MASK 0x00000100L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F0_MASK 0x00003E00L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F0_MASK 0x00004000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_ARI_EN_DEV2_F0_MASK 0x00008000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_AER_EN_DEV2_F0_MASK 0x00010000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_ACS_EN_DEV2_F0_MASK 0x00020000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F0_MASK 0x00100000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_DPA_EN_DEV2_F0_MASK 0x00200000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_VC_EN_DEV2_F0_MASK 0x00800000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F0_MASK 0x07000000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EN_DEV2_F0_MASK 0x10000000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F0_MASK 0x20000000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F0_MASK 0x40000000L
+#define RCC_DEV2_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F0_MASK 0x80000000L
+//RCC_DEV2_EPF0_STRAP3
+#define RCC_DEV2_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F0__SHIFT 0x0
+#define RCC_DEV2_EPF0_STRAP3__STRAP_PWR_EN_DEV2_F0__SHIFT 0x1
+#define RCC_DEV2_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV2_F0__SHIFT 0x2
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_EN_DEV2_F0__SHIFT 0x12
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F0__SHIFT 0x13
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSIX_EN_DEV2_F0__SHIFT 0x14
+#define RCC_DEV2_EPF0_STRAP3__STRAP_PMC_DSI_DEV2_F0__SHIFT 0x18
+#define RCC_DEV2_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F0__SHIFT 0x1a
+#define RCC_DEV2_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F0__SHIFT 0x1b
+#define RCC_DEV2_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV2_F0__SHIFT 0x1d
+#define RCC_DEV2_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV2_F0__SHIFT 0x1e
+#define RCC_DEV2_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F0_MASK 0x00000001L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_PWR_EN_DEV2_F0_MASK 0x00000002L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV2_F0_MASK 0x0003FFFCL
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_EN_DEV2_F0_MASK 0x00040000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F0_MASK 0x00080000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_MSIX_EN_DEV2_F0_MASK 0x00100000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_PMC_DSI_DEV2_F0_MASK 0x01000000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F0_MASK 0x04000000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F0_MASK 0x08000000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV2_F0_MASK 0x20000000L
+#define RCC_DEV2_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV2_F0_MASK 0x40000000L
+//RCC_DEV2_EPF0_STRAP4
+#define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F0__SHIFT 0x14
+#define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV2_F0__SHIFT 0x15
+#define RCC_DEV2_EPF0_STRAP4__STRAP_FLR_EN_DEV2_F0__SHIFT 0x16
+#define RCC_DEV2_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV2_F0__SHIFT 0x17
+#define RCC_DEV2_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F0__SHIFT 0x1c
+#define RCC_DEV2_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV2_F0__SHIFT 0x1f
+#define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F0_MASK 0x00100000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV2_F0_MASK 0x00200000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_FLR_EN_DEV2_F0_MASK 0x00400000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV2_F0_MASK 0x0F800000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F0_MASK 0x70000000L
+#define RCC_DEV2_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV2_F0_MASK 0x80000000L
+//RCC_DEV2_EPF0_STRAP5
+#define RCC_DEV2_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F0__SHIFT 0x0
+#define RCC_DEV2_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F0__SHIFT 0x1e
+#define RCC_DEV2_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F0_MASK 0x0000FFFFL
+#define RCC_DEV2_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F0_MASK 0x40000000L
+//RCC_DEV2_EPF0_STRAP6
+#define RCC_DEV2_EPF0_STRAP6__STRAP_APER0_EN_DEV2_F0__SHIFT 0x0
+#define RCC_DEV2_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV2_F0__SHIFT 0x1
+#define RCC_DEV2_EPF0_STRAP6__STRAP_APER0_EN_DEV2_F0_MASK 0x00000001L
+#define RCC_DEV2_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV2_F0_MASK 0x00000002L
+//RCC_DEV2_EPF0_STRAP7
+#define RCC_DEV2_EPF0_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV2_F0__SHIFT 0x5
+#define RCC_DEV2_EPF0_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV2_F0_MASK 0x0000FFE0L
+//RCC_DEV2_EPF0_STRAP13
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F0__SHIFT 0x0
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F0__SHIFT 0x8
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F0__SHIFT 0x10
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F0_MASK 0x000000FFL
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F0_MASK 0x0000FF00L
+#define RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F0_MASK 0x00FF0000L
+//RCC_DEV2_EPF0_STRAP14
+#define RCC_DEV2_EPF0_STRAP14__STRAP_VENDOR_ID_DEV2_F0__SHIFT 0x0
+#define RCC_DEV2_EPF0_STRAP14__STRAP_VENDOR_ID_DEV2_F0_MASK 0x0000FFFFL
+//RCC_DEV2_EPF1_STRAP0
+#define RCC_DEV2_EPF1_STRAP0__STRAP_DEVICE_ID_DEV2_F1__SHIFT 0x0
+#define RCC_DEV2_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F1__SHIFT 0x10
+#define RCC_DEV2_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV2_F1__SHIFT 0x14
+#define RCC_DEV2_EPF1_STRAP0__STRAP_FUNC_EN_DEV2_F1__SHIFT 0x1c
+#define RCC_DEV2_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F1__SHIFT 0x1d
+#define RCC_DEV2_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV2_F1__SHIFT 0x1e
+#define RCC_DEV2_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV2_F1__SHIFT 0x1f
+#define RCC_DEV2_EPF1_STRAP0__STRAP_DEVICE_ID_DEV2_F1_MASK 0x0000FFFFL
+#define RCC_DEV2_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F1_MASK 0x000F0000L
+#define RCC_DEV2_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV2_F1_MASK 0x00F00000L
+#define RCC_DEV2_EPF1_STRAP0__STRAP_FUNC_EN_DEV2_F1_MASK 0x10000000L
+#define RCC_DEV2_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F1_MASK 0x20000000L
+#define RCC_DEV2_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV2_F1_MASK 0x40000000L
+#define RCC_DEV2_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV2_F1_MASK 0x80000000L
+//RCC_DEV2_EPF1_STRAP2
+#define RCC_DEV2_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F1__SHIFT 0x7
+#define RCC_DEV2_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F1__SHIFT 0x8
+#define RCC_DEV2_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F1__SHIFT 0x9
+#define RCC_DEV2_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F1__SHIFT 0xe
+#define RCC_DEV2_EPF1_STRAP2__STRAP_AER_EN_DEV2_F1__SHIFT 0x10
+#define RCC_DEV2_EPF1_STRAP2__STRAP_ACS_EN_DEV2_F1__SHIFT 0x11
+#define RCC_DEV2_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F1__SHIFT 0x14
+#define RCC_DEV2_EPF1_STRAP2__STRAP_DPA_EN_DEV2_F1__SHIFT 0x15
+#define RCC_DEV2_EPF1_STRAP2__STRAP_VC_EN_DEV2_F1__SHIFT 0x17
+#define RCC_DEV2_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F1__SHIFT 0x18
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_EN_DEV2_F1__SHIFT 0x1c
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F1__SHIFT 0x1d
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F1__SHIFT 0x1e
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F1__SHIFT 0x1f
+#define RCC_DEV2_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F1_MASK 0x00000080L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F1_MASK 0x00000100L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F1_MASK 0x00003E00L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F1_MASK 0x00004000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_AER_EN_DEV2_F1_MASK 0x00010000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_ACS_EN_DEV2_F1_MASK 0x00020000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F1_MASK 0x00100000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_DPA_EN_DEV2_F1_MASK 0x00200000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_VC_EN_DEV2_F1_MASK 0x00800000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F1_MASK 0x07000000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_EN_DEV2_F1_MASK 0x10000000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F1_MASK 0x20000000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F1_MASK 0x40000000L
+#define RCC_DEV2_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F1_MASK 0x80000000L
+//RCC_DEV2_EPF1_STRAP3
+#define RCC_DEV2_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F1__SHIFT 0x0
+#define RCC_DEV2_EPF1_STRAP3__STRAP_PWR_EN_DEV2_F1__SHIFT 0x1
+#define RCC_DEV2_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV2_F1__SHIFT 0x2
+#define RCC_DEV2_EPF1_STRAP3__STRAP_MSI_EN_DEV2_F1__SHIFT 0x12
+#define RCC_DEV2_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F1__SHIFT 0x13
+#define RCC_DEV2_EPF1_STRAP3__STRAP_MSIX_EN_DEV2_F1__SHIFT 0x14
+#define RCC_DEV2_EPF1_STRAP3__STRAP_PMC_DSI_DEV2_F1__SHIFT 0x18
+#define RCC_DEV2_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F1__SHIFT 0x1a
+#define RCC_DEV2_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F1__SHIFT 0x1b
+#define RCC_DEV2_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV2_F1__SHIFT 0x1d
+#define RCC_DEV2_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV2_F1__SHIFT 0x1e
+#define RCC_DEV2_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F1_MASK 0x00000001L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_PWR_EN_DEV2_F1_MASK 0x00000002L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV2_F1_MASK 0x0003FFFCL
+#define RCC_DEV2_EPF1_STRAP3__STRAP_MSI_EN_DEV2_F1_MASK 0x00040000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F1_MASK 0x00080000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_MSIX_EN_DEV2_F1_MASK 0x00100000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_PMC_DSI_DEV2_F1_MASK 0x01000000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F1_MASK 0x04000000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F1_MASK 0x08000000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV2_F1_MASK 0x20000000L
+#define RCC_DEV2_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV2_F1_MASK 0x40000000L
+//RCC_DEV2_EPF1_STRAP4
+#define RCC_DEV2_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F1__SHIFT 0x14
+#define RCC_DEV2_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV2_F1__SHIFT 0x15
+#define RCC_DEV2_EPF1_STRAP4__STRAP_FLR_EN_DEV2_F1__SHIFT 0x16
+#define RCC_DEV2_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV2_F1__SHIFT 0x17
+#define RCC_DEV2_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F1__SHIFT 0x1c
+#define RCC_DEV2_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV2_F1__SHIFT 0x1f
+#define RCC_DEV2_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F1_MASK 0x00100000L
+#define RCC_DEV2_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV2_F1_MASK 0x00200000L
+#define RCC_DEV2_EPF1_STRAP4__STRAP_FLR_EN_DEV2_F1_MASK 0x00400000L
+#define RCC_DEV2_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV2_F1_MASK 0x0F800000L
+#define RCC_DEV2_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F1_MASK 0x70000000L
+#define RCC_DEV2_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV2_F1_MASK 0x80000000L
+//RCC_DEV2_EPF1_STRAP5
+#define RCC_DEV2_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F1__SHIFT 0x0
+#define RCC_DEV2_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F1__SHIFT 0x1e
+#define RCC_DEV2_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F1_MASK 0x0000FFFFL
+#define RCC_DEV2_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F1_MASK 0x40000000L
+//RCC_DEV2_EPF1_STRAP6
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER0_EN_DEV2_F1__SHIFT 0x0
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER1_EN_DEV2_F1__SHIFT 0x8
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER2_EN_DEV2_F1__SHIFT 0x10
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER3_EN_DEV2_F1__SHIFT 0x18
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV2_F1__SHIFT 0x19
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER0_EN_DEV2_F1_MASK 0x00000001L
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER1_EN_DEV2_F1_MASK 0x00000100L
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER2_EN_DEV2_F1_MASK 0x00010000L
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER3_EN_DEV2_F1_MASK 0x01000000L
+#define RCC_DEV2_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV2_F1_MASK 0x02000000L
+//RCC_DEV2_EPF1_STRAP13
+#define RCC_DEV2_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F1__SHIFT 0x0
+#define RCC_DEV2_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F1__SHIFT 0x8
+#define RCC_DEV2_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F1__SHIFT 0x10
+#define RCC_DEV2_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F1_MASK 0x000000FFL
+#define RCC_DEV2_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F1_MASK 0x0000FF00L
+#define RCC_DEV2_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F1_MASK 0x00FF0000L
+//RCC_DEV2_EPF1_STRAP14
+#define RCC_DEV2_EPF1_STRAP14__STRAP_VENDOR_ID_DEV2_F1__SHIFT 0x0
+#define RCC_DEV2_EPF1_STRAP14__STRAP_VENDOR_ID_DEV2_F1_MASK 0x0000FFFFL
+//RCC_DEV2_EPF2_STRAP0
+#define RCC_DEV2_EPF2_STRAP0__STRAP_DEVICE_ID_DEV2_F2__SHIFT 0x0
+#define RCC_DEV2_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F2__SHIFT 0x10
+#define RCC_DEV2_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV2_F2__SHIFT 0x14
+#define RCC_DEV2_EPF2_STRAP0__STRAP_FUNC_EN_DEV2_F2__SHIFT 0x1c
+#define RCC_DEV2_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F2__SHIFT 0x1d
+#define RCC_DEV2_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV2_F2__SHIFT 0x1e
+#define RCC_DEV2_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV2_F2__SHIFT 0x1f
+#define RCC_DEV2_EPF2_STRAP0__STRAP_DEVICE_ID_DEV2_F2_MASK 0x0000FFFFL
+#define RCC_DEV2_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F2_MASK 0x000F0000L
+#define RCC_DEV2_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV2_F2_MASK 0x00F00000L
+#define RCC_DEV2_EPF2_STRAP0__STRAP_FUNC_EN_DEV2_F2_MASK 0x10000000L
+#define RCC_DEV2_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F2_MASK 0x20000000L
+#define RCC_DEV2_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV2_F2_MASK 0x40000000L
+#define RCC_DEV2_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV2_F2_MASK 0x80000000L
+//RCC_DEV2_EPF2_STRAP2
+#define RCC_DEV2_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F2__SHIFT 0x7
+#define RCC_DEV2_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F2__SHIFT 0x8
+#define RCC_DEV2_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F2__SHIFT 0x9
+#define RCC_DEV2_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F2__SHIFT 0xe
+#define RCC_DEV2_EPF2_STRAP2__STRAP_AER_EN_DEV2_F2__SHIFT 0x10
+#define RCC_DEV2_EPF2_STRAP2__STRAP_ACS_EN_DEV2_F2__SHIFT 0x11
+#define RCC_DEV2_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F2__SHIFT 0x14
+#define RCC_DEV2_EPF2_STRAP2__STRAP_DPA_EN_DEV2_F2__SHIFT 0x15
+#define RCC_DEV2_EPF2_STRAP2__STRAP_VC_EN_DEV2_F2__SHIFT 0x17
+#define RCC_DEV2_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F2__SHIFT 0x18
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_EN_DEV2_F2__SHIFT 0x1c
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F2__SHIFT 0x1d
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F2__SHIFT 0x1e
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F2__SHIFT 0x1f
+#define RCC_DEV2_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F2_MASK 0x00000080L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F2_MASK 0x00000100L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F2_MASK 0x00003E00L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F2_MASK 0x00004000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_AER_EN_DEV2_F2_MASK 0x00010000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_ACS_EN_DEV2_F2_MASK 0x00020000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F2_MASK 0x00100000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_DPA_EN_DEV2_F2_MASK 0x00200000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_VC_EN_DEV2_F2_MASK 0x00800000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F2_MASK 0x07000000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_EN_DEV2_F2_MASK 0x10000000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F2_MASK 0x20000000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F2_MASK 0x40000000L
+#define RCC_DEV2_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F2_MASK 0x80000000L
+//RCC_DEV2_EPF2_STRAP3
+#define RCC_DEV2_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F2__SHIFT 0x0
+#define RCC_DEV2_EPF2_STRAP3__STRAP_PWR_EN_DEV2_F2__SHIFT 0x1
+#define RCC_DEV2_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV2_F2__SHIFT 0x2
+#define RCC_DEV2_EPF2_STRAP3__STRAP_MSI_EN_DEV2_F2__SHIFT 0x12
+#define RCC_DEV2_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F2__SHIFT 0x13
+#define RCC_DEV2_EPF2_STRAP3__STRAP_MSIX_EN_DEV2_F2__SHIFT 0x14
+#define RCC_DEV2_EPF2_STRAP3__STRAP_PMC_DSI_DEV2_F2__SHIFT 0x18
+#define RCC_DEV2_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F2__SHIFT 0x1a
+#define RCC_DEV2_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F2__SHIFT 0x1b
+#define RCC_DEV2_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV2_F2__SHIFT 0x1d
+#define RCC_DEV2_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV2_F2__SHIFT 0x1e
+#define RCC_DEV2_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F2_MASK 0x00000001L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_PWR_EN_DEV2_F2_MASK 0x00000002L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV2_F2_MASK 0x0003FFFCL
+#define RCC_DEV2_EPF2_STRAP3__STRAP_MSI_EN_DEV2_F2_MASK 0x00040000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F2_MASK 0x00080000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_MSIX_EN_DEV2_F2_MASK 0x00100000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_PMC_DSI_DEV2_F2_MASK 0x01000000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F2_MASK 0x04000000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F2_MASK 0x08000000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_CLK_PM_EN_DEV2_F2_MASK 0x20000000L
+#define RCC_DEV2_EPF2_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV2_F2_MASK 0x40000000L
+//RCC_DEV2_EPF2_STRAP4
+#define RCC_DEV2_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F2__SHIFT 0x14
+#define RCC_DEV2_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV2_F2__SHIFT 0x15
+#define RCC_DEV2_EPF2_STRAP4__STRAP_FLR_EN_DEV2_F2__SHIFT 0x16
+#define RCC_DEV2_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV2_F2__SHIFT 0x17
+#define RCC_DEV2_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F2__SHIFT 0x1c
+#define RCC_DEV2_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV2_F2__SHIFT 0x1f
+#define RCC_DEV2_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F2_MASK 0x00100000L
+#define RCC_DEV2_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV2_F2_MASK 0x00200000L
+#define RCC_DEV2_EPF2_STRAP4__STRAP_FLR_EN_DEV2_F2_MASK 0x00400000L
+#define RCC_DEV2_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV2_F2_MASK 0x0F800000L
+#define RCC_DEV2_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F2_MASK 0x70000000L
+#define RCC_DEV2_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV2_F2_MASK 0x80000000L
+//RCC_DEV2_EPF2_STRAP5
+#define RCC_DEV2_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F2__SHIFT 0x0
+#define RCC_DEV2_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F2__SHIFT 0x1e
+#define RCC_DEV2_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F2_MASK 0x0000FFFFL
+#define RCC_DEV2_EPF2_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV2_F2_MASK 0x40000000L
+//RCC_DEV2_EPF2_STRAP6
+#define RCC_DEV2_EPF2_STRAP6__STRAP_APER0_EN_DEV2_F2__SHIFT 0x0
+#define RCC_DEV2_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV2_F2__SHIFT 0x1
+#define RCC_DEV2_EPF2_STRAP6__STRAP_APER1_EN_DEV2_F2__SHIFT 0x8
+#define RCC_DEV2_EPF2_STRAP6__STRAP_APER0_EN_DEV2_F2_MASK 0x00000001L
+#define RCC_DEV2_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV2_F2_MASK 0x00000002L
+#define RCC_DEV2_EPF2_STRAP6__STRAP_APER1_EN_DEV2_F2_MASK 0x00000100L
+//RCC_DEV2_EPF2_STRAP13
+#define RCC_DEV2_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F2__SHIFT 0x0
+#define RCC_DEV2_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F2__SHIFT 0x8
+#define RCC_DEV2_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F2__SHIFT 0x10
+#define RCC_DEV2_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F2_MASK 0x000000FFL
+#define RCC_DEV2_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F2_MASK 0x0000FF00L
+#define RCC_DEV2_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F2_MASK 0x00FF0000L
+//RCC_DEV2_EPF2_STRAP14
+#define RCC_DEV2_EPF2_STRAP14__STRAP_VENDOR_ID_DEV2_F2__SHIFT 0x0
+#define RCC_DEV2_EPF2_STRAP14__STRAP_VENDOR_ID_DEV2_F2_MASK 0x0000FFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_RCCPORTDEC
+//RCC_DEV0_2_RCC_VDM_SUPPORT
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_DEV0_2_RCC_BUS_CNTL
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_DEV0_2_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L
+//RCC_DEV0_2_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_DEV0_2_RCC_MH_ARB_CNTL
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L
+//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC
+//RCC_EP_DEV0_2_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_2_EP_PCIE_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_2_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_2_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_2_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_2_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC
+//RCC_DWN_DEV0_2_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_2_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_2_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC
+//RCC_DWNP_DEV0_2_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV0_2_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+//RCC_DWNP_DEV0_2_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev1_RCCPORTDEC
+//RCC_DEV1_RCC_VDM_SUPPORT
+#define RCC_DEV1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_DEV1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_DEV1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_DEV1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_DEV1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_DEV1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_DEV1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_DEV1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_DEV1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_DEV1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_DEV1_RCC_BUS_CNTL
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_DEV1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_DEV1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_DEV1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_DEV1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_DEV1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_DEV1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_DEV1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_DEV1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_DEV1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_DEV1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_DEV1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_DEV1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_DEV1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_DEV1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_DEV1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_DEV1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_DEV1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_DEV1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_DEV1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_DEV1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_DEV1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_DEV1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_DEV1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_DEV1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_DEV1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_DEV1_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_DEV1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_DEV1_RCC_DEV0_LINK_CNTL
+#define RCC_DEV1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+#define RCC_DEV1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L
+#define RCC_DEV1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L
+//RCC_DEV1_RCC_CMN_LINK_CNTL
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_DEV1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_DEV1_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_DEV1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_DEV1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_DEV1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_DEV1_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_DEV1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_DEV1_RCC_MH_ARB_CNTL
+#define RCC_DEV1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_DEV1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_DEV1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_DEV1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+//RCC_DEV1_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L
+//RCC_DEV1_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L
+#define RCC_DEV1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev1_RCCPORTDEC
+//RCC_EP_DEV1_EP_PCIE_SCRATCH
+#define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV1_EP_PCIE_CNTL
+#define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV1_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV1_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV1_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV1_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV1_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV1_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_EP_DEV1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_EP_DEV1_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define RCC_EP_DEV1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+//RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV1_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV1_EP_PCIEP_RESERVED
+#define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV1_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV1_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV1_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev1_RCCPORTDEC
+//RCC_DWN_DEV1_DN_PCIE_RESERVED
+#define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV1_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV1_DN_PCIE_CNTL
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV1_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV1_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV1_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_DWN_DEV1_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+//RCC_DWN_DEV1_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_DWN_DEV1_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define RCC_DWN_DEV1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev1_RCCPORTDEC
+//RCC_DWNP_DEV1_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV1_PCIE_RX_CNTL
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+//RCC_DWNP_DEV1_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV1_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev2_RCCPORTDEC
+//RCC_DEV2_RCC_VDM_SUPPORT
+#define RCC_DEV2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_DEV2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_DEV2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_DEV2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_DEV2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_DEV2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_DEV2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_DEV2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_DEV2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_DEV2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_DEV2_RCC_BUS_CNTL
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_DEV2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_DEV2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_DEV2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_DEV2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_DEV2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_DEV2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_DEV2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_DEV2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_DEV2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_DEV2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_DEV2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_DEV2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_DEV2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_DEV2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_DEV2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_DEV2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_DEV2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_DEV2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_DEV2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_DEV2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_DEV2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_DEV2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_DEV2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_DEV2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_DEV2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_DEV2_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_DEV2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_DEV2_RCC_DEV0_LINK_CNTL
+#define RCC_DEV2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+#define RCC_DEV2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L
+#define RCC_DEV2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L
+//RCC_DEV2_RCC_CMN_LINK_CNTL
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_DEV2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_DEV2_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_DEV2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_DEV2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_DEV2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_DEV2_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_DEV2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_DEV2_RCC_MH_ARB_CNTL
+#define RCC_DEV2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_DEV2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_DEV2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_DEV2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+//RCC_DEV2_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L
+//RCC_DEV2_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L
+#define RCC_DEV2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev2_RCCPORTDEC
+//RCC_EP_DEV2_EP_PCIE_SCRATCH
+#define RCC_EP_DEV2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV2_EP_PCIE_CNTL
+#define RCC_EP_DEV2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV2_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV2_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV2_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV2_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV2_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_EP_DEV2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV2_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_EP_DEV2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_EP_DEV2_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define RCC_EP_DEV2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+//RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV2_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV2_EP_PCIEP_RESERVED
+#define RCC_EP_DEV2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV2_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV2_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV2_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_EP_DEV2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev2_RCCPORTDEC
+//RCC_DWN_DEV2_DN_PCIE_RESERVED
+#define RCC_DWN_DEV2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV2_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV2_DN_PCIE_CNTL
+#define RCC_DWN_DEV2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV2_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV2_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV2_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_DWN_DEV2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_DWN_DEV2_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+//RCC_DWN_DEV2_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_DWN_DEV2_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define RCC_DWN_DEV2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev2_RCCPORTDEC
+//RCC_DWNP_DEV2_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV2_PCIE_RX_CNTL
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_DWNP_DEV2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+//RCC_DWNP_DEV2_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV2_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk
+//NBIF_STRAP_BIOS_CNTL
+#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT 0x0
+#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK 0x00000001L
+//MISC_SCRATCH
+#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0
+#define MISC_SCRATCH__MISC_SCRATCH0_MASK 0xFFFFFFFFL
+//INTR_LINE_POLARITY
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1__SHIFT 0x8
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV2__SHIFT 0x10
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK 0x000000FFL
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV1_MASK 0x0000FF00L
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV2_MASK 0x00FF0000L
+//INTR_LINE_ENABLE
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1__SHIFT 0x8
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV2__SHIFT 0x10
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK 0x000000FFL
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV1_MASK 0x0000FF00L
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV2_MASK 0x00FF0000L
+//OUTSTANDING_VC_ALLOC
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK 0x00000003L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK 0x0000000CL
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK 0x00000030L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK 0x000000C0L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK 0x00000300L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK 0x00000C00L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK 0x00003000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK 0x0000C000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK 0x000F0000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK 0x03000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK 0x0C000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK 0xF0000000L
+//BIFC_MISC_CTRL0
+#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT 0x4
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT 0xb
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT 0xc
+#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT 0xd
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT 0x12
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT 0x13
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT 0x14
+#define BIFC_MISC_CTRL0__VC5_DMA_IOCFG_DIS__SHIFT 0x17
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18
+#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f
+#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK 0x000000F0L
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK 0x00000100L
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK 0x00000200L
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK 0x00000400L
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK 0x00000800L
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK 0x00001000L
+#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK 0x00002000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK 0x00010000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK 0x00020000L
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK 0x00040000L
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK 0x00080000L
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK 0x00100000L
+#define BIFC_MISC_CTRL0__VC5_DMA_IOCFG_DIS_MASK 0x00800000L
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK 0x01000000L
+#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK 0x02000000L
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK 0x04000000L
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK 0x08000000L
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK 0x10000000L
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK 0x80000000L
+//BIFC_MISC_CTRL1
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT 0x7
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT 0x14
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT 0x17
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT 0x18
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT 0x19
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT 0x1a
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT 0x1b
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT 0x1c
+#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT 0x1d
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x1e
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK 0x00000001L
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK 0x00000002L
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK 0x00000004L
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK 0x00000008L
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK 0x00000010L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK 0x00000020L
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK 0x00000040L
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK 0x00000080L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK 0x00000300L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK 0x00000C00L
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK 0x00001000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK 0x00002000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK 0x00004000L
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK 0x00008000L
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK 0x00010000L
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK 0x00020000L
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK 0x00040000L
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK 0x00080000L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK 0x00100000L
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK 0x00800000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK 0x01000000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK 0x02000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK 0x04000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK 0x08000000L
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK 0x10000000L
+#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK 0x20000000L
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK 0xC0000000L
+//BIFC_BME_ERR_LOG
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F0__SHIFT 0x8
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F1__SHIFT 0x9
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV2_F0__SHIFT 0xc
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV2_F1__SHIFT 0xd
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV2_F2__SHIFT 0xe
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F0__SHIFT 0x18
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F1__SHIFT 0x19
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV2_F0__SHIFT 0x1c
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV2_F1__SHIFT 0x1d
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV2_F2__SHIFT 0x1e
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0_MASK 0x00000001L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1_MASK 0x00000002L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2_MASK 0x00000004L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3_MASK 0x00000008L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4_MASK 0x00000010L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5_MASK 0x00000020L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6_MASK 0x00000040L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7_MASK 0x00000080L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F0_MASK 0x00000100L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV1_F1_MASK 0x00000200L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV2_F0_MASK 0x00001000L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV2_F1_MASK 0x00002000L
+#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV2_F2_MASK 0x00004000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK 0x00010000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK 0x00020000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK 0x00040000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK 0x00080000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4_MASK 0x00100000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5_MASK 0x00200000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6_MASK 0x00400000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7_MASK 0x00800000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F0_MASK 0x01000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV1_F1_MASK 0x02000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV2_F0_MASK 0x10000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV2_F1_MASK 0x20000000L
+#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV2_F2_MASK 0x40000000L
+//BIFC_LC_TIMER_CTRL
+#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT 0x0
+#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT 0x10
+#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK 0x0000FFFFL
+#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK 0xFFFF0000L
+//BIFC_RCCBIH_BME_ERR_LOG0
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT 0x8
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT 0x9
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0__SHIFT 0x18
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1__SHIFT 0x19
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00000001L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00000002L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00000004L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00000008L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00000010L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00000020L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00000040L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00000080L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F0_MASK 0x00000100L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV1_F1_MASK 0x00000200L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK 0x00010000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK 0x00020000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK 0x00040000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK 0x00080000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK 0x00100000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK 0x00200000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK 0x00400000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK 0x00800000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F0_MASK 0x01000000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV1_F1_MASK 0x02000000L
+//BIFC_RCCBIH_BME_ERR_LOG1
+#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F0__SHIFT 0x0
+#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F1__SHIFT 0x1
+#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F2__SHIFT 0x2
+#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F0__SHIFT 0x10
+#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F1__SHIFT 0x11
+#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F2__SHIFT 0x12
+#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F0_MASK 0x00000001L
+#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F1_MASK 0x00000002L
+#define BIFC_RCCBIH_BME_ERR_LOG1__RCCBIH_ON_BME_LOW_DEV2_F2_MASK 0x00000004L
+#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F0_MASK 0x00010000L
+#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F1_MASK 0x00020000L
+#define BIFC_RCCBIH_BME_ERR_LOG1__CLEAR_RCCBIH_ON_BME_LOW_DEV2_F2_MASK 0x00040000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F0__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F0__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F1__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F1__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F0_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F0_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F0_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F0_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F0_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F0_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F0_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F0_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_P_DEV1_F1_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_IDO_OVERIDE_NP_DEV1_F1_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_IDO_DEV1_F1_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_P_DEV1_F1_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_RO_OVERIDE_NP_DEV1_F1_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_P_DEV1_F1_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__TX_SNR_OVERIDE_NP_DEV1_F1_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1__BLKLVL_FOR_NONIDO_DEV1_F1_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F2__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F2__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F3__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F3__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F2_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F2_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F2_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F2_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F2_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F2_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F2_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F2_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_P_DEV1_F3_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_IDO_OVERIDE_NP_DEV1_F3_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_IDO_DEV1_F3_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_P_DEV1_F3_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_RO_OVERIDE_NP_DEV1_F3_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_P_DEV1_F3_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__TX_SNR_OVERIDE_NP_DEV1_F3_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3__BLKLVL_FOR_NONIDO_DEV1_F3_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F4__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F4__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F5__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F5__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F4_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F4_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F4_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F4_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F4_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F4_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F4_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F4_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_P_DEV1_F5_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_IDO_OVERIDE_NP_DEV1_F5_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_IDO_DEV1_F5_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_P_DEV1_F5_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_RO_OVERIDE_NP_DEV1_F5_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_P_DEV1_F5_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__TX_SNR_OVERIDE_NP_DEV1_F5_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5__BLKLVL_FOR_NONIDO_DEV1_F5_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F6__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F6__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F7__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F7__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F6_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F6_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F6_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F6_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F6_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F6_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F6_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F6_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_P_DEV1_F7_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_IDO_OVERIDE_NP_DEV1_F7_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_IDO_DEV1_F7_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_P_DEV1_F7_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_RO_OVERIDE_NP_DEV1_F7_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_P_DEV1_F7_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__TX_SNR_OVERIDE_NP_DEV1_F7_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7__BLKLVL_FOR_NONIDO_DEV1_F7_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F0__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F0__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F0__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F0__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F0__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F0__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F0__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F1__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F1__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F1__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F1__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F1__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F1__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F1__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F1__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F0_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F0_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F0_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F0_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F0_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F0_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F0_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F0_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_P_DEV2_F1_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_IDO_OVERIDE_NP_DEV2_F1_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_IDO_DEV2_F1_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_P_DEV2_F1_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_RO_OVERIDE_NP_DEV2_F1_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_P_DEV2_F1_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__TX_SNR_OVERIDE_NP_DEV2_F1_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F0_F1__BLKLVL_FOR_NONIDO_DEV2_F1_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F2__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F2__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F2__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F2__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F2__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F2__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F2__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F3__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F3__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F3__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F3__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F3__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F3__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F3__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F3__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F2_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F2_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F2_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F2_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F2_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F2_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F2_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F2_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_P_DEV2_F3_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_IDO_OVERIDE_NP_DEV2_F3_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_IDO_DEV2_F3_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_P_DEV2_F3_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_RO_OVERIDE_NP_DEV2_F3_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_P_DEV2_F3_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__TX_SNR_OVERIDE_NP_DEV2_F3_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F2_F3__BLKLVL_FOR_NONIDO_DEV2_F3_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F4__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F4__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F4__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F4__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F4__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F4__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F4__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F4__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F5__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F5__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F5__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F5__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F5__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F5__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F5__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F5__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F4_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F4_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F4_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F4_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F4_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F4_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F4_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F4_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_P_DEV2_F5_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_IDO_OVERIDE_NP_DEV2_F5_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_IDO_DEV2_F5_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_P_DEV2_F5_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_RO_OVERIDE_NP_DEV2_F5_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_P_DEV2_F5_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__TX_SNR_OVERIDE_NP_DEV2_F5_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F4_F5__BLKLVL_FOR_NONIDO_DEV2_F5_MASK 0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F6__SHIFT 0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F6__SHIFT 0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F6__SHIFT 0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F6__SHIFT 0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F6__SHIFT 0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F6__SHIFT 0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F6__SHIFT 0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F6__SHIFT 0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F7__SHIFT 0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F7__SHIFT 0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F7__SHIFT 0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F7__SHIFT 0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F7__SHIFT 0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F7__SHIFT 0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F7__SHIFT 0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F6_MASK 0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F6_MASK 0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F6_MASK 0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F6_MASK 0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F6_MASK 0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F6_MASK 0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F6_MASK 0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F6_MASK 0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_P_DEV2_F7_MASK 0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_IDO_OVERIDE_NP_DEV2_F7_MASK 0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_IDO_DEV2_F7_MASK 0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_P_DEV2_F7_MASK 0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_RO_OVERIDE_NP_DEV2_F7_MASK 0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_P_DEV2_F7_MASK 0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__TX_SNR_OVERIDE_NP_DEV2_F7_MASK 0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV2_F6_F7__BLKLVL_FOR_NONIDO_DEV2_F7_MASK 0xC0000000L
+//BIFC_DMA_ATTR_CNTL2_DEV0
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT 0x4
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT 0xc
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT 0x10
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT 0x14
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT 0x18
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK 0x00000001L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK 0x00000010L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK 0x00000100L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK 0x00001000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK 0x00010000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK 0x00100000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK 0x01000000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK 0x10000000L
+//BIFC_DMA_ATTR_CNTL2_DEV1
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F1__SHIFT 0x4
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F3__SHIFT 0xc
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F4__SHIFT 0x10
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F5__SHIFT 0x14
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F6__SHIFT 0x18
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F0_MASK 0x00000001L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F1_MASK 0x00000010L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F2_MASK 0x00000100L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F3_MASK 0x00001000L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F4_MASK 0x00010000L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F5_MASK 0x00100000L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F6_MASK 0x01000000L
+#define BIFC_DMA_ATTR_CNTL2_DEV1__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV1_F7_MASK 0x10000000L
+//BIFC_DMA_ATTR_CNTL2_DEV2
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F0__SHIFT 0x0
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F1__SHIFT 0x4
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F2__SHIFT 0x8
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F3__SHIFT 0xc
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F4__SHIFT 0x10
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F5__SHIFT 0x14
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F6__SHIFT 0x18
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F7__SHIFT 0x1c
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F0_MASK 0x00000001L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F1_MASK 0x00000010L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F2_MASK 0x00000100L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F3_MASK 0x00001000L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F4_MASK 0x00010000L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F5_MASK 0x00100000L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F6_MASK 0x01000000L
+#define BIFC_DMA_ATTR_CNTL2_DEV2__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV2_F7_MASK 0x10000000L
+//BME_DUMMY_CNTL_0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0__SHIFT 0x10
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1__SHIFT 0x12
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2__SHIFT 0x14
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3__SHIFT 0x16
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4__SHIFT 0x18
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5__SHIFT 0x1a
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6__SHIFT 0x1c
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7__SHIFT 0x1e
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK 0x00000003L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK 0x0000000CL
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK 0x00000030L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK 0x000000C0L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK 0x00000300L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK 0x00000C00L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK 0x00003000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK 0x0000C000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F0_MASK 0x00030000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F1_MASK 0x000C0000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F2_MASK 0x00300000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F3_MASK 0x00C00000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F4_MASK 0x03000000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F5_MASK 0x0C000000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F6_MASK 0x30000000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV1_F7_MASK 0xC0000000L
+//BME_DUMMY_CNTL_1
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F0__SHIFT 0x0
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F1__SHIFT 0x2
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F2__SHIFT 0x4
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F3__SHIFT 0x6
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F4__SHIFT 0x8
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F5__SHIFT 0xa
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F6__SHIFT 0xc
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F7__SHIFT 0xe
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F0_MASK 0x00000003L
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F1_MASK 0x0000000CL
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F2_MASK 0x00000030L
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F3_MASK 0x000000C0L
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F4_MASK 0x00000300L
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F5_MASK 0x00000C00L
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F6_MASK 0x00003000L
+#define BME_DUMMY_CNTL_1__BME_DUMMY_RSPSTS_DEV2_F7_MASK 0x0000C000L
+//BIFC_HSTARB_CNTL
+#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0
+#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT 0x8
+#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK 0x00000003L
+#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK 0x00000100L
+//BIFC_GSI_CNTL
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc
+#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT 0xe
+#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT 0xf
+#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT 0x10
+#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT 0x11
+#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT 0x1b
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT 0x1c
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT 0x1d
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT 0x1e
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT 0x1f
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK 0x00000003L
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK 0x0000001CL
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK 0x00000020L
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK 0x00000040L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK 0x00000080L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK 0x00000100L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK 0x00000200L
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK 0x00000C00L
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK 0x00003000L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK 0x00004000L
+#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK 0x00008000L
+#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK 0x00010000L
+#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK 0x00020000L
+#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK 0x08000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK 0x10000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK 0x20000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK 0x40000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK 0x80000000L
+//BIFC_PCIEFUNC_CNTL
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK 0x0000FFFFL
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK 0x00010000L
+//BIFC_PASID_CHECK_DIS
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT 0x0
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT 0x1
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2__SHIFT 0x2
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3__SHIFT 0x3
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F4__SHIFT 0x4
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F5__SHIFT 0x5
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F6__SHIFT 0x6
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F7__SHIFT 0x7
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F0__SHIFT 0x8
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F1__SHIFT 0x9
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F0__SHIFT 0x10
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F1__SHIFT 0x11
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F2__SHIFT 0x12
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK 0x00000001L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK 0x00000002L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F2_MASK 0x00000004L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F3_MASK 0x00000008L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F4_MASK 0x00000010L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F5_MASK 0x00000020L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F6_MASK 0x00000040L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F7_MASK 0x00000080L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F0_MASK 0x00000100L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV1_F1_MASK 0x00000200L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F0_MASK 0x00010000L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F1_MASK 0x00020000L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV2_F2_MASK 0x00040000L
+//BIFC_SDP_CNTL_0
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x8
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0x10
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x18
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK 0x000000FFL
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK 0x0000FF00L
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK 0x00FF0000L
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK 0xFF000000L
+//BIFC_SDP_CNTL_1
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT 0x1
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT 0x2
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT 0x3
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x4
+#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT 0x5
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT 0x7
+#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT 0x8
+#define BIFC_SDP_CNTL_1__NBIF_OBFF_HW_URGENT_EARLY_WAKEUP_EN__SHIFT 0x1e
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK 0x00000001L
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK 0x00000002L
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK 0x00000004L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK 0x00000008L
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000010L
+#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK 0x00000020L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK 0x00000080L
+#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK 0x00000100L
+#define BIFC_SDP_CNTL_1__NBIF_OBFF_HW_URGENT_EARLY_WAKEUP_EN_MASK 0x40000000L
+//BIFC_PASID_STS
+#define BIFC_PASID_STS__PASID_STS__SHIFT 0x0
+#define BIFC_PASID_STS__PASID_STS_MASK 0x0000000FL
+//BIFC_ATHUB_ACT_CNTL
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT 0x0
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT 0x8
+#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS__SHIFT 0x9
+#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS__SHIFT 0xa
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT 0xb
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK 0x00000007L
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK 0x00000100L
+#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_DIS_MASK 0x00000200L
+#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_DIS_MASK 0x00000400L
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK 0x00000800L
+//BIFC_PERF_CNTL_0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK 0x00000001L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK 0x00000002L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK 0x00000100L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK 0x00000200L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK 0x007F0000L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK 0x7F000000L
+//BIFC_PERF_CNTL_1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK 0x00000001L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK 0x00000002L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK 0x00000100L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK 0x00000200L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK 0x007F0000L
+#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK 0xFF000000L
+//BIFC_PERF_CNT_MMIO_RD
+#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_MMIO_WR
+#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_RD
+#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE_MASK 0xFFFFFFFFL
+//BIFC_PERF_CNT_DMA_WR
+#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0
+#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE_MASK 0xFFFFFFFFL
+//NBIF_REGIF_ERRSET_CTRL
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//BIFC_SDP_CNTL_2
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT 0x0
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT 0x8
+#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT 0x10
+#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT 0x18
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK 0x000000FFL
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK 0x00000F00L
+#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L
+#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK 0x0F000000L
+//NBIF_PGMST_CTRL
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT 0x0
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT 0x8
+#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT 0xe
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK 0x00000100L
+#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L
+//NBIF_PGSLV_CTRL
+#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT 0x0
+#define NBIF_PGSLV_CTRL__NBIF_CFG_PGSLV_EXTCLK_0_IDLE_HYSTERESIS__SHIFT 0x5
+#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK 0x0000001FL
+#define NBIF_PGSLV_CTRL__NBIF_CFG_PGSLV_EXTCLK_0_IDLE_HYSTERESIS_MASK 0x000003E0L
+//NBIF_PG_MISC_CTRL
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5
+#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT 0xa
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT 0xd
+#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT 0xe
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT 0x10
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18
+#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT 0x1e
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK 0x00000400L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK 0x00002000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK 0x00004000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK 0x00010000L
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK 0x40000000L
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L
+//NBIF_HST_MISC_CTRL
+//SMN_MST_EP_CNTL3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0__SHIFT 0x8
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1__SHIFT 0x9
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2__SHIFT 0xa
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3__SHIFT 0xb
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4__SHIFT 0xc
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5__SHIFT 0xd
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6__SHIFT 0xe
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7__SHIFT 0xf
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF0__SHIFT 0x10
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF1__SHIFT 0x11
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF2__SHIFT 0x12
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF3__SHIFT 0x13
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF4__SHIFT 0x14
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF5__SHIFT 0x15
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF6__SHIFT 0x16
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF7__SHIFT 0x17
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK 0x00000080L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF0_MASK 0x00000100L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF1_MASK 0x00000200L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF2_MASK 0x00000400L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF3_MASK 0x00000800L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF4_MASK 0x00001000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF5_MASK 0x00002000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF6_MASK 0x00004000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV1_PF7_MASK 0x00008000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF0_MASK 0x00010000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF1_MASK 0x00020000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF2_MASK 0x00040000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF3_MASK 0x00080000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF4_MASK 0x00100000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF5_MASK 0x00200000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF6_MASK 0x00400000L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV2_PF7_MASK 0x00800000L
+//SMN_MST_EP_CNTL4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0__SHIFT 0x8
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1__SHIFT 0x9
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2__SHIFT 0xa
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3__SHIFT 0xb
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4__SHIFT 0xc
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5__SHIFT 0xd
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6__SHIFT 0xe
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7__SHIFT 0xf
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF0__SHIFT 0x10
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF1__SHIFT 0x11
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF2__SHIFT 0x12
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF3__SHIFT 0x13
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF4__SHIFT 0x14
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF5__SHIFT 0x15
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF6__SHIFT 0x16
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF7__SHIFT 0x17
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK 0x00000080L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF0_MASK 0x00000100L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF1_MASK 0x00000200L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF2_MASK 0x00000400L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF3_MASK 0x00000800L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF4_MASK 0x00001000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF5_MASK 0x00002000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF6_MASK 0x00004000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV1_PF7_MASK 0x00008000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF0_MASK 0x00010000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF1_MASK 0x00020000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF2_MASK 0x00040000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF3_MASK 0x00080000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF4_MASK 0x00100000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF5_MASK 0x00200000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF6_MASK 0x00400000L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV2_PF7_MASK 0x00800000L
+//SMN_MST_CNTL1
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT 0x0
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT 0x10
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1__SHIFT 0x11
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV2__SHIFT 0x12
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK 0x00000001L
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK 0x00010000L
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV1_MASK 0x00020000L
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV2_MASK 0x00040000L
+//SMN_MST_EP_CNTL5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0__SHIFT 0x8
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1__SHIFT 0x9
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2__SHIFT 0xa
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3__SHIFT 0xb
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4__SHIFT 0xc
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5__SHIFT 0xd
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6__SHIFT 0xe
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7__SHIFT 0xf
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF0__SHIFT 0x10
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF1__SHIFT 0x11
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF2__SHIFT 0x12
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF3__SHIFT 0x13
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF4__SHIFT 0x14
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF5__SHIFT 0x15
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF6__SHIFT 0x16
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF7__SHIFT 0x17
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK 0x00000080L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF0_MASK 0x00000100L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF1_MASK 0x00000200L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF2_MASK 0x00000400L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF3_MASK 0x00000800L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF4_MASK 0x00001000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF5_MASK 0x00002000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF6_MASK 0x00004000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV1_PF7_MASK 0x00008000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF0_MASK 0x00010000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF1_MASK 0x00020000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF2_MASK 0x00040000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF3_MASK 0x00080000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF4_MASK 0x00100000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF5_MASK 0x00200000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF6_MASK 0x00400000L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV2_PF7_MASK 0x00800000L
+//BIF_SELFRING_BUFFER_VID
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0
+#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT 0x8
+#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT 0x10
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK 0x000000FFL
+#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK 0x0000FF00L
+#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK 0x00FF0000L
+//BIF_SELFRING_VECTOR_CNTL
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT 0x1
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK 0x00000001L
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK 0x00000002L
+//NBIF_STRAP_WRITE_CTRL
+#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0
+#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK 0x00000001L
+//NBIF_INTX_DSTATE_MISC_CNTL
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x0
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x1
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x2
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x3
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x4
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT 0x5
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT 0x6
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x7
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK 0x00000001L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK 0x00000002L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK 0x00000004L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK 0x00000008L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK 0x00000010L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK 0x00000020L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK 0x00000040L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK 0x00000080L
+//NBIF_PENDING_MISC_CNTL
+#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT 0x0
+#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT 0x1
+#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK 0x00000001L
+#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK 0x00000002L
+//BIF_GMI_WRR_WEIGHT
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT 0x1d
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT 0x1e
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT 0x1f
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK 0x20000000L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK 0x40000000L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK 0x80000000L
+//BIF_GMI_WRR_WEIGHT2
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT 0x0
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT 0x8
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT 0x10
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT 0x18
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK 0x000000FFL
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK 0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK 0x00FF0000L
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK 0xFF000000L
+//BIF_GMI_WRR_WEIGHT3
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT 0x0
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT 0x8
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT 0x10
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT 0x18
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK 0x000000FFL
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK 0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK 0x00FF0000L
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK 0xFF000000L
+//NBIF_PWRBRK_REQUEST
+#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT 0x0
+#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK 0x00000001L
+//BIF_ATOMIC_ERR_LOG_DEV0_F0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_OPCODE_DEV0_F2_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_LENGTH_DEV0_F2_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__UR_ATOMIC_NR_DEV0_F2_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F2_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F2_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F2_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F2__CLEAR_UR_ATOMIC_NR_DEV0_F2_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_OPCODE_DEV0_F3_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_LENGTH_DEV0_F3_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__UR_ATOMIC_NR_DEV0_F3_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F3_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F3_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F3_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F3__CLEAR_UR_ATOMIC_NR_DEV0_F3_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F4
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_OPCODE_DEV0_F4__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_REQEN_LOW_DEV0_F4__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_LENGTH_DEV0_F4__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_NR_DEV0_F4__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F4__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F4__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_NR_DEV0_F4__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_OPCODE_DEV0_F4_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_REQEN_LOW_DEV0_F4_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_LENGTH_DEV0_F4_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__UR_ATOMIC_NR_DEV0_F4_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F4_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F4_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F4_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F4__CLEAR_UR_ATOMIC_NR_DEV0_F4_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F5
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_OPCODE_DEV0_F5__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_REQEN_LOW_DEV0_F5__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_LENGTH_DEV0_F5__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_NR_DEV0_F5__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F5__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F5__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_NR_DEV0_F5__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_OPCODE_DEV0_F5_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_REQEN_LOW_DEV0_F5_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_LENGTH_DEV0_F5_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__UR_ATOMIC_NR_DEV0_F5_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F5_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F5_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F5_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F5__CLEAR_UR_ATOMIC_NR_DEV0_F5_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F6
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_OPCODE_DEV0_F6__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_REQEN_LOW_DEV0_F6__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_LENGTH_DEV0_F6__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_NR_DEV0_F6__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F6__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F6__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_NR_DEV0_F6__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_OPCODE_DEV0_F6_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_REQEN_LOW_DEV0_F6_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_LENGTH_DEV0_F6_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__UR_ATOMIC_NR_DEV0_F6_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F6_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F6_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F6_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F6__CLEAR_UR_ATOMIC_NR_DEV0_F6_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F7
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_OPCODE_DEV0_F7__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_REQEN_LOW_DEV0_F7__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_LENGTH_DEV0_F7__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_NR_DEV0_F7__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F7__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F7__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F7__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_NR_DEV0_F7__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_OPCODE_DEV0_F7_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_REQEN_LOW_DEV0_F7_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_LENGTH_DEV0_F7_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__UR_ATOMIC_NR_DEV0_F7_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F7_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F7_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F7_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F7__CLEAR_UR_ATOMIC_NR_DEV0_F7_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV1_F0
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_OPCODE_DEV1_F0__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_REQEN_LOW_DEV1_F0__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_LENGTH_DEV1_F0__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_NR_DEV1_F0__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_OPCODE_DEV1_F0__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV1_F0__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_LENGTH_DEV1_F0__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_NR_DEV1_F0__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_OPCODE_DEV1_F0_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_REQEN_LOW_DEV1_F0_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_LENGTH_DEV1_F0_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__UR_ATOMIC_NR_DEV1_F0_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_OPCODE_DEV1_F0_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV1_F0_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_LENGTH_DEV1_F0_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F0__CLEAR_UR_ATOMIC_NR_DEV1_F0_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV1_F1
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_OPCODE_DEV1_F1__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_REQEN_LOW_DEV1_F1__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_LENGTH_DEV1_F1__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_NR_DEV1_F1__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_OPCODE_DEV1_F1__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV1_F1__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_LENGTH_DEV1_F1__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_NR_DEV1_F1__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_OPCODE_DEV1_F1_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_REQEN_LOW_DEV1_F1_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_LENGTH_DEV1_F1_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__UR_ATOMIC_NR_DEV1_F1_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_OPCODE_DEV1_F1_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV1_F1_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_LENGTH_DEV1_F1_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV1_F1__CLEAR_UR_ATOMIC_NR_DEV1_F1_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV2_F0
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_OPCODE_DEV2_F0__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_REQEN_LOW_DEV2_F0__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_LENGTH_DEV2_F0__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_NR_DEV2_F0__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_OPCODE_DEV2_F0__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F0__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_LENGTH_DEV2_F0__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_NR_DEV2_F0__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_OPCODE_DEV2_F0_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_REQEN_LOW_DEV2_F0_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_LENGTH_DEV2_F0_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__UR_ATOMIC_NR_DEV2_F0_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_OPCODE_DEV2_F0_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F0_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_LENGTH_DEV2_F0_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F0__CLEAR_UR_ATOMIC_NR_DEV2_F0_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV2_F1
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_OPCODE_DEV2_F1__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_REQEN_LOW_DEV2_F1__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_LENGTH_DEV2_F1__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_NR_DEV2_F1__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_OPCODE_DEV2_F1__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F1__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_LENGTH_DEV2_F1__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_NR_DEV2_F1__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_OPCODE_DEV2_F1_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_REQEN_LOW_DEV2_F1_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_LENGTH_DEV2_F1_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__UR_ATOMIC_NR_DEV2_F1_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_OPCODE_DEV2_F1_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F1_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_LENGTH_DEV2_F1_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F1__CLEAR_UR_ATOMIC_NR_DEV2_F1_MASK 0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV2_F2
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_OPCODE_DEV2_F2__SHIFT 0x0
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_REQEN_LOW_DEV2_F2__SHIFT 0x1
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_LENGTH_DEV2_F2__SHIFT 0x2
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_NR_DEV2_F2__SHIFT 0x3
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_OPCODE_DEV2_F2__SHIFT 0x10
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F2__SHIFT 0x11
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_LENGTH_DEV2_F2__SHIFT 0x12
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_NR_DEV2_F2__SHIFT 0x13
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_OPCODE_DEV2_F2_MASK 0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_REQEN_LOW_DEV2_F2_MASK 0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_LENGTH_DEV2_F2_MASK 0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__UR_ATOMIC_NR_DEV2_F2_MASK 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_OPCODE_DEV2_F2_MASK 0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV2_F2_MASK 0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_LENGTH_DEV2_F2_MASK 0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV2_F2__CLEAR_UR_ATOMIC_NR_DEV2_F2_MASK 0x00080000L
+//BIF_DMA_MP4_ERR_LOG
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x0
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x1
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT 0x10
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT 0x11
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK 0x00000001L
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00000002L
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK 0x00010000L
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK 0x00020000L
+//BIF_PASID_ERR_LOG
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT 0x0
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT 0x1
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2__SHIFT 0x2
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3__SHIFT 0x3
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F4__SHIFT 0x4
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F5__SHIFT 0x5
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F6__SHIFT 0x6
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F7__SHIFT 0x7
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV1_F0__SHIFT 0x8
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV1_F1__SHIFT 0x9
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV2_F0__SHIFT 0x10
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV2_F1__SHIFT 0x11
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV2_F2__SHIFT 0x12
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK 0x00000001L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK 0x00000002L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F2_MASK 0x00000004L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F3_MASK 0x00000008L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F4_MASK 0x00000010L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F5_MASK 0x00000020L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F6_MASK 0x00000040L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F7_MASK 0x00000080L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV1_F0_MASK 0x00000100L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV1_F1_MASK 0x00000200L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV2_F0_MASK 0x00010000L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV2_F1_MASK 0x00020000L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV2_F2_MASK 0x00040000L
+//BIF_PASID_ERR_CLR
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT 0x0
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT 0x1
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2__SHIFT 0x2
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3__SHIFT 0x3
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F4__SHIFT 0x4
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F5__SHIFT 0x5
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F6__SHIFT 0x6
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F7__SHIFT 0x7
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F0__SHIFT 0x8
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F1__SHIFT 0x9
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F0__SHIFT 0x10
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F1__SHIFT 0x11
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F2__SHIFT 0x12
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK 0x00000001L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK 0x00000002L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F2_MASK 0x00000004L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F3_MASK 0x00000008L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F4_MASK 0x00000010L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F5_MASK 0x00000020L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F6_MASK 0x00000040L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F7_MASK 0x00000080L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F0_MASK 0x00000100L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV1_F1_MASK 0x00000200L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F0_MASK 0x00010000L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F1_MASK 0x00020000L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV2_F2_MASK 0x00040000L
+//OBFF_EMU_CFG
+#define OBFF_EMU_CFG__OBFF_EMU_INTR_EN__SHIFT 0x0
+#define OBFF_EMU_CFG__OBFF_EMU_INTR_EN_MASK 0x00000001L
+//EP0_INTR_URGENT_CAP
+#define EP0_INTR_URGENT_CAP__EP0_F0_INTR_URGENT_MODE__SHIFT 0x0
+#define EP0_INTR_URGENT_CAP__EP0_F1_INTR_URGENT_MODE__SHIFT 0x2
+#define EP0_INTR_URGENT_CAP__EP0_F2_INTR_URGENT_MODE__SHIFT 0x4
+#define EP0_INTR_URGENT_CAP__EP0_F3_INTR_URGENT_MODE__SHIFT 0x6
+#define EP0_INTR_URGENT_CAP__EP0_F4_INTR_URGENT_MODE__SHIFT 0x8
+#define EP0_INTR_URGENT_CAP__EP0_F5_INTR_URGENT_MODE__SHIFT 0xa
+#define EP0_INTR_URGENT_CAP__EP0_F6_INTR_URGENT_MODE__SHIFT 0xc
+#define EP0_INTR_URGENT_CAP__EP0_F7_INTR_URGENT_MODE__SHIFT 0xe
+#define EP0_INTR_URGENT_CAP__EP0_F0_INTR_URGENT_MODE_MASK 0x00000003L
+#define EP0_INTR_URGENT_CAP__EP0_F1_INTR_URGENT_MODE_MASK 0x0000000CL
+#define EP0_INTR_URGENT_CAP__EP0_F2_INTR_URGENT_MODE_MASK 0x00000030L
+#define EP0_INTR_URGENT_CAP__EP0_F3_INTR_URGENT_MODE_MASK 0x000000C0L
+#define EP0_INTR_URGENT_CAP__EP0_F4_INTR_URGENT_MODE_MASK 0x00000300L
+#define EP0_INTR_URGENT_CAP__EP0_F5_INTR_URGENT_MODE_MASK 0x00000C00L
+#define EP0_INTR_URGENT_CAP__EP0_F6_INTR_URGENT_MODE_MASK 0x00003000L
+#define EP0_INTR_URGENT_CAP__EP0_F7_INTR_URGENT_MODE_MASK 0x0000C000L
+//EP1_INTR_URGENT_CAP
+#define EP1_INTR_URGENT_CAP__EP1_F0_INTR_URGENT_MODE__SHIFT 0x0
+#define EP1_INTR_URGENT_CAP__EP1_F1_INTR_URGENT_MODE__SHIFT 0x2
+#define EP1_INTR_URGENT_CAP__EP1_F0_INTR_URGENT_MODE_MASK 0x00000003L
+#define EP1_INTR_URGENT_CAP__EP1_F1_INTR_URGENT_MODE_MASK 0x0000000CL
+//EP2_INTR_URGENT_CAP
+#define EP2_INTR_URGENT_CAP__EP2_F0_INTR_URGENT_MODE__SHIFT 0x0
+#define EP2_INTR_URGENT_CAP__EP2_F1_INTR_URGENT_MODE__SHIFT 0x2
+#define EP2_INTR_URGENT_CAP__EP2_F2_INTR_URGENT_MODE__SHIFT 0x4
+#define EP2_INTR_URGENT_CAP__EP2_F0_INTR_URGENT_MODE_MASK 0x00000003L
+#define EP2_INTR_URGENT_CAP__EP2_F1_INTR_URGENT_MODE_MASK 0x0000000CL
+#define EP2_INTR_URGENT_CAP__EP2_F2_INTR_URGENT_MODE_MASK 0x00000030L
+//EP_PEND_BLOCK_MSK
+#define EP_PEND_BLOCK_MSK__EP0_F0_PEND_BLOCK_MSK__SHIFT 0x0
+#define EP_PEND_BLOCK_MSK__EP0_F1_PEND_BLOCK_MSK__SHIFT 0x1
+#define EP_PEND_BLOCK_MSK__EP0_F2_PEND_BLOCK_MSK__SHIFT 0x2
+#define EP_PEND_BLOCK_MSK__EP0_F3_PEND_BLOCK_MSK__SHIFT 0x3
+#define EP_PEND_BLOCK_MSK__EP0_F4_PEND_BLOCK_MSK__SHIFT 0x4
+#define EP_PEND_BLOCK_MSK__EP0_F5_PEND_BLOCK_MSK__SHIFT 0x5
+#define EP_PEND_BLOCK_MSK__EP0_F6_PEND_BLOCK_MSK__SHIFT 0x6
+#define EP_PEND_BLOCK_MSK__EP0_F7_PEND_BLOCK_MSK__SHIFT 0x7
+#define EP_PEND_BLOCK_MSK__EP1_F0_PEND_BLOCK_MSK__SHIFT 0x8
+#define EP_PEND_BLOCK_MSK__EP1_F1_PEND_BLOCK_MSK__SHIFT 0x9
+#define EP_PEND_BLOCK_MSK__EP2_F0_PEND_BLOCK_MSK__SHIFT 0x10
+#define EP_PEND_BLOCK_MSK__EP2_F1_PEND_BLOCK_MSK__SHIFT 0x11
+#define EP_PEND_BLOCK_MSK__EP2_F2_PEND_BLOCK_MSK__SHIFT 0x12
+#define EP_PEND_BLOCK_MSK__EP0_F0_PEND_BLOCK_MSK_MASK 0x00000001L
+#define EP_PEND_BLOCK_MSK__EP0_F1_PEND_BLOCK_MSK_MASK 0x00000002L
+#define EP_PEND_BLOCK_MSK__EP0_F2_PEND_BLOCK_MSK_MASK 0x00000004L
+#define EP_PEND_BLOCK_MSK__EP0_F3_PEND_BLOCK_MSK_MASK 0x00000008L
+#define EP_PEND_BLOCK_MSK__EP0_F4_PEND_BLOCK_MSK_MASK 0x00000010L
+#define EP_PEND_BLOCK_MSK__EP0_F5_PEND_BLOCK_MSK_MASK 0x00000020L
+#define EP_PEND_BLOCK_MSK__EP0_F6_PEND_BLOCK_MSK_MASK 0x00000040L
+#define EP_PEND_BLOCK_MSK__EP0_F7_PEND_BLOCK_MSK_MASK 0x00000080L
+#define EP_PEND_BLOCK_MSK__EP1_F0_PEND_BLOCK_MSK_MASK 0x00000100L
+#define EP_PEND_BLOCK_MSK__EP1_F1_PEND_BLOCK_MSK_MASK 0x00000200L
+#define EP_PEND_BLOCK_MSK__EP2_F0_PEND_BLOCK_MSK_MASK 0x00010000L
+#define EP_PEND_BLOCK_MSK__EP2_F1_PEND_BLOCK_MSK_MASK 0x00020000L
+#define EP_PEND_BLOCK_MSK__EP2_F2_PEND_BLOCK_MSK_MASK 0x00040000L
+//NBIF_VWIRE_CTRL
+#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT 0x0
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8
+#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT 0x10
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a
+#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK 0x00000001L
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK 0x000000F0L
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK 0x00000100L
+#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK 0x00010000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK 0x00F00000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK 0x0C000000L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET10_DIS__SHIFT 0xa
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET11_DIS__SHIFT 0xb
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET12_DIS__SHIFT 0xc
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET13_DIS__SHIFT 0xd
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET14_DIS__SHIFT 0xe
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET15_DIS__SHIFT 0xf
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET16_DIS__SHIFT 0x10
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET17_DIS__SHIFT 0x11
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET18_DIS__SHIFT 0x12
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET19_DIS__SHIFT 0x13
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET20_DIS__SHIFT 0x14
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET21_DIS__SHIFT 0x15
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET22_DIS__SHIFT 0x16
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET23_DIS__SHIFT 0x17
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET24_DIS__SHIFT 0x18
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET25_DIS__SHIFT 0x19
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET26_DIS__SHIFT 0x1a
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET7_DIS_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET8_DIS_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET9_DIS_MASK 0x00000200L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET10_DIS_MASK 0x00000400L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET11_DIS_MASK 0x00000800L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET12_DIS_MASK 0x00001000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET13_DIS_MASK 0x00002000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET14_DIS_MASK 0x00004000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET15_DIS_MASK 0x00008000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET16_DIS_MASK 0x00010000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET17_DIS_MASK 0x00020000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET18_DIS_MASK 0x00040000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET19_DIS_MASK 0x00080000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET20_DIS_MASK 0x00100000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET21_DIS_MASK 0x00200000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET22_DIS_MASK 0x00400000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET23_DIS_MASK 0x00800000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET24_DIS_MASK 0x01000000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET25_DIS_MASK 0x02000000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET26_DIS_MASK 0x04000000L
+//NBIF_SMN_VWR_VCHG_RST_CTRL0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET10_RST_DEF_REV__SHIFT 0xa
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET11_RST_DEF_REV__SHIFT 0xb
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET12_RST_DEF_REV__SHIFT 0xc
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET13_RST_DEF_REV__SHIFT 0xd
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET14_RST_DEF_REV__SHIFT 0xe
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET15_RST_DEF_REV__SHIFT 0xf
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET16_RST_DEF_REV__SHIFT 0x10
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET17_RST_DEF_REV__SHIFT 0x11
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET18_RST_DEF_REV__SHIFT 0x12
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET19_RST_DEF_REV__SHIFT 0x13
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET20_RST_DEF_REV__SHIFT 0x14
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET21_RST_DEF_REV__SHIFT 0x15
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET22_RST_DEF_REV__SHIFT 0x16
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET23_RST_DEF_REV__SHIFT 0x17
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET24_RST_DEF_REV__SHIFT 0x18
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET25_RST_DEF_REV__SHIFT 0x19
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET26_RST_DEF_REV__SHIFT 0x1a
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET7_RST_DEF_REV_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET8_RST_DEF_REV_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET9_RST_DEF_REV_MASK 0x00000200L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET10_RST_DEF_REV_MASK 0x00000400L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET11_RST_DEF_REV_MASK 0x00000800L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET12_RST_DEF_REV_MASK 0x00001000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET13_RST_DEF_REV_MASK 0x00002000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET14_RST_DEF_REV_MASK 0x00004000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET15_RST_DEF_REV_MASK 0x00008000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET16_RST_DEF_REV_MASK 0x00010000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET17_RST_DEF_REV_MASK 0x00020000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET18_RST_DEF_REV_MASK 0x00040000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET19_RST_DEF_REV_MASK 0x00080000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET20_RST_DEF_REV_MASK 0x00100000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET21_RST_DEF_REV_MASK 0x00200000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET22_RST_DEF_REV_MASK 0x00400000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET23_RST_DEF_REV_MASK 0x00800000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET24_RST_DEF_REV_MASK 0x01000000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET25_RST_DEF_REV_MASK 0x02000000L
+#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET26_RST_DEF_REV_MASK 0x04000000L
+//NBIF_SMN_VWR_VCHG_TRIG
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET10_TRIG__SHIFT 0xa
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET11_TRIG__SHIFT 0xb
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET12_TRIG__SHIFT 0xc
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET13_TRIG__SHIFT 0xd
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET14_TRIG__SHIFT 0xe
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET15_TRIG__SHIFT 0xf
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET16_TRIG__SHIFT 0x10
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET17_TRIG__SHIFT 0x11
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET18_TRIG__SHIFT 0x12
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET19_TRIG__SHIFT 0x13
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET20_TRIG__SHIFT 0x14
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET21_TRIG__SHIFT 0x15
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET22_TRIG__SHIFT 0x16
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET23_TRIG__SHIFT 0x17
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET24_TRIG__SHIFT 0x18
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET25_TRIG__SHIFT 0x19
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET26_TRIG__SHIFT 0x1a
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET7_TRIG_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET8_TRIG_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET9_TRIG_MASK 0x00000200L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET10_TRIG_MASK 0x00000400L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET11_TRIG_MASK 0x00000800L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET12_TRIG_MASK 0x00001000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET13_TRIG_MASK 0x00002000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET14_TRIG_MASK 0x00004000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET15_TRIG_MASK 0x00008000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET16_TRIG_MASK 0x00010000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET17_TRIG_MASK 0x00020000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET18_TRIG_MASK 0x00040000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET19_TRIG_MASK 0x00080000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET20_TRIG_MASK 0x00100000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET21_TRIG_MASK 0x00200000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET22_TRIG_MASK 0x00400000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET23_TRIG_MASK 0x00800000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET24_TRIG_MASK 0x01000000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET25_TRIG_MASK 0x02000000L
+#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET26_TRIG_MASK 0x04000000L
+//NBIF_SMN_VWR_WTRIG_CNTL
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS__SHIFT 0x7
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS__SHIFT 0x8
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS__SHIFT 0x9
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET10_DIS__SHIFT 0xa
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET11_DIS__SHIFT 0xb
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET12_DIS__SHIFT 0xc
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET13_DIS__SHIFT 0xd
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET14_DIS__SHIFT 0xe
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET15_DIS__SHIFT 0xf
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET16_DIS__SHIFT 0x10
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET17_DIS__SHIFT 0x11
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET18_DIS__SHIFT 0x12
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET19_DIS__SHIFT 0x13
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET20_DIS__SHIFT 0x14
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET21_DIS__SHIFT 0x15
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET22_DIS__SHIFT 0x16
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET23_DIS__SHIFT 0x17
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET24_DIS__SHIFT 0x18
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET25_DIS__SHIFT 0x19
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET26_DIS__SHIFT 0x1a
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK 0x00000001L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK 0x00000002L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK 0x00000004L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS_MASK 0x00000008L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS_MASK 0x00000010L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS_MASK 0x00000020L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS_MASK 0x00000040L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET7_DIS_MASK 0x00000080L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET8_DIS_MASK 0x00000100L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET9_DIS_MASK 0x00000200L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET10_DIS_MASK 0x00000400L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET11_DIS_MASK 0x00000800L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET12_DIS_MASK 0x00001000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET13_DIS_MASK 0x00002000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET14_DIS_MASK 0x00004000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET15_DIS_MASK 0x00008000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET16_DIS_MASK 0x00010000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET17_DIS_MASK 0x00020000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET18_DIS_MASK 0x00040000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET19_DIS_MASK 0x00080000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET20_DIS_MASK 0x00100000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET21_DIS_MASK 0x00200000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET22_DIS_MASK 0x00400000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET23_DIS_MASK 0x00800000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET24_DIS_MASK 0x01000000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET25_DIS_MASK 0x02000000L
+#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET26_DIS_MASK 0x04000000L
+//NBIF_SMN_VWR_VCHG_DIS_CTRL_1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV__SHIFT 0x7
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV__SHIFT 0x8
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV__SHIFT 0x9
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET10_DIFFDET_DEF_REV__SHIFT 0xa
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET11_DIFFDET_DEF_REV__SHIFT 0xb
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET12_DIFFDET_DEF_REV__SHIFT 0xc
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET13_DIFFDET_DEF_REV__SHIFT 0xd
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET14_DIFFDET_DEF_REV__SHIFT 0xe
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET15_DIFFDET_DEF_REV__SHIFT 0xf
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET16_DIFFDET_DEF_REV__SHIFT 0x10
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET17_DIFFDET_DEF_REV__SHIFT 0x11
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET18_DIFFDET_DEF_REV__SHIFT 0x12
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET19_DIFFDET_DEF_REV__SHIFT 0x13
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET20_DIFFDET_DEF_REV__SHIFT 0x14
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET21_DIFFDET_DEF_REV__SHIFT 0x15
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET22_DIFFDET_DEF_REV__SHIFT 0x16
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET23_DIFFDET_DEF_REV__SHIFT 0x17
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET24_DIFFDET_DEF_REV__SHIFT 0x18
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET25_DIFFDET_DEF_REV__SHIFT 0x19
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET26_DIFFDET_DEF_REV__SHIFT 0x1a
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK 0x00000001L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK 0x00000002L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK 0x00000004L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV_MASK 0x00000008L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV_MASK 0x00000010L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV_MASK 0x00000020L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV_MASK 0x00000040L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET7_DIFFDET_DEF_REV_MASK 0x00000080L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET8_DIFFDET_DEF_REV_MASK 0x00000100L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET9_DIFFDET_DEF_REV_MASK 0x00000200L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET10_DIFFDET_DEF_REV_MASK 0x00000400L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET11_DIFFDET_DEF_REV_MASK 0x00000800L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET12_DIFFDET_DEF_REV_MASK 0x00001000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET13_DIFFDET_DEF_REV_MASK 0x00002000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET14_DIFFDET_DEF_REV_MASK 0x00004000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET15_DIFFDET_DEF_REV_MASK 0x00008000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET16_DIFFDET_DEF_REV_MASK 0x00010000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET17_DIFFDET_DEF_REV_MASK 0x00020000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET18_DIFFDET_DEF_REV_MASK 0x00040000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET19_DIFFDET_DEF_REV_MASK 0x00080000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET20_DIFFDET_DEF_REV_MASK 0x00100000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET21_DIFFDET_DEF_REV_MASK 0x00200000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET22_DIFFDET_DEF_REV_MASK 0x00400000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET23_DIFFDET_DEF_REV_MASK 0x00800000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET24_DIFFDET_DEF_REV_MASK 0x01000000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET25_DIFFDET_DEF_REV_MASK 0x02000000L
+#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET26_DIFFDET_DEF_REV_MASK 0x04000000L
+//NBIF_MGCG_CTRL_LCLK
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT 0x0
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT 0x1
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT 0x2
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT 0xa
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT 0xb
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT 0xc
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT 0xd
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK 0x00000001L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK 0x00000002L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK 0x000003FCL
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK 0x00000400L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK 0x00000800L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK 0x00002000L
+//NBIF_DS_CTRL_LCLK
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK 0x00000001L
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK 0xFFFF0000L
+//SMN_MST_CNTL0
+#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1__SHIFT 0x11
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV2__SHIFT 0x12
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1__SHIFT 0x15
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV2__SHIFT 0x16
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1__SHIFT 0x19
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV2__SHIFT 0x1a
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1__SHIFT 0x1d
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV2__SHIFT 0x1e
+#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK 0x00000003L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK 0x00000100L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK 0x00000200L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK 0x00000400L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK 0x00000800L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK 0x00010000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV1_MASK 0x00020000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV2_MASK 0x00040000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK 0x00100000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV1_MASK 0x00200000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV2_MASK 0x00400000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK 0x01000000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV1_MASK 0x02000000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV2_MASK 0x04000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK 0x10000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV1_MASK 0x20000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV2_MASK 0x40000000L
+//SMN_MST_EP_CNTL1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0__SHIFT 0x8
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1__SHIFT 0x9
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2__SHIFT 0xa
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3__SHIFT 0xb
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4__SHIFT 0xc
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5__SHIFT 0xd
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6__SHIFT 0xe
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7__SHIFT 0xf
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF0__SHIFT 0x10
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF1__SHIFT 0x11
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF2__SHIFT 0x12
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF3__SHIFT 0x13
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF4__SHIFT 0x14
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF5__SHIFT 0x15
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF6__SHIFT 0x16
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF7__SHIFT 0x17
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK 0x00000080L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF0_MASK 0x00000100L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF1_MASK 0x00000200L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF2_MASK 0x00000400L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF3_MASK 0x00000800L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF4_MASK 0x00001000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF5_MASK 0x00002000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF6_MASK 0x00004000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV1_PF7_MASK 0x00008000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF0_MASK 0x00010000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF1_MASK 0x00020000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF2_MASK 0x00040000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF3_MASK 0x00080000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF4_MASK 0x00100000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF5_MASK 0x00200000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF6_MASK 0x00400000L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV2_PF7_MASK 0x00800000L
+//SMN_MST_EP_CNTL2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0__SHIFT 0x8
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1__SHIFT 0x9
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2__SHIFT 0xa
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3__SHIFT 0xb
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4__SHIFT 0xc
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5__SHIFT 0xd
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6__SHIFT 0xe
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7__SHIFT 0xf
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF0__SHIFT 0x10
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF1__SHIFT 0x11
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF2__SHIFT 0x12
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF3__SHIFT 0x13
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF4__SHIFT 0x14
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF5__SHIFT 0x15
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF6__SHIFT 0x16
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF7__SHIFT 0x17
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK 0x00000001L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK 0x00000002L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK 0x00000004L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK 0x00000008L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK 0x00000010L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK 0x00000020L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK 0x00000040L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK 0x00000080L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF0_MASK 0x00000100L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF1_MASK 0x00000200L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF2_MASK 0x00000400L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF3_MASK 0x00000800L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF4_MASK 0x00001000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF5_MASK 0x00002000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF6_MASK 0x00004000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV1_PF7_MASK 0x00008000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF0_MASK 0x00010000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF1_MASK 0x00020000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF2_MASK 0x00040000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF3_MASK 0x00080000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF4_MASK 0x00100000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF5_MASK 0x00200000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF6_MASK 0x00400000L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV2_PF7_MASK 0x00800000L
+//NBIF_SDP_VWR_VCHG_DIS_CTRL
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK 0x01000000L
+//NBIF_SDP_VWR_VCHG_TRIG
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK 0x00000001L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK 0x00000002L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK 0x00000004L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK 0x00000008L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK 0x00000010L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK 0x00000020L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK 0x00000040L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK 0x00000080L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK 0x01000000L
+//NBIF_SHUB_TODET_CTRL
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT 0x0
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT 0x1
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT 0x8
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT 0x10
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK 0x00000001L
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK 0x00000002L
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK 0x00000700L
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK 0xFFFF0000L
+//NBIF_SHUB_TODET_CLIENT_CTRL
+#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT 0x0
+#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK 0xFFFFFFFFL
+//NBIF_SHUB_TODET_CLIENT_STATUS
+#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT 0x0
+#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK 0xFFFFFFFFL
+//NBIF_SHUB_TODET_SYNCFLOOD_CTRL
+#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT 0x0
+#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK 0xFFFFFFFFL
+//BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L
+//BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L
+//BIFC_GMI_SDP_REQ_POOLCRED_ALLOC
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L
+//BIFC_GMI_SDP_DAT_POOLCRED_ALLOC
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L
+//BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L
+//BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT 0x0
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT 0x4
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT 0x8
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT 0xc
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT 0x10
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT 0x14
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT 0x18
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT 0x1c
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK 0x0000000FL
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK 0x000000F0L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK 0x00000F00L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK 0x0000F000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK 0x000F0000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK 0x00F00000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK 0x0F000000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK 0xF0000000L
+//DISCON_HYSTERESIS_HEAD_CTRL
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x0
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT 0x8
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK 0x0000000FL
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK 0x00000F00L
+//BIFC_PCIE_BDF_CNTL0
+#define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL0__SHIFT 0x0
+#define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL1__SHIFT 0x10
+#define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL0_MASK 0x0000FFFFL
+#define BIFC_PCIE_BDF_CNTL0__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL1_MASK 0xFFFF0000L
+//BIFC_PCIE_BDF_CNTL1
+#define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL2__SHIFT 0x0
+#define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL3__SHIFT 0x10
+#define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL2_MASK 0x0000FFFFL
+#define BIFC_PCIE_BDF_CNTL1__DMA_NON_PCIEFUNC_BUSDEVFUNC_CL3_MASK 0xFFFF0000L
+//BIFC_EARLY_WAKEUP_CNTL
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk
+//HARD_RST_CTRL
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3
+#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5
+#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7
+#define HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x9
+#define HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT 0xa
+#define HARD_RST_CTRL__STRAP_RST_EN__SHIFT 0x17
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d
+#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e
+#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK 0x00000001L
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK 0x00000002L
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK 0x00000004L
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK 0x00000008L
+#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK 0x00000010L
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK 0x00000020L
+#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK 0x00000040L
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK 0x00000080L
+#define HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK 0x00000200L
+#define HARD_RST_CTRL__SION_AON_RESET_EN_MASK 0x00000400L
+#define HARD_RST_CTRL__STRAP_RST_EN_MASK 0x00800000L
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK 0x10000000L
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK 0x20000000L
+#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK 0x40000000L
+#define HARD_RST_CTRL__CORE_RST_EN_MASK 0x80000000L
+//SELF_SOFT_RST
+#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1
+#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3
+#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5
+#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7
+#define SELF_SOFT_RST__DSPT1_CFG_RST__SHIFT 0x8
+#define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST__SHIFT 0x9
+#define SELF_SOFT_RST__DSPT1_PRV_RST__SHIFT 0xa
+#define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST__SHIFT 0xb
+#define SELF_SOFT_RST__EP1_CFG_RST__SHIFT 0xc
+#define SELF_SOFT_RST__EP1_CFG_STICKY_RST__SHIFT 0xd
+#define SELF_SOFT_RST__EP1_PRV_RST__SHIFT 0xe
+#define SELF_SOFT_RST__EP1_PRV_STICKY_RST__SHIFT 0xf
+#define SELF_SOFT_RST__DSPT2_CFG_RST__SHIFT 0x10
+#define SELF_SOFT_RST__DSPT2_CFG_STICKY_RST__SHIFT 0x11
+#define SELF_SOFT_RST__DSPT2_PRV_RST__SHIFT 0x12
+#define SELF_SOFT_RST__DSPT2_PRV_STICKY_RST__SHIFT 0x13
+#define SELF_SOFT_RST__EP2_CFG_RST__SHIFT 0x14
+#define SELF_SOFT_RST__EP2_CFG_STICKY_RST__SHIFT 0x15
+#define SELF_SOFT_RST__EP2_PRV_RST__SHIFT 0x16
+#define SELF_SOFT_RST__EP2_PRV_STICKY_RST__SHIFT 0x17
+#define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT 0x18
+#define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT 0x19
+#define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT 0x1a
+#define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT 0x1b
+#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c
+#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d
+#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e
+#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f
+#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK 0x00000001L
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK 0x00000002L
+#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK 0x00000004L
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK 0x00000008L
+#define SELF_SOFT_RST__EP0_CFG_RST_MASK 0x00000010L
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK 0x00000020L
+#define SELF_SOFT_RST__EP0_PRV_RST_MASK 0x00000040L
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK 0x00000080L
+#define SELF_SOFT_RST__DSPT1_CFG_RST_MASK 0x00000100L
+#define SELF_SOFT_RST__DSPT1_CFG_STICKY_RST_MASK 0x00000200L
+#define SELF_SOFT_RST__DSPT1_PRV_RST_MASK 0x00000400L
+#define SELF_SOFT_RST__DSPT1_PRV_STICKY_RST_MASK 0x00000800L
+#define SELF_SOFT_RST__EP1_CFG_RST_MASK 0x00001000L
+#define SELF_SOFT_RST__EP1_CFG_STICKY_RST_MASK 0x00002000L
+#define SELF_SOFT_RST__EP1_PRV_RST_MASK 0x00004000L
+#define SELF_SOFT_RST__EP1_PRV_STICKY_RST_MASK 0x00008000L
+#define SELF_SOFT_RST__DSPT2_CFG_RST_MASK 0x00010000L
+#define SELF_SOFT_RST__DSPT2_CFG_STICKY_RST_MASK 0x00020000L
+#define SELF_SOFT_RST__DSPT2_PRV_RST_MASK 0x00040000L
+#define SELF_SOFT_RST__DSPT2_PRV_STICKY_RST_MASK 0x00080000L
+#define SELF_SOFT_RST__EP2_CFG_RST_MASK 0x00100000L
+#define SELF_SOFT_RST__EP2_CFG_STICKY_RST_MASK 0x00200000L
+#define SELF_SOFT_RST__EP2_PRV_RST_MASK 0x00400000L
+#define SELF_SOFT_RST__EP2_PRV_STICKY_RST_MASK 0x00800000L
+#define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK 0x01000000L
+#define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK 0x02000000L
+#define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK 0x04000000L
+#define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK 0x08000000L
+#define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK 0x10000000L
+#define SELF_SOFT_RST__CORE_STICKY_RST_MASK 0x20000000L
+#define SELF_SOFT_RST__RELOAD_STRAP_MASK 0x40000000L
+#define SELF_SOFT_RST__CORE_RST_MASK 0x80000000L
+//BIF_GFX_DRV_VPU_RST
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT 0x0
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT 0x3
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT 0x5
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT 0x7
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK 0x00000001L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK 0x00000002L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK 0x00000004L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK 0x00000008L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK 0x00000010L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK 0x00000020L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK 0x00000040L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK 0x00000080L
+//BIF_RST_MISC_CTRL
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK 0x00000001L
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK 0x0000000CL
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK 0x00000010L
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK 0x00000020L
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK 0x00000040L
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK 0x00000100L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK 0x00000200L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK 0x00001C00L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK 0x00006000L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK 0x00018000L
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK 0x000E0000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK 0x00800000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK 0x03000000L
+//BIF_RST_MISC_CTRL2
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12
+#define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE__SHIFT 0x13
+#define BIF_RST_MISC_CTRL2__ENDP2_LNK_RST_TRANS_IDLE__SHIFT 0x14
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK 0x00010000L
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK 0x00020000L
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK 0x00040000L
+#define BIF_RST_MISC_CTRL2__ENDP1_LNK_RST_TRANS_IDLE_MASK 0x00080000L
+#define BIF_RST_MISC_CTRL2__ENDP2_LNK_RST_TRANS_IDLE_MASK 0x00100000L
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK 0x80000000L
+//BIF_RST_MISC_CTRL3
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK 0x0000000FL
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK 0x00000030L
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK 0x00000040L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK 0x00000380L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK 0x00001C00L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK 0x0000E000L
+//DEV0_PF0_FLR_RST_CTRL
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT 0x1f
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK 0x00000020L
+#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK 0x00000040L
+#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK 0x00000080L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK 0x00000100L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK 0x00000200L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK 0x00000400L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK 0x00000800L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK 0x00001000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK 0x00002000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK 0x00004000L
+#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK 0x00008000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK 0x00010000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK 0x80000000L
+//DEV0_PF1_FLR_RST_CTRL
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF2_FLR_RST_CTRL
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF3_FLR_RST_CTRL
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF4_FLR_RST_CTRL
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF5_FLR_RST_CTRL
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF6_FLR_RST_CTRL
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV0_PF7_FLR_RST_CTRL
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//BIF_INST_RESET_INTR_STS
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4
+#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS__SHIFT 0x8
+#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x9
+#define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_INTR_STS__SHIFT 0xa
+#define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0xb
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK 0x00000001L
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000002L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK 0x00000004L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK 0x00000008L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK 0x00000010L
+#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_INTR_STS_MASK 0x00000100L
+#define BIF_INST_RESET_INTR_STS__EP1_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000200L
+#define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_INTR_STS_MASK 0x00000400L
+#define BIF_INST_RESET_INTR_STS__EP2_LINK_RESET_CFG_ONLY_INTR_STS_MASK 0x00000800L
+//BIF_PF_FLR_INTR_STS
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6
+#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7
+#define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS__SHIFT 0x8
+#define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS__SHIFT 0x9
+#define BIF_PF_FLR_INTR_STS__DEV1_PF2_FLR_INTR_STS__SHIFT 0xa
+#define BIF_PF_FLR_INTR_STS__DEV1_PF3_FLR_INTR_STS__SHIFT 0xb
+#define BIF_PF_FLR_INTR_STS__DEV1_PF4_FLR_INTR_STS__SHIFT 0xc
+#define BIF_PF_FLR_INTR_STS__DEV1_PF5_FLR_INTR_STS__SHIFT 0xd
+#define BIF_PF_FLR_INTR_STS__DEV1_PF6_FLR_INTR_STS__SHIFT 0xe
+#define BIF_PF_FLR_INTR_STS__DEV1_PF7_FLR_INTR_STS__SHIFT 0xf
+#define BIF_PF_FLR_INTR_STS__DEV2_PF0_FLR_INTR_STS__SHIFT 0x10
+#define BIF_PF_FLR_INTR_STS__DEV2_PF1_FLR_INTR_STS__SHIFT 0x11
+#define BIF_PF_FLR_INTR_STS__DEV2_PF2_FLR_INTR_STS__SHIFT 0x12
+#define BIF_PF_FLR_INTR_STS__DEV2_PF3_FLR_INTR_STS__SHIFT 0x13
+#define BIF_PF_FLR_INTR_STS__DEV2_PF4_FLR_INTR_STS__SHIFT 0x14
+#define BIF_PF_FLR_INTR_STS__DEV2_PF5_FLR_INTR_STS__SHIFT 0x15
+#define BIF_PF_FLR_INTR_STS__DEV2_PF6_FLR_INTR_STS__SHIFT 0x16
+#define BIF_PF_FLR_INTR_STS__DEV2_PF7_FLR_INTR_STS__SHIFT 0x17
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK 0x00000001L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK 0x00000002L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK 0x00000004L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK 0x00000008L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK 0x00000010L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK 0x00000020L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK 0x00000040L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK 0x00000080L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF0_FLR_INTR_STS_MASK 0x00000100L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF1_FLR_INTR_STS_MASK 0x00000200L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF2_FLR_INTR_STS_MASK 0x00000400L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF3_FLR_INTR_STS_MASK 0x00000800L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF4_FLR_INTR_STS_MASK 0x00001000L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF5_FLR_INTR_STS_MASK 0x00002000L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF6_FLR_INTR_STS_MASK 0x00004000L
+#define BIF_PF_FLR_INTR_STS__DEV1_PF7_FLR_INTR_STS_MASK 0x00008000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF0_FLR_INTR_STS_MASK 0x00010000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF1_FLR_INTR_STS_MASK 0x00020000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF2_FLR_INTR_STS_MASK 0x00040000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF3_FLR_INTR_STS_MASK 0x00080000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF4_FLR_INTR_STS_MASK 0x00100000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF5_FLR_INTR_STS_MASK 0x00200000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF6_FLR_INTR_STS_MASK 0x00400000L
+#define BIF_PF_FLR_INTR_STS__DEV2_PF7_FLR_INTR_STS_MASK 0x00800000L
+//BIF_D3HOTD0_INTR_STS
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS__SHIFT 0x8
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS__SHIFT 0x9
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF2_D3HOTD0_INTR_STS__SHIFT 0xa
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF3_D3HOTD0_INTR_STS__SHIFT 0xb
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF4_D3HOTD0_INTR_STS__SHIFT 0xc
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF5_D3HOTD0_INTR_STS__SHIFT 0xd
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF6_D3HOTD0_INTR_STS__SHIFT 0xe
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF7_D3HOTD0_INTR_STS__SHIFT 0xf
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF0_D3HOTD0_INTR_STS__SHIFT 0x10
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF1_D3HOTD0_INTR_STS__SHIFT 0x11
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF2_D3HOTD0_INTR_STS__SHIFT 0x12
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF3_D3HOTD0_INTR_STS__SHIFT 0x13
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF4_D3HOTD0_INTR_STS__SHIFT 0x14
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF5_D3HOTD0_INTR_STS__SHIFT 0x15
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF6_D3HOTD0_INTR_STS__SHIFT 0x16
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF7_D3HOTD0_INTR_STS__SHIFT 0x17
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK 0x00000001L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK 0x00000002L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK 0x00000004L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK 0x00000008L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK 0x00000010L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK 0x00000020L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK 0x00000040L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK 0x00000080L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF0_D3HOTD0_INTR_STS_MASK 0x00000100L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF1_D3HOTD0_INTR_STS_MASK 0x00000200L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF2_D3HOTD0_INTR_STS_MASK 0x00000400L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF3_D3HOTD0_INTR_STS_MASK 0x00000800L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF4_D3HOTD0_INTR_STS_MASK 0x00001000L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF5_D3HOTD0_INTR_STS_MASK 0x00002000L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF6_D3HOTD0_INTR_STS_MASK 0x00004000L
+#define BIF_D3HOTD0_INTR_STS__DEV1_PF7_D3HOTD0_INTR_STS_MASK 0x00008000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF0_D3HOTD0_INTR_STS_MASK 0x00010000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF1_D3HOTD0_INTR_STS_MASK 0x00020000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF2_D3HOTD0_INTR_STS_MASK 0x00040000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF3_D3HOTD0_INTR_STS_MASK 0x00080000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF4_D3HOTD0_INTR_STS_MASK 0x00100000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF5_D3HOTD0_INTR_STS_MASK 0x00200000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF6_D3HOTD0_INTR_STS_MASK 0x00400000L
+#define BIF_D3HOTD0_INTR_STS__DEV2_PF7_D3HOTD0_INTR_STS_MASK 0x00800000L
+//BIF_POWER_INTR_STS
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0
+#define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS__SHIFT 0x1
+#define BIF_POWER_INTR_STS__DEV2_PME_TURN_OFF_INTR_STS__SHIFT 0x2
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10
+#define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS__SHIFT 0x11
+#define BIF_POWER_INTR_STS__PORT2_DSTATE_INTR_STS__SHIFT 0x12
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK 0x00000001L
+#define BIF_POWER_INTR_STS__DEV1_PME_TURN_OFF_INTR_STS_MASK 0x00000002L
+#define BIF_POWER_INTR_STS__DEV2_PME_TURN_OFF_INTR_STS_MASK 0x00000004L
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK 0x00010000L
+#define BIF_POWER_INTR_STS__PORT1_DSTATE_INTR_STS_MASK 0x00020000L
+#define BIF_POWER_INTR_STS__PORT2_DSTATE_INTR_STS_MASK 0x00040000L
+//BIF_PF_DSTATE_INTR_STS
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS__SHIFT 0x8
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS__SHIFT 0x9
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS__SHIFT 0xa
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS__SHIFT 0xb
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS__SHIFT 0xc
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS__SHIFT 0xd
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS__SHIFT 0xe
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS__SHIFT 0xf
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF0_DSTATE_INTR_STS__SHIFT 0x10
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF1_DSTATE_INTR_STS__SHIFT 0x11
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF2_DSTATE_INTR_STS__SHIFT 0x12
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF3_DSTATE_INTR_STS__SHIFT 0x13
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF4_DSTATE_INTR_STS__SHIFT 0x14
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF5_DSTATE_INTR_STS__SHIFT 0x15
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF6_DSTATE_INTR_STS__SHIFT 0x16
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF7_DSTATE_INTR_STS__SHIFT 0x17
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK 0x00000001L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK 0x00000002L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK 0x00000004L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK 0x00000008L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK 0x00000010L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK 0x00000020L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK 0x00000040L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK 0x00000080L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF0_DSTATE_INTR_STS_MASK 0x00000100L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF1_DSTATE_INTR_STS_MASK 0x00000200L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF2_DSTATE_INTR_STS_MASK 0x00000400L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF3_DSTATE_INTR_STS_MASK 0x00000800L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF4_DSTATE_INTR_STS_MASK 0x00001000L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF5_DSTATE_INTR_STS_MASK 0x00002000L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF6_DSTATE_INTR_STS_MASK 0x00004000L
+#define BIF_PF_DSTATE_INTR_STS__DEV1_PF7_DSTATE_INTR_STS_MASK 0x00008000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF0_DSTATE_INTR_STS_MASK 0x00010000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF1_DSTATE_INTR_STS_MASK 0x00020000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF2_DSTATE_INTR_STS_MASK 0x00040000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF3_DSTATE_INTR_STS_MASK 0x00080000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF4_DSTATE_INTR_STS_MASK 0x00100000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF5_DSTATE_INTR_STS_MASK 0x00200000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF6_DSTATE_INTR_STS_MASK 0x00400000L
+#define BIF_PF_DSTATE_INTR_STS__DEV2_PF7_DSTATE_INTR_STS_MASK 0x00800000L
+//SELF_SOFT_RST_2
+#define SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT 0x0
+#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT 0x1
+#define SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT 0x2
+#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT 0x3
+#define SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT 0x4
+#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT 0x5
+#define SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT 0x6
+#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT 0x7
+#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT 0x18
+#define SELF_SOFT_RST_2__STRAP_RST__SHIFT 0x19
+#define SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK 0x00000001L
+#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK 0x00000002L
+#define SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK 0x00000004L
+#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK 0x00000008L
+#define SELF_SOFT_RST_2__EP3_CFG_RST_MASK 0x00000010L
+#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK 0x00000020L
+#define SELF_SOFT_RST_2__EP3_PRV_RST_MASK 0x00000040L
+#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK 0x00000080L
+#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK 0x01000000L
+#define SELF_SOFT_RST_2__STRAP_RST_MASK 0x02000000L
+//BIF_INST_RESET_INTR_MASK
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4
+#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK__SHIFT 0x8
+#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x9
+#define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_INTR_MASK__SHIFT 0xa
+#define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0xb
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK 0x00000001L
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000002L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK 0x00000004L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK 0x00000008L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK 0x00000010L
+#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_INTR_MASK_MASK 0x00000100L
+#define BIF_INST_RESET_INTR_MASK__EP1_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000200L
+#define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_INTR_MASK_MASK 0x00000400L
+#define BIF_INST_RESET_INTR_MASK__EP2_LINK_RESET_CFG_ONLY_INTR_MASK_MASK 0x00000800L
+//BIF_PF_FLR_INTR_MASK
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK__SHIFT 0x8
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK__SHIFT 0x9
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF2_FLR_INTR_MASK__SHIFT 0xa
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF3_FLR_INTR_MASK__SHIFT 0xb
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF4_FLR_INTR_MASK__SHIFT 0xc
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF5_FLR_INTR_MASK__SHIFT 0xd
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF6_FLR_INTR_MASK__SHIFT 0xe
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF7_FLR_INTR_MASK__SHIFT 0xf
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF0_FLR_INTR_MASK__SHIFT 0x10
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF1_FLR_INTR_MASK__SHIFT 0x11
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF2_FLR_INTR_MASK__SHIFT 0x12
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF3_FLR_INTR_MASK__SHIFT 0x13
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF4_FLR_INTR_MASK__SHIFT 0x14
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF5_FLR_INTR_MASK__SHIFT 0x15
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF6_FLR_INTR_MASK__SHIFT 0x16
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF7_FLR_INTR_MASK__SHIFT 0x17
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK 0x00000001L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK 0x00000002L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK 0x00000004L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK 0x00000008L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK 0x00000010L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK 0x00000020L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK 0x00000040L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK 0x00000080L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF0_FLR_INTR_MASK_MASK 0x00000100L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF1_FLR_INTR_MASK_MASK 0x00000200L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF2_FLR_INTR_MASK_MASK 0x00000400L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF3_FLR_INTR_MASK_MASK 0x00000800L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF4_FLR_INTR_MASK_MASK 0x00001000L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF5_FLR_INTR_MASK_MASK 0x00002000L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF6_FLR_INTR_MASK_MASK 0x00004000L
+#define BIF_PF_FLR_INTR_MASK__DEV1_PF7_FLR_INTR_MASK_MASK 0x00008000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF0_FLR_INTR_MASK_MASK 0x00010000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF1_FLR_INTR_MASK_MASK 0x00020000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF2_FLR_INTR_MASK_MASK 0x00040000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF3_FLR_INTR_MASK_MASK 0x00080000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF4_FLR_INTR_MASK_MASK 0x00100000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF5_FLR_INTR_MASK_MASK 0x00200000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF6_FLR_INTR_MASK_MASK 0x00400000L
+#define BIF_PF_FLR_INTR_MASK__DEV2_PF7_FLR_INTR_MASK_MASK 0x00800000L
+//BIF_D3HOTD0_INTR_MASK
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK__SHIFT 0x8
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK__SHIFT 0x9
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF2_D3HOTD0_INTR_MASK__SHIFT 0xa
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF3_D3HOTD0_INTR_MASK__SHIFT 0xb
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF4_D3HOTD0_INTR_MASK__SHIFT 0xc
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF5_D3HOTD0_INTR_MASK__SHIFT 0xd
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF6_D3HOTD0_INTR_MASK__SHIFT 0xe
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF7_D3HOTD0_INTR_MASK__SHIFT 0xf
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF0_D3HOTD0_INTR_MASK__SHIFT 0x10
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF1_D3HOTD0_INTR_MASK__SHIFT 0x11
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF2_D3HOTD0_INTR_MASK__SHIFT 0x12
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF3_D3HOTD0_INTR_MASK__SHIFT 0x13
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF4_D3HOTD0_INTR_MASK__SHIFT 0x14
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF5_D3HOTD0_INTR_MASK__SHIFT 0x15
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF6_D3HOTD0_INTR_MASK__SHIFT 0x16
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF7_D3HOTD0_INTR_MASK__SHIFT 0x17
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK 0x00000001L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK 0x00000002L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK 0x00000004L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK 0x00000008L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK 0x00000010L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK 0x00000020L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK 0x00000040L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK 0x00000080L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF0_D3HOTD0_INTR_MASK_MASK 0x00000100L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF1_D3HOTD0_INTR_MASK_MASK 0x00000200L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF2_D3HOTD0_INTR_MASK_MASK 0x00000400L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF3_D3HOTD0_INTR_MASK_MASK 0x00000800L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF4_D3HOTD0_INTR_MASK_MASK 0x00001000L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF5_D3HOTD0_INTR_MASK_MASK 0x00002000L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF6_D3HOTD0_INTR_MASK_MASK 0x00004000L
+#define BIF_D3HOTD0_INTR_MASK__DEV1_PF7_D3HOTD0_INTR_MASK_MASK 0x00008000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF0_D3HOTD0_INTR_MASK_MASK 0x00010000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF1_D3HOTD0_INTR_MASK_MASK 0x00020000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF2_D3HOTD0_INTR_MASK_MASK 0x00040000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF3_D3HOTD0_INTR_MASK_MASK 0x00080000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF4_D3HOTD0_INTR_MASK_MASK 0x00100000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF5_D3HOTD0_INTR_MASK_MASK 0x00200000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF6_D3HOTD0_INTR_MASK_MASK 0x00400000L
+#define BIF_D3HOTD0_INTR_MASK__DEV2_PF7_D3HOTD0_INTR_MASK_MASK 0x00800000L
+//BIF_POWER_INTR_MASK
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0
+#define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK__SHIFT 0x1
+#define BIF_POWER_INTR_MASK__DEV2_PME_TURN_OFF_INTR_MASK__SHIFT 0x2
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10
+#define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK__SHIFT 0x11
+#define BIF_POWER_INTR_MASK__PORT2_DSTATE_INTR_MASK__SHIFT 0x12
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK 0x00000001L
+#define BIF_POWER_INTR_MASK__DEV1_PME_TURN_OFF_INTR_MASK_MASK 0x00000002L
+#define BIF_POWER_INTR_MASK__DEV2_PME_TURN_OFF_INTR_MASK_MASK 0x00000004L
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK 0x00010000L
+#define BIF_POWER_INTR_MASK__PORT1_DSTATE_INTR_MASK_MASK 0x00020000L
+#define BIF_POWER_INTR_MASK__PORT2_DSTATE_INTR_MASK_MASK 0x00040000L
+//BIF_PF_DSTATE_INTR_MASK
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK__SHIFT 0x8
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK__SHIFT 0x9
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK__SHIFT 0xa
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK__SHIFT 0xb
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK__SHIFT 0xc
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK__SHIFT 0xd
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK__SHIFT 0xe
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK__SHIFT 0xf
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF0_DSTATE_INTR_MASK__SHIFT 0x10
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF1_DSTATE_INTR_MASK__SHIFT 0x11
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF2_DSTATE_INTR_MASK__SHIFT 0x12
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF3_DSTATE_INTR_MASK__SHIFT 0x13
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF4_DSTATE_INTR_MASK__SHIFT 0x14
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF5_DSTATE_INTR_MASK__SHIFT 0x15
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF6_DSTATE_INTR_MASK__SHIFT 0x16
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF7_DSTATE_INTR_MASK__SHIFT 0x17
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK 0x00000001L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK 0x00000002L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK 0x00000004L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK 0x00000008L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK 0x00000010L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK 0x00000020L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK 0x00000040L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK 0x00000080L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF0_DSTATE_INTR_MASK_MASK 0x00000100L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF1_DSTATE_INTR_MASK_MASK 0x00000200L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF2_DSTATE_INTR_MASK_MASK 0x00000400L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF3_DSTATE_INTR_MASK_MASK 0x00000800L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF4_DSTATE_INTR_MASK_MASK 0x00001000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF5_DSTATE_INTR_MASK_MASK 0x00002000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF6_DSTATE_INTR_MASK_MASK 0x00004000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV1_PF7_DSTATE_INTR_MASK_MASK 0x00008000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF0_DSTATE_INTR_MASK_MASK 0x00010000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF1_DSTATE_INTR_MASK_MASK 0x00020000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF2_DSTATE_INTR_MASK_MASK 0x00040000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF3_DSTATE_INTR_MASK_MASK 0x00080000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF4_DSTATE_INTR_MASK_MASK 0x00100000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF5_DSTATE_INTR_MASK_MASK 0x00200000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF6_DSTATE_INTR_MASK_MASK 0x00400000L
+#define BIF_PF_DSTATE_INTR_MASK__DEV2_PF7_DSTATE_INTR_MASK_MASK 0x00800000L
+//BIF_PF_FLR_RST
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6
+#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7
+#define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST__SHIFT 0x8
+#define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST__SHIFT 0x9
+#define BIF_PF_FLR_RST__DEV1_PF2_FLR_RST__SHIFT 0xa
+#define BIF_PF_FLR_RST__DEV1_PF3_FLR_RST__SHIFT 0xb
+#define BIF_PF_FLR_RST__DEV1_PF4_FLR_RST__SHIFT 0xc
+#define BIF_PF_FLR_RST__DEV1_PF5_FLR_RST__SHIFT 0xd
+#define BIF_PF_FLR_RST__DEV1_PF6_FLR_RST__SHIFT 0xe
+#define BIF_PF_FLR_RST__DEV1_PF7_FLR_RST__SHIFT 0xf
+#define BIF_PF_FLR_RST__DEV2_PF0_FLR_RST__SHIFT 0x10
+#define BIF_PF_FLR_RST__DEV2_PF1_FLR_RST__SHIFT 0x11
+#define BIF_PF_FLR_RST__DEV2_PF2_FLR_RST__SHIFT 0x12
+#define BIF_PF_FLR_RST__DEV2_PF3_FLR_RST__SHIFT 0x13
+#define BIF_PF_FLR_RST__DEV2_PF4_FLR_RST__SHIFT 0x14
+#define BIF_PF_FLR_RST__DEV2_PF5_FLR_RST__SHIFT 0x15
+#define BIF_PF_FLR_RST__DEV2_PF6_FLR_RST__SHIFT 0x16
+#define BIF_PF_FLR_RST__DEV2_PF7_FLR_RST__SHIFT 0x17
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK 0x00000001L
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK 0x00000002L
+#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK 0x00000004L
+#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK 0x00000008L
+#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK 0x00000010L
+#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK 0x00000020L
+#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK 0x00000040L
+#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK 0x00000080L
+#define BIF_PF_FLR_RST__DEV1_PF0_FLR_RST_MASK 0x00000100L
+#define BIF_PF_FLR_RST__DEV1_PF1_FLR_RST_MASK 0x00000200L
+#define BIF_PF_FLR_RST__DEV1_PF2_FLR_RST_MASK 0x00000400L
+#define BIF_PF_FLR_RST__DEV1_PF3_FLR_RST_MASK 0x00000800L
+#define BIF_PF_FLR_RST__DEV1_PF4_FLR_RST_MASK 0x00001000L
+#define BIF_PF_FLR_RST__DEV1_PF5_FLR_RST_MASK 0x00002000L
+#define BIF_PF_FLR_RST__DEV1_PF6_FLR_RST_MASK 0x00004000L
+#define BIF_PF_FLR_RST__DEV1_PF7_FLR_RST_MASK 0x00008000L
+#define BIF_PF_FLR_RST__DEV2_PF0_FLR_RST_MASK 0x00010000L
+#define BIF_PF_FLR_RST__DEV2_PF1_FLR_RST_MASK 0x00020000L
+#define BIF_PF_FLR_RST__DEV2_PF2_FLR_RST_MASK 0x00040000L
+#define BIF_PF_FLR_RST__DEV2_PF3_FLR_RST_MASK 0x00080000L
+#define BIF_PF_FLR_RST__DEV2_PF4_FLR_RST_MASK 0x00100000L
+#define BIF_PF_FLR_RST__DEV2_PF5_FLR_RST_MASK 0x00200000L
+#define BIF_PF_FLR_RST__DEV2_PF6_FLR_RST_MASK 0x00400000L
+#define BIF_PF_FLR_RST__DEV2_PF7_FLR_RST_MASK 0x00800000L
+//BIF_DEV0_PF0_DSTATE_VALUE
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF1_DSTATE_VALUE
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF2_DSTATE_VALUE
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF3_DSTATE_VALUE
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF4_DSTATE_VALUE
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF5_DSTATE_VALUE
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF6_DSTATE_VALUE
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV0_PF7_DSTATE_VALUE
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L
+//DEV0_PF0_D3HOTD0_RST_CTRL
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF1_D3HOTD0_RST_CTRL
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF2_D3HOTD0_RST_CTRL
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF3_D3HOTD0_RST_CTRL
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF4_D3HOTD0_RST_CTRL
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF5_D3HOTD0_RST_CTRL
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF6_D3HOTD0_RST_CTRL
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV0_PF7_D3HOTD0_RST_CTRL
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF0_FLR_RST_CTRL
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF1_FLR_RST_CTRL
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF2_FLR_RST_CTRL
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF3_FLR_RST_CTRL
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF4_FLR_RST_CTRL
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF5_FLR_RST_CTRL
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF6_FLR_RST_CTRL
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV1_PF7_FLR_RST_CTRL
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV1_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV1_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV1_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV1_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV1_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//BIF_DEV1_PF0_DSTATE_VALUE
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF0_DSTATE_VALUE__DEV1_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF1_DSTATE_VALUE
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF1_DSTATE_VALUE__DEV1_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF2_DSTATE_VALUE
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF2_DSTATE_VALUE__DEV1_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF3_DSTATE_VALUE
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF3_DSTATE_VALUE__DEV1_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF4_DSTATE_VALUE
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF4_DSTATE_VALUE__DEV1_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF5_DSTATE_VALUE
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF5_DSTATE_VALUE__DEV1_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF6_DSTATE_VALUE
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF6_DSTATE_VALUE__DEV1_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV1_PF7_DSTATE_VALUE
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV1_PF7_DSTATE_VALUE__DEV1_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L
+//DEV1_PF0_D3HOTD0_RST_CTRL
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF1_D3HOTD0_RST_CTRL
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF2_D3HOTD0_RST_CTRL
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF3_D3HOTD0_RST_CTRL
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF4_D3HOTD0_RST_CTRL
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF5_D3HOTD0_RST_CTRL
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF6_D3HOTD0_RST_CTRL
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV1_PF7_D3HOTD0_RST_CTRL
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV1_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV2_PF0_FLR_RST_CTRL
+#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV2_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV2_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV2_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV2_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV2_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV2_PF1_FLR_RST_CTRL
+#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV2_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV2_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV2_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV2_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV2_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV2_PF2_FLR_RST_CTRL
+#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV2_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV2_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV2_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV2_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV2_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV2_PF3_FLR_RST_CTRL
+#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV2_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV2_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV2_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV2_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV2_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV2_PF4_FLR_RST_CTRL
+#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV2_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV2_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV2_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV2_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV2_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV2_PF5_FLR_RST_CTRL
+#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV2_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV2_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV2_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV2_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV2_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV2_PF6_FLR_RST_CTRL
+#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV2_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV2_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV2_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV2_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV2_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//DEV2_PF7_FLR_RST_CTRL
+#define DEV2_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11
+#define DEV2_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12
+#define DEV2_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17
+#define DEV2_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19
+#define DEV2_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+#define DEV2_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK 0x00020000L
+#define DEV2_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK 0x001C0000L
+#define DEV2_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK 0x01800000L
+#define DEV2_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK 0x06000000L
+//BIF_DEV2_PF0_DSTATE_VALUE
+#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV2_PF0_DSTATE_VALUE__DEV2_PF0_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV2_PF1_DSTATE_VALUE
+#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV2_PF1_DSTATE_VALUE__DEV2_PF1_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV2_PF2_DSTATE_VALUE
+#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV2_PF2_DSTATE_VALUE__DEV2_PF2_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV2_PF3_DSTATE_VALUE
+#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV2_PF3_DSTATE_VALUE__DEV2_PF3_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV2_PF4_DSTATE_VALUE
+#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV2_PF4_DSTATE_VALUE__DEV2_PF4_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV2_PF5_DSTATE_VALUE
+#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV2_PF5_DSTATE_VALUE__DEV2_PF5_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV2_PF6_DSTATE_VALUE
+#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV2_PF6_DSTATE_VALUE__DEV2_PF6_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_DEV2_PF7_DSTATE_VALUE
+#define BIF_DEV2_PF7_DSTATE_VALUE__DEV2_PF7_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_DEV2_PF7_DSTATE_VALUE__DEV2_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2
+#define BIF_DEV2_PF7_DSTATE_VALUE__DEV2_PF7_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_DEV2_PF7_DSTATE_VALUE__DEV2_PF7_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_DEV2_PF7_DSTATE_VALUE__DEV2_PF7_DSTATE_NEED_D3TOD0_RESET_MASK 0x00000004L
+#define BIF_DEV2_PF7_DSTATE_VALUE__DEV2_PF7_DSTATE_ACK_VALUE_MASK 0x00030000L
+//DEV2_PF0_D3HOTD0_RST_CTRL
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV2_PF1_D3HOTD0_RST_CTRL
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV2_PF2_D3HOTD0_RST_CTRL
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV2_PF3_D3HOTD0_RST_CTRL
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV2_PF4_D3HOTD0_RST_CTRL
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV2_PF5_D3HOTD0_RST_CTRL
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV2_PF6_D3HOTD0_RST_CTRL
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//DEV2_PF7_D3HOTD0_RST_CTRL
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK 0x00000001L
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK 0x00000002L
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK 0x00000004L
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK 0x00000008L
+#define DEV2_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK 0x00000010L
+//BIF_PORT0_DSTATE_VALUE
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_PORT1_DSTATE_VALUE
+#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_PORT1_DSTATE_VALUE__PORT1_DSTATE_ACK_VALUE_MASK 0x00030000L
+//BIF_PORT2_DSTATE_VALUE
+#define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_TGT_VALUE__SHIFT 0x0
+#define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_ACK_VALUE__SHIFT 0x10
+#define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_TGT_VALUE_MASK 0x00000003L
+#define BIF_PORT2_DSTATE_VALUE__PORT2_DSTATE_ACK_VALUE_MASK 0x00030000L
+
+
+// addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk
+//BIFL_RAS_CENTRAL_CNTL
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT 0x1d
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT 0x1e
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT 0x1f
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK 0x20000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK 0x40000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK 0x80000000L
+//BIFL_RAS_CENTRAL_STATUS
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT 0x0
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT 0x1
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT 0x2
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT 0x3
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT 0x1d
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT 0x1e
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT 0x1f
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK 0x00000001L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK 0x00000002L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK 0x00000004L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK 0x00000008L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK 0x20000000L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK 0x40000000L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK 0x80000000L
+//BIFL_RAS_LEAF0_CTRL
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+//BIFL_RAS_LEAF1_CTRL
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+//BIFL_RAS_LEAF2_CTRL
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+//BIFL_RAS_LEAF3_CTRL
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN__SHIFT 0x0
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1
+#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x3
+#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x4
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT 0x5
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN__SHIFT 0x6
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN__SHIFT 0xa
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN__SHIFT 0xb
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT 0x10
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN_MASK 0x00000001L
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK 0x00000002L
+#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK 0x00000004L
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK 0x00000008L
+#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK 0x00000010L
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN_MASK 0x00000020L
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN_MASK 0x00000040L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN_MASK 0x00000400L
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN_MASK 0x00000800L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN_MASK 0x00010000L
+//BIFL_RAS_LEAF0_STATUS
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_RAS_LEAF1_STATUS
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_RAS_LEAF2_STATUS
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_RAS_LEAF3_STATUS
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV__SHIFT 0x0
+#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET__SHIFT 0x1
+#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET__SHIFT 0x2
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT__SHIFT 0x8
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT 0x9
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT__SHIFT 0xa
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT 0xb
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV_MASK 0x00000001L
+#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET_MASK 0x00000002L
+#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET_MASK 0x00000004L
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT_MASK 0x00000100L
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT_MASK 0x00000200L
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT_MASK 0x00000400L
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT_MASK 0x00000800L
+//BIFL_IOHUB_RAS_IH_CNTL
+#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT 0x0
+#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK 0x00000001L
+//BIFL_RAS_VWR_FROM_IOHUB
+#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT 0x0
+#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_nbif_sion_SIONDEC
+//SION_CL0_RdRsp_BurstTarget_REG0
+#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_BurstTarget_REG1
+#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_TimeSlot_REG0
+#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_RdRsp_TimeSlot_REG1
+#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_BurstTarget_REG0
+#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_BurstTarget_REG1
+#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_TimeSlot_REG0
+#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_WrRsp_TimeSlot_REG1
+#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_Req_BurstTarget_REG0
+#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_Req_BurstTarget_REG1
+#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_Req_TimeSlot_REG0
+#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_Req_TimeSlot_REG1
+#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_ReqPoolCredit_Alloc_REG0
+#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_ReqPoolCredit_Alloc_REG1
+#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_DataPoolCredit_Alloc_REG0
+#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_DataPoolCredit_Alloc_REG1
+#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_RdRspPoolCredit_Alloc_REG0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_RdRspPoolCredit_Alloc_REG1
+#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL0_WrRspPoolCredit_Alloc_REG0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL0_WrRspPoolCredit_Alloc_REG1
+#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_BurstTarget_REG0
+#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_BurstTarget_REG1
+#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_TimeSlot_REG0
+#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_RdRsp_TimeSlot_REG1
+#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_BurstTarget_REG0
+#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_BurstTarget_REG1
+#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_TimeSlot_REG0
+#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_WrRsp_TimeSlot_REG1
+#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_Req_BurstTarget_REG0
+#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_Req_BurstTarget_REG1
+#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_Req_TimeSlot_REG0
+#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_Req_TimeSlot_REG1
+#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_ReqPoolCredit_Alloc_REG0
+#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_ReqPoolCredit_Alloc_REG1
+#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_DataPoolCredit_Alloc_REG0
+#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_DataPoolCredit_Alloc_REG1
+#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_RdRspPoolCredit_Alloc_REG0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_RdRspPoolCredit_Alloc_REG1
+#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL1_WrRspPoolCredit_Alloc_REG0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL1_WrRspPoolCredit_Alloc_REG1
+#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_BurstTarget_REG0
+#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_BurstTarget_REG1
+#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_TimeSlot_REG0
+#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_RdRsp_TimeSlot_REG1
+#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_BurstTarget_REG0
+#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_BurstTarget_REG1
+#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_TimeSlot_REG0
+#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_WrRsp_TimeSlot_REG1
+#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_Req_BurstTarget_REG0
+#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0
+#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_Req_BurstTarget_REG1
+#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0
+#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_Req_TimeSlot_REG0
+#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0
+#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_Req_TimeSlot_REG1
+#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0
+#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_ReqPoolCredit_Alloc_REG0
+#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_ReqPoolCredit_Alloc_REG1
+#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_DataPoolCredit_Alloc_REG0
+#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_DataPoolCredit_Alloc_REG1
+#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_RdRspPoolCredit_Alloc_REG0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_RdRspPoolCredit_Alloc_REG1
+#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CL2_WrRspPoolCredit_Alloc_REG0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK 0xFFFFFFFFL
+//SION_CL2_WrRspPoolCredit_Alloc_REG1
+#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0
+#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK 0xFFFFFFFFL
+//SION_CNTL_REG0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK 0x00000001L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK 0x00000002L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK 0x00000004L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK 0x00000008L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK 0x00000010L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK 0x00000020L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK 0x00000040L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK 0x00000080L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK 0x00000100L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK 0x00000200L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK 0x00000400L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK 0x00000800L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK 0x00001000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK 0x00002000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK 0x00004000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK 0x00008000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK 0x00010000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK 0x00020000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK 0x00040000L
+#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK 0x00080000L
+//SION_CNTL_REG1
+#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0
+#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8
+#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD_MASK 0x000000FFL
+#define SION_CNTL_REG1__CG_OFF_HYSTERESIS_MASK 0x0000FF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_0_STATUS
+#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_HEADER
+#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_0_BIST
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_COMMAND
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_0_STATUS
+#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_LATENCY
+#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_HEADER
+#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_0_BIST
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_COMMAND
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_0_STATUS
+#define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_LATENCY
+#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_HEADER
+#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF2_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_0_BIST
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF2_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_SBRN
+#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_FLADJ
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF2_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF2_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF2_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_COMMAND
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_0_STATUS
+#define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_LATENCY
+#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_HEADER
+#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF3_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_0_BIST
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF3_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_SBRN
+#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_FLADJ
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF3_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF3_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF3_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF4_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_COMMAND
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF4_0_STATUS
+#define BIF_CFG_DEV0_EPF4_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_LATENCY
+#define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_HEADER
+#define BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF4_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF4_0_BIST
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF4_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_0_SBRN
+#define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_FLADJ
+#define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF4_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF4_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF4_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF4_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF4_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF5_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_COMMAND
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF5_0_STATUS
+#define BIF_CFG_DEV0_EPF5_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_LATENCY
+#define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_HEADER
+#define BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF5_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF5_0_BIST
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF5_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_0_SBRN
+#define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_FLADJ
+#define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF5_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF5_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF5_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF5_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF5_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF6_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_COMMAND
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF6_0_STATUS
+#define BIF_CFG_DEV0_EPF6_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_LATENCY
+#define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_HEADER
+#define BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF6_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF6_0_BIST
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF6_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_0_SBRN
+#define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_FLADJ
+#define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF6_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF6_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF6_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF6_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF6_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF7_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_COMMAND
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF7_0_STATUS
+#define BIF_CFG_DEV0_EPF7_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_LATENCY
+#define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_HEADER
+#define BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF7_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF7_0_BIST
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF7_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_0_SBRN
+#define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_FLADJ
+#define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF7_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF7_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF7_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF7_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF7_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF7_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp
+//BIF_CFG_DEV1_EPF0_0_VENDOR_ID
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_DEVICE_ID
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_COMMAND
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF0_0_STATUS
+#define BIF_CFG_DEV1_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_REVISION_ID
+#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_SUB_CLASS
+#define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_CLASS
+#define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_CACHE_LINE
+#define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_LATENCY
+#define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_HEADER
+#define BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF0_0_BIST
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF0_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV1_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_CAP_PTR
+#define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_MIN_GRANT
+#define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PMI_CAP
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_SBRN
+#define BIF_CFG_DEV1_EPF0_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_FLADJ
+#define BIF_CFG_DEV1_EPF0_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV1_EPF0_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV1_EPF0_0_LINK_CAP
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_LINK_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV1_EPF0_0_LINK_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_LINK_CAP2
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_0_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF0_0_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_MASK
+#define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_PENDING
+#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_0_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_0_MSIX_PBA
+#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV1_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp
+//BIF_CFG_DEV1_EPF1_0_VENDOR_ID
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_DEVICE_ID
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_COMMAND
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF1_0_STATUS
+#define BIF_CFG_DEV1_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_0_REVISION_ID
+#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_SUB_CLASS
+#define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_CLASS
+#define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_CACHE_LINE
+#define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_LATENCY
+#define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_HEADER
+#define BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF1_0_BIST
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF1_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV1_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_CAP_PTR
+#define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_MIN_GRANT
+#define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PMI_CAP
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_0_SBRN
+#define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_FLADJ
+#define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV1_EPF1_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV1_EPF1_0_LINK_CAP
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_0_LINK_CNTL
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV1_EPF1_0_LINK_STATUS
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_LINK_CAP2
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF1_0_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF1_0_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_MASK
+#define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_PENDING
+#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_0_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_0_MSIX_PBA
+#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf0_bifcfgdecp
+//BIF_CFG_DEV2_EPF0_0_VENDOR_ID
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_DEVICE_ID
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_COMMAND
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF0_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV2_EPF0_0_STATUS
+#define BIF_CFG_DEV2_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV2_EPF0_0_REVISION_ID
+#define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_PROG_INTERFACE
+#define BIF_CFG_DEV2_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_SUB_CLASS
+#define BIF_CFG_DEV2_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_BASE_CLASS
+#define BIF_CFG_DEV2_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_CACHE_LINE
+#define BIF_CFG_DEV2_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_LATENCY
+#define BIF_CFG_DEV2_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_HEADER
+#define BIF_CFG_DEV2_EPF0_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV2_EPF0_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV2_EPF0_0_BIST
+#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV2_EPF0_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_1
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_2
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_3
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_4
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_5
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_BASE_ADDR_6
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV2_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_ADAPTER_ID
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_CAP_PTR
+#define BIF_CFG_DEV2_EPF0_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE
+#define BIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN
+#define BIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_MIN_GRANT
+#define BIF_CFG_DEV2_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_MAX_LATENCY
+#define BIF_CFG_DEV2_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV2_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PMI_CAP
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF0_0_SBRN
+#define BIF_CFG_DEV2_EPF0_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_FLADJ
+#define BIF_CFG_DEV2_EPF0_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV2_EPF0_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD
+#define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV2_EPF0_0_DEVICE_CAP
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV2_EPF0_0_LINK_CAP
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF0_0_LINK_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV2_EPF0_0_LINK_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_LINK_CAP2
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF0_0_LINK_CNTL2
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV2_EPF0_0_LINK_STATUS2
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_MASK
+#define BIF_CFG_DEV2_EPF0_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_MASK_64
+#define BIF_CFG_DEV2_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_PENDING
+#define BIF_CFG_DEV2_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSI_PENDING_64
+#define BIF_CFG_DEV2_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV2_EPF0_0_MSIX_TABLE
+#define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF0_0_MSIX_PBA
+#define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV2_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV2_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf1_bifcfgdecp
+//BIF_CFG_DEV2_EPF1_0_VENDOR_ID
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_DEVICE_ID
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_COMMAND
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF1_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV2_EPF1_0_STATUS
+#define BIF_CFG_DEV2_EPF1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV2_EPF1_0_REVISION_ID
+#define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV2_EPF1_0_PROG_INTERFACE
+#define BIF_CFG_DEV2_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_SUB_CLASS
+#define BIF_CFG_DEV2_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_BASE_CLASS
+#define BIF_CFG_DEV2_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_CACHE_LINE
+#define BIF_CFG_DEV2_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_LATENCY
+#define BIF_CFG_DEV2_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_HEADER
+#define BIF_CFG_DEV2_EPF1_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV2_EPF1_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV2_EPF1_0_BIST
+#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV2_EPF1_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_1
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_2
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_3
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_4
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_5
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_BASE_ADDR_6
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV2_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_ADAPTER_ID
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_CAP_PTR
+#define BIF_CFG_DEV2_EPF1_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE
+#define BIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN
+#define BIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_MIN_GRANT
+#define BIF_CFG_DEV2_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_MAX_LATENCY
+#define BIF_CFG_DEV2_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV2_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PMI_CAP
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF1_0_SBRN
+#define BIF_CFG_DEV2_EPF1_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_FLADJ
+#define BIF_CFG_DEV2_EPF1_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV2_EPF1_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD
+#define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF1_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV2_EPF1_0_DEVICE_CAP
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV2_EPF1_0_LINK_CAP
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF1_0_LINK_CNTL
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV2_EPF1_0_LINK_STATUS
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_LINK_CAP2
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF1_0_LINK_CNTL2
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV2_EPF1_0_LINK_STATUS2
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV2_EPF1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_MASK
+#define BIF_CFG_DEV2_EPF1_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_MASK_64
+#define BIF_CFG_DEV2_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_PENDING
+#define BIF_CFG_DEV2_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSI_PENDING_64
+#define BIF_CFG_DEV2_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV2_EPF1_0_MSIX_TABLE
+#define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF1_0_MSIX_PBA
+#define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf2_bifcfgdecp
+//BIF_CFG_DEV2_EPF2_0_VENDOR_ID
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_DEVICE_ID
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_COMMAND
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF2_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV2_EPF2_0_STATUS
+#define BIF_CFG_DEV2_EPF2_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV2_EPF2_0_REVISION_ID
+#define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV2_EPF2_0_PROG_INTERFACE
+#define BIF_CFG_DEV2_EPF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_SUB_CLASS
+#define BIF_CFG_DEV2_EPF2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_BASE_CLASS
+#define BIF_CFG_DEV2_EPF2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_CACHE_LINE
+#define BIF_CFG_DEV2_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_LATENCY
+#define BIF_CFG_DEV2_EPF2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_HEADER
+#define BIF_CFG_DEV2_EPF2_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV2_EPF2_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV2_EPF2_0_BIST
+#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV2_EPF2_0_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_1
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_2
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_3
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_4
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_5
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_BASE_ADDR_6
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV2_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_ADAPTER_ID
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_CAP_PTR
+#define BIF_CFG_DEV2_EPF2_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE
+#define BIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN
+#define BIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_MIN_GRANT
+#define BIF_CFG_DEV2_EPF2_0_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_MAX_LATENCY
+#define BIF_CFG_DEV2_EPF2_0_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV2_EPF2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PMI_CAP
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF2_0_SBRN
+#define BIF_CFG_DEV2_EPF2_0_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_FLADJ
+#define BIF_CFG_DEV2_EPF2_0_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV2_EPF2_0_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV2_EPF2_0_DBESL_DBESLD
+#define BIF_CFG_DEV2_EPF2_0_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF2_0_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV2_EPF2_0_DEVICE_CAP
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV2_EPF2_0_LINK_CAP
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF2_0_LINK_CNTL
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV2_EPF2_0_LINK_STATUS
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_LINK_CAP2
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF2_0_LINK_CNTL2
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV2_EPF2_0_LINK_STATUS2
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV2_EPF2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_MASK
+#define BIF_CFG_DEV2_EPF2_0_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_MASK_64
+#define BIF_CFG_DEV2_EPF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_PENDING
+#define BIF_CFG_DEV2_EPF2_0_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSI_PENDING_64
+#define BIF_CFG_DEV2_EPF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV2_EPF2_0_MSIX_TABLE
+#define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF2_0_MSIX_PBA
+#define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_0_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+
+
+
+
+// addressBlock: nbio_nbif0_pciemsix_0_mp2_MSIXTDEC
+
+
+
+
+
+
+
+
+// addressBlock: nbio_nbif0_pciemsix_0_mp2_MSIXPDEC
+
+
+
+
+// addressBlock: nbio_pcie0_bifplr0_cfgdecp
+//BIFPLR0_0_VENDOR_ID
+#define BIFPLR0_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR0_0_DEVICE_ID
+#define BIFPLR0_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR0_0_COMMAND
+#define BIFPLR0_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR0_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR0_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR0_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR0_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR0_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR0_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR0_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR0_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR0_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR0_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR0_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR0_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR0_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR0_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR0_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR0_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR0_0_STATUS
+#define BIFPLR0_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR0_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR0_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR0_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR0_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR0_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR0_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR0_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR0_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR0_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR0_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR0_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR0_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR0_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR0_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR0_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR0_0_REVISION_ID
+#define BIFPLR0_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR0_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR0_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR0_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR0_0_PROG_INTERFACE
+#define BIFPLR0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR0_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR0_0_SUB_CLASS
+#define BIFPLR0_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR0_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR0_0_BASE_CLASS
+#define BIFPLR0_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR0_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR0_0_CACHE_LINE
+#define BIFPLR0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR0_0_LATENCY
+#define BIFPLR0_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR0_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR0_0_HEADER
+#define BIFPLR0_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR0_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR0_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR0_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR0_0_BIST
+#define BIFPLR0_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR0_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR0_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR0_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR0_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR0_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR0_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR0_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR0_0_IO_BASE_LIMIT
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR0_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR0_0_SECONDARY_STATUS
+#define BIFPLR0_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR0_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR0_0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR0_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR0_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR0_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR0_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR0_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR0_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR0_0_MEM_BASE_LIMIT
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR0_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR0_0_PREF_BASE_LIMIT
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR0_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR0_0_PREF_BASE_UPPER
+#define BIFPLR0_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR0_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PREF_LIMIT_UPPER
+#define BIFPLR0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR0_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR0_0_IO_BASE_LIMIT_HI
+#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR0_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR0_0_CAP_PTR
+#define BIFPLR0_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR0_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR0_0_ROM_BASE_ADDR
+#define BIFPLR0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR0_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_INTERRUPT_LINE
+#define BIFPLR0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR0_0_INTERRUPT_PIN
+#define BIFPLR0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR0_0_IRQ_BRIDGE_CNTL
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR0_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR0_0_EXT_BRIDGE_CNTL
+#define BIFPLR0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR0_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR0_0_VENDOR_CAP_LIST
+#define BIFPLR0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR0_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR0_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR0_0_ADAPTER_ID_W
+#define BIFPLR0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR0_0_PMI_CAP_LIST
+#define BIFPLR0_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_0_PMI_CAP
+#define BIFPLR0_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR0_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR0_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR0_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR0_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR0_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR0_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR0_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR0_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR0_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR0_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR0_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR0_0_PMI_STATUS_CNTL
+#define BIFPLR0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR0_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR0_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR0_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR0_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR0_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR0_0_PCIE_CAP_LIST
+#define BIFPLR0_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_0_PCIE_CAP
+#define BIFPLR0_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR0_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR0_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR0_0_DEVICE_CAP
+#define BIFPLR0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR0_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR0_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR0_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR0_0_DEVICE_CNTL
+#define BIFPLR0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR0_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR0_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR0_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR0_0_DEVICE_STATUS
+#define BIFPLR0_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR0_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR0_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR0_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR0_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR0_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR0_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR0_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR0_0_LINK_CAP
+#define BIFPLR0_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR0_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR0_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR0_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR0_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR0_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR0_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR0_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR0_0_LINK_CNTL
+#define BIFPLR0_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR0_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR0_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR0_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR0_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR0_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR0_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR0_0_LINK_STATUS
+#define BIFPLR0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR0_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR0_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR0_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR0_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR0_0_SLOT_CAP
+#define BIFPLR0_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR0_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR0_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR0_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR0_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR0_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR0_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR0_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR0_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR0_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR0_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR0_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR0_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR0_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR0_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR0_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR0_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR0_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR0_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR0_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR0_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR0_0_SLOT_CNTL
+#define BIFPLR0_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR0_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR0_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR0_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR0_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR0_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR0_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR0_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR0_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR0_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR0_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR0_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR0_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR0_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR0_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR0_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR0_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR0_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR0_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR0_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR0_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR0_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR0_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR0_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR0_0_SLOT_STATUS
+#define BIFPLR0_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR0_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR0_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR0_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR0_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR0_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR0_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR0_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR0_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR0_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR0_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR0_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR0_0_ROOT_CNTL
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR0_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR0_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR0_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR0_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR0_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR0_0_ROOT_CAP
+#define BIFPLR0_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR0_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR0_0_ROOT_STATUS
+#define BIFPLR0_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR0_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR0_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR0_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR0_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR0_0_DEVICE_CAP2
+#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR0_0_DEVICE_CNTL2
+#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR0_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR0_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR0_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR0_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR0_0_DEVICE_STATUS2
+#define BIFPLR0_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR0_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_0_LINK_CAP2
+#define BIFPLR0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR0_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR0_0_LINK_CNTL2
+#define BIFPLR0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR0_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR0_0_LINK_STATUS2
+#define BIFPLR0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR0_0_SLOT_CAP2
+#define BIFPLR0_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR0_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_0_SLOT_CNTL2
+#define BIFPLR0_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR0_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_0_SLOT_STATUS2
+#define BIFPLR0_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR0_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_0_MSI_CAP_LIST
+#define BIFPLR0_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_0_MSI_MSG_CNTL
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR0_0_MSI_MSG_ADDR_LO
+#define BIFPLR0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR0_0_MSI_MSG_ADDR_HI
+#define BIFPLR0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_0_MSI_MSG_DATA
+#define BIFPLR0_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR0_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR0_0_MSI_MSG_DATA_64
+#define BIFPLR0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR0_0_SSID_CAP_LIST
+#define BIFPLR0_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_0_SSID_CAP
+#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR0_0_MSI_MAP_CAP_LIST
+#define BIFPLR0_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_0_MSI_MAP_CAP
+#define BIFPLR0_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR0_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR0_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR0_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR0_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR0_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR0_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_0_PCIE_PORT_VC_CNTL
+#define BIFPLR0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR0_0_PCIE_PORT_VC_STATUS
+#define BIFPLR0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR0_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR0_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR0_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR0_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR0_0_PCIE_CORR_ERR_MASK
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR0_0_PCIE_HDR_LOG0
+#define BIFPLR0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_HDR_LOG1
+#define BIFPLR0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_HDR_LOG2
+#define BIFPLR0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_HDR_LOG3
+#define BIFPLR0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR0_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR0_0_PCIE_ERR_SRC_ID
+#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR0_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_LINK_CNTL3
+#define BIFPLR0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR0_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_ACS_CAP
+#define BIFPLR0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR0_0_PCIE_ACS_CNTL
+#define BIFPLR0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR0_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_MC_CAP
+#define BIFPLR0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR0_0_PCIE_MC_CNTL
+#define BIFPLR0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR0_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR0_0_PCIE_MC_ADDR0
+#define BIFPLR0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR0_0_PCIE_MC_ADDR1
+#define BIFPLR0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_RCV0
+#define BIFPLR0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_RCV1
+#define BIFPLR0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR0_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR0_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR0_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_DPC_CAP_LIST
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR0_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR0_0_PCIE_DPC_CNTL
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR0_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR0_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR0_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR0_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR0_0_PCIE_DPC_STATUS
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR0_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR0_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR0_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_STATUS
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_MASK
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_ESM_CAP_LIST
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_ESM_HEADER_1
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_ESM_HEADER_2
+#define BIFPLR0_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR0_0_PCIE_ESM_STATUS
+#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR0_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR0_0_PCIE_ESM_CTRL
+#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR0_0_PCIE_ESM_CAP_1
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_2
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_3
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR0_0_PCIE_ESM_CAP_4
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_5
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_6
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR0_0_PCIE_ESM_CAP_7
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR0_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR0_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_LINK_CAP_16GT
+#define BIFPLR0_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR0_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_0_LINK_CNTL_16GT
+#define BIFPLR0_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR0_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_0_LINK_STATUS_16GT
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_MARGINING_PORT_CAP
+#define BIFPLR0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR0_0_MARGINING_PORT_STATUS
+#define BIFPLR0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR0_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_CCIX_HEADER_1
+#define BIFPLR0_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR0_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR0_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR0_0_PCIE_CCIX_HEADER_2
+#define BIFPLR0_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR0_0_PCIE_CCIX_CAP
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR0_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR0_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR0_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR0_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR0_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR0_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR0_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR0_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR0_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR0_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR0_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR0_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR0_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr1_cfgdecp
+//BIFPLR1_0_VENDOR_ID
+#define BIFPLR1_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR1_0_DEVICE_ID
+#define BIFPLR1_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR1_0_COMMAND
+#define BIFPLR1_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR1_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR1_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR1_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR1_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR1_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR1_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR1_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR1_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR1_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR1_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR1_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR1_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR1_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR1_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR1_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR1_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR1_0_STATUS
+#define BIFPLR1_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR1_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR1_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR1_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR1_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR1_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR1_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR1_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR1_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR1_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR1_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR1_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR1_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR1_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR1_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR1_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR1_0_REVISION_ID
+#define BIFPLR1_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR1_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR1_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR1_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR1_0_PROG_INTERFACE
+#define BIFPLR1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR1_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR1_0_SUB_CLASS
+#define BIFPLR1_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR1_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR1_0_BASE_CLASS
+#define BIFPLR1_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR1_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR1_0_CACHE_LINE
+#define BIFPLR1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR1_0_LATENCY
+#define BIFPLR1_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR1_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR1_0_HEADER
+#define BIFPLR1_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR1_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR1_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR1_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR1_0_BIST
+#define BIFPLR1_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR1_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR1_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR1_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR1_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR1_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR1_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR1_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR1_0_IO_BASE_LIMIT
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR1_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR1_0_SECONDARY_STATUS
+#define BIFPLR1_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR1_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR1_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR1_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR1_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR1_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR1_0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR1_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR1_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR1_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR1_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR1_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR1_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR1_0_MEM_BASE_LIMIT
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR1_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR1_0_PREF_BASE_LIMIT
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR1_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR1_0_PREF_BASE_UPPER
+#define BIFPLR1_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR1_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PREF_LIMIT_UPPER
+#define BIFPLR1_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR1_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR1_0_IO_BASE_LIMIT_HI
+#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR1_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR1_0_CAP_PTR
+#define BIFPLR1_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR1_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR1_0_ROM_BASE_ADDR
+#define BIFPLR1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR1_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_INTERRUPT_LINE
+#define BIFPLR1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR1_0_INTERRUPT_PIN
+#define BIFPLR1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR1_0_IRQ_BRIDGE_CNTL
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR1_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR1_0_EXT_BRIDGE_CNTL
+#define BIFPLR1_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR1_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR1_0_VENDOR_CAP_LIST
+#define BIFPLR1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR1_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR1_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR1_0_ADAPTER_ID_W
+#define BIFPLR1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR1_0_PMI_CAP_LIST
+#define BIFPLR1_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_0_PMI_CAP
+#define BIFPLR1_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR1_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR1_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR1_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR1_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR1_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR1_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR1_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR1_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR1_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR1_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR1_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR1_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR1_0_PMI_STATUS_CNTL
+#define BIFPLR1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR1_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR1_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR1_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR1_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR1_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR1_0_PCIE_CAP_LIST
+#define BIFPLR1_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_0_PCIE_CAP
+#define BIFPLR1_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR1_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR1_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR1_0_DEVICE_CAP
+#define BIFPLR1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR1_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR1_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR1_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR1_0_DEVICE_CNTL
+#define BIFPLR1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR1_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR1_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR1_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR1_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR1_0_DEVICE_STATUS
+#define BIFPLR1_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR1_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR1_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR1_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR1_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR1_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR1_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR1_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR1_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR1_0_LINK_CAP
+#define BIFPLR1_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR1_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR1_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR1_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR1_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR1_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR1_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR1_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR1_0_LINK_CNTL
+#define BIFPLR1_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR1_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR1_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR1_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR1_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR1_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR1_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR1_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR1_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR1_0_LINK_STATUS
+#define BIFPLR1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR1_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR1_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR1_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR1_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR1_0_SLOT_CAP
+#define BIFPLR1_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR1_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR1_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR1_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR1_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR1_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR1_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR1_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR1_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR1_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR1_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR1_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR1_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR1_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR1_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR1_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR1_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR1_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR1_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR1_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR1_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR1_0_SLOT_CNTL
+#define BIFPLR1_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR1_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR1_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR1_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR1_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR1_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR1_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR1_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR1_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR1_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR1_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR1_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR1_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR1_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR1_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR1_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR1_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR1_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR1_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR1_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR1_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR1_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR1_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR1_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR1_0_SLOT_STATUS
+#define BIFPLR1_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR1_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR1_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR1_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR1_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR1_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR1_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR1_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR1_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR1_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR1_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR1_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR1_0_ROOT_CNTL
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR1_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR1_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR1_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR1_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR1_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR1_0_ROOT_CAP
+#define BIFPLR1_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR1_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR1_0_ROOT_STATUS
+#define BIFPLR1_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR1_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR1_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR1_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR1_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR1_0_DEVICE_CAP2
+#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR1_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR1_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR1_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR1_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR1_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR1_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR1_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR1_0_DEVICE_CNTL2
+#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR1_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR1_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR1_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR1_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR1_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR1_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR1_0_DEVICE_STATUS2
+#define BIFPLR1_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR1_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_0_LINK_CAP2
+#define BIFPLR1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR1_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR1_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR1_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR1_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR1_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR1_0_LINK_CNTL2
+#define BIFPLR1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR1_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR1_0_LINK_STATUS2
+#define BIFPLR1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR1_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR1_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR1_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR1_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR1_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR1_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR1_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR1_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR1_0_SLOT_CAP2
+#define BIFPLR1_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR1_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_0_SLOT_CNTL2
+#define BIFPLR1_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR1_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_0_SLOT_STATUS2
+#define BIFPLR1_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR1_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_0_MSI_CAP_LIST
+#define BIFPLR1_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_0_MSI_MSG_CNTL
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR1_0_MSI_MSG_ADDR_LO
+#define BIFPLR1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR1_0_MSI_MSG_ADDR_HI
+#define BIFPLR1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_0_MSI_MSG_DATA
+#define BIFPLR1_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR1_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR1_0_MSI_MSG_DATA_64
+#define BIFPLR1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR1_0_SSID_CAP_LIST
+#define BIFPLR1_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_0_SSID_CAP
+#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR1_0_MSI_MAP_CAP_LIST
+#define BIFPLR1_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_0_MSI_MAP_CAP
+#define BIFPLR1_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR1_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR1_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR1_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR1_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR1_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR1_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_0_PCIE_PORT_VC_CNTL
+#define BIFPLR1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR1_0_PCIE_PORT_VC_STATUS
+#define BIFPLR1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR1_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR1_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR1_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR1_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR1_0_PCIE_CORR_ERR_MASK
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR1_0_PCIE_HDR_LOG0
+#define BIFPLR1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_HDR_LOG1
+#define BIFPLR1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_HDR_LOG2
+#define BIFPLR1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_HDR_LOG3
+#define BIFPLR1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR1_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR1_0_PCIE_ERR_SRC_ID
+#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR1_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_LINK_CNTL3
+#define BIFPLR1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR1_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_ACS_CAP
+#define BIFPLR1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR1_0_PCIE_ACS_CNTL
+#define BIFPLR1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR1_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_MC_CAP
+#define BIFPLR1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR1_0_PCIE_MC_CNTL
+#define BIFPLR1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR1_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR1_0_PCIE_MC_ADDR0
+#define BIFPLR1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR1_0_PCIE_MC_ADDR1
+#define BIFPLR1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_RCV0
+#define BIFPLR1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_RCV1
+#define BIFPLR1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR1_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR1_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR1_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_DPC_CAP_LIST
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR1_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR1_0_PCIE_DPC_CNTL
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR1_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR1_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR1_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR1_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR1_0_PCIE_DPC_STATUS
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR1_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR1_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR1_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_STATUS
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_MASK
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_ESM_CAP_LIST
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_ESM_HEADER_1
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_ESM_HEADER_2
+#define BIFPLR1_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR1_0_PCIE_ESM_STATUS
+#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR1_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR1_0_PCIE_ESM_CTRL
+#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR1_0_PCIE_ESM_CAP_1
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_2
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_3
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR1_0_PCIE_ESM_CAP_4
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_5
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_6
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR1_0_PCIE_ESM_CAP_7
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR1_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR1_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR1_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR1_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR1_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_LINK_CAP_16GT
+#define BIFPLR1_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR1_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_0_LINK_CNTL_16GT
+#define BIFPLR1_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR1_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_0_LINK_STATUS_16GT
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR1_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR1_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR1_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR1_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_MARGINING_PORT_CAP
+#define BIFPLR1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR1_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR1_0_MARGINING_PORT_STATUS
+#define BIFPLR1_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR1_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR1_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR1_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_CCIX_HEADER_1
+#define BIFPLR1_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR1_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR1_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR1_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR1_0_PCIE_CCIX_HEADER_2
+#define BIFPLR1_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR1_0_PCIE_CCIX_CAP
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR1_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR1_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR1_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR1_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR1_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR1_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR1_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR1_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR1_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR1_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR1_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR1_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR1_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr2_cfgdecp
+//BIFPLR2_0_VENDOR_ID
+#define BIFPLR2_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR2_0_DEVICE_ID
+#define BIFPLR2_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR2_0_COMMAND
+#define BIFPLR2_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR2_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR2_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR2_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR2_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR2_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR2_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR2_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR2_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR2_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR2_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR2_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR2_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR2_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR2_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR2_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR2_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR2_0_STATUS
+#define BIFPLR2_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR2_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR2_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR2_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR2_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR2_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR2_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR2_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR2_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR2_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR2_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR2_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR2_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR2_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR2_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR2_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR2_0_REVISION_ID
+#define BIFPLR2_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR2_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR2_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR2_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR2_0_PROG_INTERFACE
+#define BIFPLR2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR2_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR2_0_SUB_CLASS
+#define BIFPLR2_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR2_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR2_0_BASE_CLASS
+#define BIFPLR2_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR2_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR2_0_CACHE_LINE
+#define BIFPLR2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR2_0_LATENCY
+#define BIFPLR2_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR2_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR2_0_HEADER
+#define BIFPLR2_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR2_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR2_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR2_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR2_0_BIST
+#define BIFPLR2_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR2_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR2_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR2_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR2_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR2_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR2_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR2_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR2_0_IO_BASE_LIMIT
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR2_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR2_0_SECONDARY_STATUS
+#define BIFPLR2_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR2_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR2_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR2_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR2_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR2_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR2_0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR2_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR2_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR2_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR2_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR2_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR2_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR2_0_MEM_BASE_LIMIT
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR2_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR2_0_PREF_BASE_LIMIT
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR2_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR2_0_PREF_BASE_UPPER
+#define BIFPLR2_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR2_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PREF_LIMIT_UPPER
+#define BIFPLR2_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR2_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR2_0_IO_BASE_LIMIT_HI
+#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR2_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR2_0_CAP_PTR
+#define BIFPLR2_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR2_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR2_0_ROM_BASE_ADDR
+#define BIFPLR2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR2_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_INTERRUPT_LINE
+#define BIFPLR2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR2_0_INTERRUPT_PIN
+#define BIFPLR2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR2_0_IRQ_BRIDGE_CNTL
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR2_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR2_0_EXT_BRIDGE_CNTL
+#define BIFPLR2_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR2_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR2_0_VENDOR_CAP_LIST
+#define BIFPLR2_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR2_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR2_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR2_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR2_0_ADAPTER_ID_W
+#define BIFPLR2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR2_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR2_0_PMI_CAP_LIST
+#define BIFPLR2_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_0_PMI_CAP
+#define BIFPLR2_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR2_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR2_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR2_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR2_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR2_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR2_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR2_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR2_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR2_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR2_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR2_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR2_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR2_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR2_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR2_0_PMI_STATUS_CNTL
+#define BIFPLR2_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR2_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR2_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR2_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR2_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR2_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR2_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR2_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR2_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR2_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR2_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR2_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR2_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR2_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR2_0_PCIE_CAP_LIST
+#define BIFPLR2_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_0_PCIE_CAP
+#define BIFPLR2_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR2_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR2_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR2_0_DEVICE_CAP
+#define BIFPLR2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR2_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR2_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR2_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR2_0_DEVICE_CNTL
+#define BIFPLR2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR2_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR2_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR2_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR2_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR2_0_DEVICE_STATUS
+#define BIFPLR2_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR2_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR2_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR2_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR2_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR2_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR2_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR2_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR2_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR2_0_LINK_CAP
+#define BIFPLR2_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR2_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR2_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR2_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR2_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR2_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR2_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR2_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR2_0_LINK_CNTL
+#define BIFPLR2_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR2_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR2_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR2_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR2_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR2_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR2_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR2_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR2_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR2_0_LINK_STATUS
+#define BIFPLR2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR2_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR2_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR2_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR2_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR2_0_SLOT_CAP
+#define BIFPLR2_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR2_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR2_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR2_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR2_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR2_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR2_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR2_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR2_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR2_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR2_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR2_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR2_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR2_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR2_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR2_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR2_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR2_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR2_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR2_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR2_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR2_0_SLOT_CNTL
+#define BIFPLR2_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR2_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR2_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR2_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR2_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR2_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR2_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR2_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR2_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR2_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR2_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR2_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR2_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR2_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR2_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR2_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR2_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR2_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR2_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR2_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR2_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR2_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR2_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR2_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR2_0_SLOT_STATUS
+#define BIFPLR2_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR2_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR2_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR2_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR2_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR2_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR2_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR2_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR2_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR2_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR2_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR2_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR2_0_ROOT_CNTL
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR2_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR2_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR2_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR2_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR2_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR2_0_ROOT_CAP
+#define BIFPLR2_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR2_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR2_0_ROOT_STATUS
+#define BIFPLR2_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR2_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR2_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR2_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR2_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR2_0_DEVICE_CAP2
+#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR2_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR2_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR2_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR2_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR2_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR2_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR2_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR2_0_DEVICE_CNTL2
+#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR2_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR2_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR2_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR2_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR2_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR2_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR2_0_DEVICE_STATUS2
+#define BIFPLR2_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR2_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_0_LINK_CAP2
+#define BIFPLR2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR2_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR2_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR2_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR2_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR2_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR2_0_LINK_CNTL2
+#define BIFPLR2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR2_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR2_0_LINK_STATUS2
+#define BIFPLR2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR2_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR2_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR2_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR2_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR2_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR2_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR2_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR2_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR2_0_SLOT_CAP2
+#define BIFPLR2_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR2_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_0_SLOT_CNTL2
+#define BIFPLR2_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR2_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_0_SLOT_STATUS2
+#define BIFPLR2_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR2_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_0_MSI_CAP_LIST
+#define BIFPLR2_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_0_MSI_MSG_CNTL
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR2_0_MSI_MSG_ADDR_LO
+#define BIFPLR2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR2_0_MSI_MSG_ADDR_HI
+#define BIFPLR2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_0_MSI_MSG_DATA
+#define BIFPLR2_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR2_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR2_0_MSI_MSG_DATA_64
+#define BIFPLR2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR2_0_SSID_CAP_LIST
+#define BIFPLR2_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_0_SSID_CAP
+#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR2_0_MSI_MAP_CAP_LIST
+#define BIFPLR2_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_0_MSI_MAP_CAP
+#define BIFPLR2_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR2_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR2_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR2_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR2_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR2_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR2_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_0_PCIE_PORT_VC_CNTL
+#define BIFPLR2_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR2_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR2_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR2_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR2_0_PCIE_PORT_VC_STATUS
+#define BIFPLR2_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR2_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR2_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR2_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR2_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR2_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR2_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR2_0_PCIE_CORR_ERR_MASK
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR2_0_PCIE_HDR_LOG0
+#define BIFPLR2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_HDR_LOG1
+#define BIFPLR2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_HDR_LOG2
+#define BIFPLR2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_HDR_LOG3
+#define BIFPLR2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR2_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR2_0_PCIE_ERR_SRC_ID
+#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR2_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_LINK_CNTL3
+#define BIFPLR2_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR2_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR2_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_ACS_CAP
+#define BIFPLR2_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR2_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR2_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR2_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR2_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR2_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR2_0_PCIE_ACS_CNTL
+#define BIFPLR2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR2_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR2_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR2_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR2_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR2_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_MC_CAP
+#define BIFPLR2_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR2_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR2_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR2_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR2_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR2_0_PCIE_MC_CNTL
+#define BIFPLR2_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR2_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR2_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR2_0_PCIE_MC_ADDR0
+#define BIFPLR2_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR2_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR2_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR2_0_PCIE_MC_ADDR1
+#define BIFPLR2_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_RCV0
+#define BIFPLR2_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_RCV1
+#define BIFPLR2_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR2_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR2_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR2_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR2_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR2_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_DPC_CAP_LIST
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR2_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR2_0_PCIE_DPC_CNTL
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR2_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR2_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR2_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR2_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR2_0_PCIE_DPC_STATUS
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR2_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR2_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR2_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_STATUS
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_MASK
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_ESM_CAP_LIST
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_ESM_HEADER_1
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_ESM_HEADER_2
+#define BIFPLR2_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR2_0_PCIE_ESM_STATUS
+#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR2_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR2_0_PCIE_ESM_CTRL
+#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR2_0_PCIE_ESM_CAP_1
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_2
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_3
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR2_0_PCIE_ESM_CAP_4
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_5
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_6
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR2_0_PCIE_ESM_CAP_7
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR2_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR2_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR2_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR2_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR2_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR2_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR2_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR2_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR2_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR2_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_LINK_CAP_16GT
+#define BIFPLR2_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR2_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_0_LINK_CNTL_16GT
+#define BIFPLR2_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR2_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_0_LINK_STATUS_16GT
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR2_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR2_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR2_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR2_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR2_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR2_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_MARGINING_PORT_CAP
+#define BIFPLR2_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR2_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR2_0_MARGINING_PORT_STATUS
+#define BIFPLR2_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR2_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR2_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR2_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR2_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_CCIX_HEADER_1
+#define BIFPLR2_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR2_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR2_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR2_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR2_0_PCIE_CCIX_HEADER_2
+#define BIFPLR2_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR2_0_PCIE_CCIX_CAP
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR2_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR2_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR2_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR2_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR2_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR2_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR2_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR2_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR2_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR2_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR2_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR2_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR2_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr3_cfgdecp
+//BIFPLR3_0_VENDOR_ID
+#define BIFPLR3_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR3_0_DEVICE_ID
+#define BIFPLR3_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR3_0_COMMAND
+#define BIFPLR3_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR3_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR3_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR3_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR3_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR3_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR3_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR3_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR3_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR3_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR3_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR3_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR3_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR3_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR3_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR3_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR3_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR3_0_STATUS
+#define BIFPLR3_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR3_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR3_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR3_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR3_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR3_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR3_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR3_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR3_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR3_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR3_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR3_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR3_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR3_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR3_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR3_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR3_0_REVISION_ID
+#define BIFPLR3_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR3_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR3_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR3_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR3_0_PROG_INTERFACE
+#define BIFPLR3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR3_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR3_0_SUB_CLASS
+#define BIFPLR3_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR3_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR3_0_BASE_CLASS
+#define BIFPLR3_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR3_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR3_0_CACHE_LINE
+#define BIFPLR3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR3_0_LATENCY
+#define BIFPLR3_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR3_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR3_0_HEADER
+#define BIFPLR3_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR3_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR3_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR3_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR3_0_BIST
+#define BIFPLR3_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR3_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR3_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR3_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR3_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR3_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR3_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR3_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR3_0_IO_BASE_LIMIT
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR3_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR3_0_SECONDARY_STATUS
+#define BIFPLR3_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR3_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR3_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR3_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR3_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR3_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR3_0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR3_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR3_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR3_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR3_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR3_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR3_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR3_0_MEM_BASE_LIMIT
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR3_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR3_0_PREF_BASE_LIMIT
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR3_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR3_0_PREF_BASE_UPPER
+#define BIFPLR3_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR3_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PREF_LIMIT_UPPER
+#define BIFPLR3_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR3_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR3_0_IO_BASE_LIMIT_HI
+#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR3_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR3_0_CAP_PTR
+#define BIFPLR3_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR3_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR3_0_ROM_BASE_ADDR
+#define BIFPLR3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR3_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_INTERRUPT_LINE
+#define BIFPLR3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR3_0_INTERRUPT_PIN
+#define BIFPLR3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR3_0_IRQ_BRIDGE_CNTL
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR3_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR3_0_EXT_BRIDGE_CNTL
+#define BIFPLR3_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR3_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR3_0_VENDOR_CAP_LIST
+#define BIFPLR3_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR3_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR3_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR3_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR3_0_ADAPTER_ID_W
+#define BIFPLR3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR3_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR3_0_PMI_CAP_LIST
+#define BIFPLR3_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_0_PMI_CAP
+#define BIFPLR3_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR3_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR3_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR3_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR3_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR3_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR3_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR3_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR3_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR3_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR3_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR3_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR3_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR3_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR3_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR3_0_PMI_STATUS_CNTL
+#define BIFPLR3_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR3_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR3_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR3_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR3_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR3_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR3_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR3_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR3_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR3_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR3_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR3_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR3_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR3_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR3_0_PCIE_CAP_LIST
+#define BIFPLR3_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_0_PCIE_CAP
+#define BIFPLR3_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR3_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR3_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR3_0_DEVICE_CAP
+#define BIFPLR3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR3_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR3_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR3_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR3_0_DEVICE_CNTL
+#define BIFPLR3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR3_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR3_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR3_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR3_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR3_0_DEVICE_STATUS
+#define BIFPLR3_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR3_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR3_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR3_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR3_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR3_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR3_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR3_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR3_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR3_0_LINK_CAP
+#define BIFPLR3_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR3_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR3_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR3_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR3_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR3_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR3_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR3_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR3_0_LINK_CNTL
+#define BIFPLR3_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR3_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR3_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR3_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR3_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR3_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR3_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR3_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR3_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR3_0_LINK_STATUS
+#define BIFPLR3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR3_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR3_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR3_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR3_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR3_0_SLOT_CAP
+#define BIFPLR3_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR3_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR3_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR3_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR3_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR3_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR3_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR3_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR3_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR3_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR3_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR3_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR3_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR3_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR3_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR3_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR3_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR3_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR3_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR3_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR3_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR3_0_SLOT_CNTL
+#define BIFPLR3_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR3_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR3_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR3_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR3_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR3_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR3_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR3_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR3_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR3_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR3_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR3_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR3_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR3_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR3_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR3_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR3_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR3_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR3_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR3_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR3_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR3_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR3_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR3_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR3_0_SLOT_STATUS
+#define BIFPLR3_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR3_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR3_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR3_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR3_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR3_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR3_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR3_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR3_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR3_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR3_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR3_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR3_0_ROOT_CNTL
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR3_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR3_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR3_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR3_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR3_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR3_0_ROOT_CAP
+#define BIFPLR3_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR3_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR3_0_ROOT_STATUS
+#define BIFPLR3_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR3_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR3_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR3_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR3_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR3_0_DEVICE_CAP2
+#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR3_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR3_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR3_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR3_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR3_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR3_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR3_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR3_0_DEVICE_CNTL2
+#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR3_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR3_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR3_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR3_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR3_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR3_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR3_0_DEVICE_STATUS2
+#define BIFPLR3_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR3_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_0_LINK_CAP2
+#define BIFPLR3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR3_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR3_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR3_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR3_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR3_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR3_0_LINK_CNTL2
+#define BIFPLR3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR3_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR3_0_LINK_STATUS2
+#define BIFPLR3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR3_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR3_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR3_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR3_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR3_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR3_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR3_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR3_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR3_0_SLOT_CAP2
+#define BIFPLR3_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR3_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_0_SLOT_CNTL2
+#define BIFPLR3_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR3_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_0_SLOT_STATUS2
+#define BIFPLR3_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR3_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_0_MSI_CAP_LIST
+#define BIFPLR3_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_0_MSI_MSG_CNTL
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR3_0_MSI_MSG_ADDR_LO
+#define BIFPLR3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR3_0_MSI_MSG_ADDR_HI
+#define BIFPLR3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_0_MSI_MSG_DATA
+#define BIFPLR3_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR3_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR3_0_MSI_MSG_DATA_64
+#define BIFPLR3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR3_0_SSID_CAP_LIST
+#define BIFPLR3_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_0_SSID_CAP
+#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR3_0_MSI_MAP_CAP_LIST
+#define BIFPLR3_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_0_MSI_MAP_CAP
+#define BIFPLR3_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR3_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR3_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR3_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR3_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR3_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR3_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_0_PCIE_PORT_VC_CNTL
+#define BIFPLR3_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR3_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR3_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR3_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR3_0_PCIE_PORT_VC_STATUS
+#define BIFPLR3_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR3_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR3_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR3_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR3_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR3_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR3_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR3_0_PCIE_CORR_ERR_MASK
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR3_0_PCIE_HDR_LOG0
+#define BIFPLR3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_HDR_LOG1
+#define BIFPLR3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_HDR_LOG2
+#define BIFPLR3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_HDR_LOG3
+#define BIFPLR3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR3_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR3_0_PCIE_ERR_SRC_ID
+#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR3_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_LINK_CNTL3
+#define BIFPLR3_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR3_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR3_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_ACS_CAP
+#define BIFPLR3_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR3_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR3_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR3_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR3_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR3_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR3_0_PCIE_ACS_CNTL
+#define BIFPLR3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR3_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR3_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR3_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR3_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR3_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_MC_CAP
+#define BIFPLR3_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR3_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR3_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR3_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR3_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR3_0_PCIE_MC_CNTL
+#define BIFPLR3_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR3_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR3_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR3_0_PCIE_MC_ADDR0
+#define BIFPLR3_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR3_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR3_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR3_0_PCIE_MC_ADDR1
+#define BIFPLR3_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_RCV0
+#define BIFPLR3_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_RCV1
+#define BIFPLR3_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR3_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR3_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR3_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR3_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR3_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_DPC_CAP_LIST
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR3_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR3_0_PCIE_DPC_CNTL
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR3_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR3_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR3_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR3_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR3_0_PCIE_DPC_STATUS
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR3_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR3_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR3_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_STATUS
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_MASK
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_ESM_CAP_LIST
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_ESM_HEADER_1
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_ESM_HEADER_2
+#define BIFPLR3_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR3_0_PCIE_ESM_STATUS
+#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR3_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR3_0_PCIE_ESM_CTRL
+#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR3_0_PCIE_ESM_CAP_1
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_2
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_3
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR3_0_PCIE_ESM_CAP_4
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_5
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_6
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR3_0_PCIE_ESM_CAP_7
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR3_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR3_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR3_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR3_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR3_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR3_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR3_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR3_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR3_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR3_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_LINK_CAP_16GT
+#define BIFPLR3_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR3_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_0_LINK_CNTL_16GT
+#define BIFPLR3_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR3_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_0_LINK_STATUS_16GT
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR3_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR3_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR3_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR3_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR3_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR3_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_MARGINING_PORT_CAP
+#define BIFPLR3_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR3_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR3_0_MARGINING_PORT_STATUS
+#define BIFPLR3_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR3_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR3_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR3_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR3_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_CCIX_HEADER_1
+#define BIFPLR3_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR3_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR3_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR3_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR3_0_PCIE_CCIX_HEADER_2
+#define BIFPLR3_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR3_0_PCIE_CCIX_CAP
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR3_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR3_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR3_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR3_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR3_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR3_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR3_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR3_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR3_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR3_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR3_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR3_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR3_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr4_cfgdecp
+//BIFPLR4_0_VENDOR_ID
+#define BIFPLR4_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR4_0_DEVICE_ID
+#define BIFPLR4_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR4_0_COMMAND
+#define BIFPLR4_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR4_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR4_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR4_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR4_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR4_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR4_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR4_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR4_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR4_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR4_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR4_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR4_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR4_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR4_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR4_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR4_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR4_0_STATUS
+#define BIFPLR4_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR4_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR4_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR4_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR4_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR4_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR4_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR4_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR4_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR4_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR4_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR4_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR4_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR4_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR4_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR4_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR4_0_REVISION_ID
+#define BIFPLR4_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR4_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR4_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR4_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR4_0_PROG_INTERFACE
+#define BIFPLR4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR4_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR4_0_SUB_CLASS
+#define BIFPLR4_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR4_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR4_0_BASE_CLASS
+#define BIFPLR4_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR4_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR4_0_CACHE_LINE
+#define BIFPLR4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR4_0_LATENCY
+#define BIFPLR4_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR4_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR4_0_HEADER
+#define BIFPLR4_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR4_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR4_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR4_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR4_0_BIST
+#define BIFPLR4_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR4_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR4_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR4_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR4_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR4_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR4_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR4_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR4_0_IO_BASE_LIMIT
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR4_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR4_0_SECONDARY_STATUS
+#define BIFPLR4_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR4_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR4_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR4_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR4_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR4_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR4_0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR4_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR4_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR4_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR4_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR4_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR4_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR4_0_MEM_BASE_LIMIT
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR4_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR4_0_PREF_BASE_LIMIT
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR4_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR4_0_PREF_BASE_UPPER
+#define BIFPLR4_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR4_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PREF_LIMIT_UPPER
+#define BIFPLR4_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR4_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR4_0_IO_BASE_LIMIT_HI
+#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR4_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR4_0_CAP_PTR
+#define BIFPLR4_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR4_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR4_0_ROM_BASE_ADDR
+#define BIFPLR4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR4_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_INTERRUPT_LINE
+#define BIFPLR4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR4_0_INTERRUPT_PIN
+#define BIFPLR4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR4_0_IRQ_BRIDGE_CNTL
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR4_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR4_0_EXT_BRIDGE_CNTL
+#define BIFPLR4_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR4_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR4_0_VENDOR_CAP_LIST
+#define BIFPLR4_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR4_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR4_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR4_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR4_0_ADAPTER_ID_W
+#define BIFPLR4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR4_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR4_0_PMI_CAP_LIST
+#define BIFPLR4_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_0_PMI_CAP
+#define BIFPLR4_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR4_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR4_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR4_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR4_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR4_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR4_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR4_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR4_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR4_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR4_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR4_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR4_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR4_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR4_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR4_0_PMI_STATUS_CNTL
+#define BIFPLR4_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR4_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR4_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR4_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR4_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR4_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR4_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR4_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR4_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR4_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR4_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR4_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR4_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR4_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR4_0_PCIE_CAP_LIST
+#define BIFPLR4_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_0_PCIE_CAP
+#define BIFPLR4_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR4_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR4_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR4_0_DEVICE_CAP
+#define BIFPLR4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR4_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR4_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR4_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR4_0_DEVICE_CNTL
+#define BIFPLR4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR4_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR4_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR4_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR4_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR4_0_DEVICE_STATUS
+#define BIFPLR4_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR4_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR4_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR4_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR4_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR4_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR4_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR4_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR4_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR4_0_LINK_CAP
+#define BIFPLR4_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR4_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR4_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR4_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR4_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR4_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR4_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR4_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR4_0_LINK_CNTL
+#define BIFPLR4_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR4_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR4_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR4_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR4_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR4_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR4_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR4_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR4_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR4_0_LINK_STATUS
+#define BIFPLR4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR4_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR4_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR4_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR4_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR4_0_SLOT_CAP
+#define BIFPLR4_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR4_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR4_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR4_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR4_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR4_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR4_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR4_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR4_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR4_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR4_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR4_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR4_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR4_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR4_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR4_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR4_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR4_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR4_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR4_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR4_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR4_0_SLOT_CNTL
+#define BIFPLR4_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR4_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR4_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR4_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR4_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR4_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR4_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR4_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR4_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR4_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR4_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR4_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR4_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR4_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR4_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR4_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR4_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR4_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR4_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR4_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR4_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR4_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR4_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR4_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR4_0_SLOT_STATUS
+#define BIFPLR4_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR4_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR4_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR4_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR4_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR4_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR4_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR4_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR4_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR4_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR4_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR4_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR4_0_ROOT_CNTL
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR4_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR4_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR4_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR4_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR4_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR4_0_ROOT_CAP
+#define BIFPLR4_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR4_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR4_0_ROOT_STATUS
+#define BIFPLR4_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR4_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR4_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR4_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR4_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR4_0_DEVICE_CAP2
+#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR4_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR4_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR4_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR4_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR4_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR4_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR4_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR4_0_DEVICE_CNTL2
+#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR4_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR4_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR4_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR4_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR4_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR4_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR4_0_DEVICE_STATUS2
+#define BIFPLR4_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR4_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_0_LINK_CAP2
+#define BIFPLR4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR4_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR4_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR4_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR4_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR4_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR4_0_LINK_CNTL2
+#define BIFPLR4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR4_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR4_0_LINK_STATUS2
+#define BIFPLR4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR4_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR4_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR4_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR4_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR4_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR4_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR4_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR4_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR4_0_SLOT_CAP2
+#define BIFPLR4_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR4_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_0_SLOT_CNTL2
+#define BIFPLR4_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR4_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_0_SLOT_STATUS2
+#define BIFPLR4_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR4_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_0_MSI_CAP_LIST
+#define BIFPLR4_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_0_MSI_MSG_CNTL
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR4_0_MSI_MSG_ADDR_LO
+#define BIFPLR4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR4_0_MSI_MSG_ADDR_HI
+#define BIFPLR4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_0_MSI_MSG_DATA
+#define BIFPLR4_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR4_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR4_0_MSI_MSG_DATA_64
+#define BIFPLR4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR4_0_SSID_CAP_LIST
+#define BIFPLR4_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_0_SSID_CAP
+#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR4_0_MSI_MAP_CAP_LIST
+#define BIFPLR4_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_0_MSI_MAP_CAP
+#define BIFPLR4_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR4_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR4_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR4_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR4_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR4_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR4_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_0_PCIE_PORT_VC_CNTL
+#define BIFPLR4_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR4_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR4_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR4_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR4_0_PCIE_PORT_VC_STATUS
+#define BIFPLR4_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR4_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR4_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR4_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR4_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR4_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR4_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR4_0_PCIE_CORR_ERR_MASK
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR4_0_PCIE_HDR_LOG0
+#define BIFPLR4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_HDR_LOG1
+#define BIFPLR4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_HDR_LOG2
+#define BIFPLR4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_HDR_LOG3
+#define BIFPLR4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR4_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR4_0_PCIE_ERR_SRC_ID
+#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR4_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_LINK_CNTL3
+#define BIFPLR4_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR4_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR4_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_ACS_CAP
+#define BIFPLR4_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR4_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR4_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR4_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR4_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR4_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR4_0_PCIE_ACS_CNTL
+#define BIFPLR4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR4_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR4_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR4_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR4_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR4_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_MC_CAP
+#define BIFPLR4_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR4_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR4_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR4_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR4_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR4_0_PCIE_MC_CNTL
+#define BIFPLR4_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR4_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR4_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR4_0_PCIE_MC_ADDR0
+#define BIFPLR4_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR4_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR4_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR4_0_PCIE_MC_ADDR1
+#define BIFPLR4_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_RCV0
+#define BIFPLR4_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_RCV1
+#define BIFPLR4_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR4_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR4_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR4_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR4_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR4_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_DPC_CAP_LIST
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR4_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR4_0_PCIE_DPC_CNTL
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR4_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR4_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR4_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR4_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR4_0_PCIE_DPC_STATUS
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR4_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR4_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR4_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_STATUS
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_MASK
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_ESM_CAP_LIST
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_ESM_HEADER_1
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_ESM_HEADER_2
+#define BIFPLR4_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR4_0_PCIE_ESM_STATUS
+#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR4_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR4_0_PCIE_ESM_CTRL
+#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR4_0_PCIE_ESM_CAP_1
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_2
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_3
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR4_0_PCIE_ESM_CAP_4
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_5
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_6
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR4_0_PCIE_ESM_CAP_7
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR4_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR4_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR4_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR4_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR4_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR4_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR4_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR4_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR4_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR4_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_LINK_CAP_16GT
+#define BIFPLR4_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR4_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_0_LINK_CNTL_16GT
+#define BIFPLR4_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR4_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_0_LINK_STATUS_16GT
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR4_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR4_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR4_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR4_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR4_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR4_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_MARGINING_PORT_CAP
+#define BIFPLR4_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR4_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR4_0_MARGINING_PORT_STATUS
+#define BIFPLR4_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR4_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR4_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR4_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR4_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_CCIX_HEADER_1
+#define BIFPLR4_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR4_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR4_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR4_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR4_0_PCIE_CCIX_HEADER_2
+#define BIFPLR4_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR4_0_PCIE_CCIX_CAP
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR4_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR4_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR4_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR4_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR4_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR4_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR4_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR4_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR4_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR4_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR4_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR4_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR4_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr5_cfgdecp
+//BIFPLR5_0_VENDOR_ID
+#define BIFPLR5_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR5_0_DEVICE_ID
+#define BIFPLR5_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR5_0_COMMAND
+#define BIFPLR5_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR5_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR5_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR5_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR5_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR5_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR5_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR5_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR5_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR5_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR5_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR5_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR5_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR5_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR5_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR5_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR5_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR5_0_STATUS
+#define BIFPLR5_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR5_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR5_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR5_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR5_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR5_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR5_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR5_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR5_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR5_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR5_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR5_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR5_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR5_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR5_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR5_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR5_0_REVISION_ID
+#define BIFPLR5_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR5_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR5_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR5_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR5_0_PROG_INTERFACE
+#define BIFPLR5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR5_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR5_0_SUB_CLASS
+#define BIFPLR5_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR5_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR5_0_BASE_CLASS
+#define BIFPLR5_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR5_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR5_0_CACHE_LINE
+#define BIFPLR5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR5_0_LATENCY
+#define BIFPLR5_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR5_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR5_0_HEADER
+#define BIFPLR5_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR5_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR5_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR5_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR5_0_BIST
+#define BIFPLR5_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR5_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR5_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR5_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR5_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR5_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR5_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR5_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR5_0_IO_BASE_LIMIT
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR5_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR5_0_SECONDARY_STATUS
+#define BIFPLR5_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR5_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR5_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR5_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR5_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR5_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR5_0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR5_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR5_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR5_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR5_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR5_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR5_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR5_0_MEM_BASE_LIMIT
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR5_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR5_0_PREF_BASE_LIMIT
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR5_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR5_0_PREF_BASE_UPPER
+#define BIFPLR5_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR5_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PREF_LIMIT_UPPER
+#define BIFPLR5_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR5_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR5_0_IO_BASE_LIMIT_HI
+#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR5_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR5_0_CAP_PTR
+#define BIFPLR5_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR5_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR5_0_ROM_BASE_ADDR
+#define BIFPLR5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR5_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_INTERRUPT_LINE
+#define BIFPLR5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR5_0_INTERRUPT_PIN
+#define BIFPLR5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR5_0_IRQ_BRIDGE_CNTL
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR5_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR5_0_EXT_BRIDGE_CNTL
+#define BIFPLR5_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR5_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR5_0_VENDOR_CAP_LIST
+#define BIFPLR5_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR5_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR5_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR5_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR5_0_ADAPTER_ID_W
+#define BIFPLR5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR5_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR5_0_PMI_CAP_LIST
+#define BIFPLR5_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_0_PMI_CAP
+#define BIFPLR5_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR5_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR5_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR5_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR5_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR5_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR5_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR5_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR5_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR5_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR5_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR5_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR5_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR5_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR5_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR5_0_PMI_STATUS_CNTL
+#define BIFPLR5_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR5_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR5_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR5_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR5_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR5_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR5_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR5_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR5_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR5_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR5_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR5_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR5_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR5_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR5_0_PCIE_CAP_LIST
+#define BIFPLR5_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_0_PCIE_CAP
+#define BIFPLR5_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR5_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR5_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR5_0_DEVICE_CAP
+#define BIFPLR5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR5_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR5_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR5_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR5_0_DEVICE_CNTL
+#define BIFPLR5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR5_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR5_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR5_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR5_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR5_0_DEVICE_STATUS
+#define BIFPLR5_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR5_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR5_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR5_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR5_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR5_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR5_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR5_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR5_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR5_0_LINK_CAP
+#define BIFPLR5_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR5_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR5_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR5_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR5_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR5_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR5_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR5_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR5_0_LINK_CNTL
+#define BIFPLR5_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR5_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR5_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR5_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR5_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR5_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR5_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR5_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR5_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR5_0_LINK_STATUS
+#define BIFPLR5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR5_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR5_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR5_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR5_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR5_0_SLOT_CAP
+#define BIFPLR5_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR5_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR5_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR5_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR5_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR5_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR5_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR5_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR5_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR5_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR5_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR5_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR5_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR5_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR5_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR5_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR5_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR5_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR5_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR5_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR5_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR5_0_SLOT_CNTL
+#define BIFPLR5_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR5_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR5_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR5_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR5_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR5_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR5_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR5_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR5_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR5_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR5_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR5_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR5_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR5_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR5_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR5_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR5_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR5_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR5_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR5_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR5_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR5_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR5_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR5_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR5_0_SLOT_STATUS
+#define BIFPLR5_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR5_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR5_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR5_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR5_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR5_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR5_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR5_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR5_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR5_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR5_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR5_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR5_0_ROOT_CNTL
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR5_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR5_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR5_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR5_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR5_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR5_0_ROOT_CAP
+#define BIFPLR5_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR5_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR5_0_ROOT_STATUS
+#define BIFPLR5_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR5_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR5_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR5_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR5_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR5_0_DEVICE_CAP2
+#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR5_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR5_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR5_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR5_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR5_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR5_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR5_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR5_0_DEVICE_CNTL2
+#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR5_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR5_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR5_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR5_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR5_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR5_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR5_0_DEVICE_STATUS2
+#define BIFPLR5_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR5_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_0_LINK_CAP2
+#define BIFPLR5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR5_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR5_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR5_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR5_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR5_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR5_0_LINK_CNTL2
+#define BIFPLR5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR5_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR5_0_LINK_STATUS2
+#define BIFPLR5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR5_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR5_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR5_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR5_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR5_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR5_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR5_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR5_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR5_0_SLOT_CAP2
+#define BIFPLR5_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR5_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_0_SLOT_CNTL2
+#define BIFPLR5_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR5_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_0_SLOT_STATUS2
+#define BIFPLR5_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR5_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_0_MSI_CAP_LIST
+#define BIFPLR5_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_0_MSI_MSG_CNTL
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR5_0_MSI_MSG_ADDR_LO
+#define BIFPLR5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR5_0_MSI_MSG_ADDR_HI
+#define BIFPLR5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_0_MSI_MSG_DATA
+#define BIFPLR5_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR5_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR5_0_MSI_MSG_DATA_64
+#define BIFPLR5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR5_0_SSID_CAP_LIST
+#define BIFPLR5_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_0_SSID_CAP
+#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR5_0_MSI_MAP_CAP_LIST
+#define BIFPLR5_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_0_MSI_MAP_CAP
+#define BIFPLR5_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR5_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR5_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR5_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR5_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR5_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR5_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_0_PCIE_PORT_VC_CNTL
+#define BIFPLR5_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR5_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR5_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR5_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR5_0_PCIE_PORT_VC_STATUS
+#define BIFPLR5_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR5_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR5_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR5_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR5_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR5_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR5_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR5_0_PCIE_CORR_ERR_MASK
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR5_0_PCIE_HDR_LOG0
+#define BIFPLR5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_HDR_LOG1
+#define BIFPLR5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_HDR_LOG2
+#define BIFPLR5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_HDR_LOG3
+#define BIFPLR5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR5_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR5_0_PCIE_ERR_SRC_ID
+#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR5_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_LINK_CNTL3
+#define BIFPLR5_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR5_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR5_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_ACS_CAP
+#define BIFPLR5_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR5_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR5_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR5_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR5_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR5_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR5_0_PCIE_ACS_CNTL
+#define BIFPLR5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR5_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR5_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR5_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR5_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR5_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_MC_CAP
+#define BIFPLR5_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR5_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR5_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR5_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR5_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR5_0_PCIE_MC_CNTL
+#define BIFPLR5_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR5_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR5_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR5_0_PCIE_MC_ADDR0
+#define BIFPLR5_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR5_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR5_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR5_0_PCIE_MC_ADDR1
+#define BIFPLR5_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_RCV0
+#define BIFPLR5_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_RCV1
+#define BIFPLR5_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR5_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR5_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR5_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR5_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR5_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_DPC_CAP_LIST
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR5_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR5_0_PCIE_DPC_CNTL
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR5_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR5_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR5_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR5_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR5_0_PCIE_DPC_STATUS
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR5_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR5_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR5_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_STATUS
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_MASK
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_ESM_CAP_LIST
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_ESM_HEADER_1
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_ESM_HEADER_2
+#define BIFPLR5_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR5_0_PCIE_ESM_STATUS
+#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR5_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR5_0_PCIE_ESM_CTRL
+#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR5_0_PCIE_ESM_CAP_1
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_2
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_3
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR5_0_PCIE_ESM_CAP_4
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_5
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_6
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR5_0_PCIE_ESM_CAP_7
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR5_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR5_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR5_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR5_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR5_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR5_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR5_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR5_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR5_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR5_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_LINK_CAP_16GT
+#define BIFPLR5_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR5_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_0_LINK_CNTL_16GT
+#define BIFPLR5_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR5_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_0_LINK_STATUS_16GT
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR5_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR5_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR5_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR5_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR5_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR5_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_MARGINING_PORT_CAP
+#define BIFPLR5_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR5_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR5_0_MARGINING_PORT_STATUS
+#define BIFPLR5_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR5_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR5_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR5_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR5_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_CCIX_HEADER_1
+#define BIFPLR5_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR5_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR5_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR5_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR5_0_PCIE_CCIX_HEADER_2
+#define BIFPLR5_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR5_0_PCIE_CCIX_CAP
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR5_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR5_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR5_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR5_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR5_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR5_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR5_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR5_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR5_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR5_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR5_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR5_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR5_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr6_cfgdecp
+//BIFPLR6_0_VENDOR_ID
+#define BIFPLR6_0_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_0_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR6_0_DEVICE_ID
+#define BIFPLR6_0_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR6_0_COMMAND
+#define BIFPLR6_0_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR6_0_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR6_0_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR6_0_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR6_0_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR6_0_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR6_0_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR6_0_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR6_0_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR6_0_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR6_0_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR6_0_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR6_0_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR6_0_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR6_0_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR6_0_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR6_0_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR6_0_STATUS
+#define BIFPLR6_0_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR6_0_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR6_0_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR6_0_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR6_0_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR6_0_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR6_0_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR6_0_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR6_0_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR6_0_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR6_0_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR6_0_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR6_0_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR6_0_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR6_0_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR6_0_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR6_0_REVISION_ID
+#define BIFPLR6_0_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR6_0_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR6_0_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR6_0_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR6_0_PROG_INTERFACE
+#define BIFPLR6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR6_0_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR6_0_SUB_CLASS
+#define BIFPLR6_0_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR6_0_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR6_0_BASE_CLASS
+#define BIFPLR6_0_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR6_0_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR6_0_CACHE_LINE
+#define BIFPLR6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR6_0_LATENCY
+#define BIFPLR6_0_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR6_0_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR6_0_HEADER
+#define BIFPLR6_0_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR6_0_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR6_0_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR6_0_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR6_0_BIST
+#define BIFPLR6_0_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR6_0_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR6_0_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR6_0_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR6_0_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR6_0_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR6_0_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR6_0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR6_0_IO_BASE_LIMIT
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR6_0_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR6_0_SECONDARY_STATUS
+#define BIFPLR6_0_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR6_0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR6_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR6_0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR6_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR6_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR6_0_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR6_0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR6_0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR6_0_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR6_0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR6_0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR6_0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR6_0_MEM_BASE_LIMIT
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR6_0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR6_0_PREF_BASE_LIMIT
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR6_0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR6_0_PREF_BASE_UPPER
+#define BIFPLR6_0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR6_0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PREF_LIMIT_UPPER
+#define BIFPLR6_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR6_0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR6_0_IO_BASE_LIMIT_HI
+#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR6_0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR6_0_CAP_PTR
+#define BIFPLR6_0_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR6_0_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR6_0_ROM_BASE_ADDR
+#define BIFPLR6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR6_0_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_INTERRUPT_LINE
+#define BIFPLR6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR6_0_INTERRUPT_PIN
+#define BIFPLR6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR6_0_IRQ_BRIDGE_CNTL
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR6_0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR6_0_EXT_BRIDGE_CNTL
+#define BIFPLR6_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR6_0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR6_0_VENDOR_CAP_LIST
+#define BIFPLR6_0_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_0_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR6_0_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR6_0_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR6_0_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR6_0_ADAPTER_ID_W
+#define BIFPLR6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR6_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR6_0_PMI_CAP_LIST
+#define BIFPLR6_0_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_0_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_0_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_0_PMI_CAP
+#define BIFPLR6_0_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR6_0_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR6_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR6_0_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR6_0_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR6_0_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR6_0_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR6_0_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR6_0_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR6_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR6_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR6_0_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR6_0_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR6_0_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR6_0_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR6_0_PMI_STATUS_CNTL
+#define BIFPLR6_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR6_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR6_0_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR6_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR6_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR6_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR6_0_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR6_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR6_0_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR6_0_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR6_0_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR6_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR6_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR6_0_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR6_0_PCIE_CAP_LIST
+#define BIFPLR6_0_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_0_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_0_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_0_PCIE_CAP
+#define BIFPLR6_0_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR6_0_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR6_0_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR6_0_DEVICE_CAP
+#define BIFPLR6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR6_0_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR6_0_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR6_0_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR6_0_DEVICE_CNTL
+#define BIFPLR6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR6_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR6_0_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR6_0_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR6_0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR6_0_DEVICE_STATUS
+#define BIFPLR6_0_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR6_0_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR6_0_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR6_0_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR6_0_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR6_0_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR6_0_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR6_0_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR6_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR6_0_LINK_CAP
+#define BIFPLR6_0_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_0_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR6_0_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR6_0_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR6_0_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR6_0_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR6_0_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR6_0_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR6_0_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR6_0_LINK_CNTL
+#define BIFPLR6_0_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR6_0_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR6_0_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR6_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR6_0_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR6_0_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR6_0_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR6_0_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR6_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR6_0_LINK_STATUS
+#define BIFPLR6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR6_0_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR6_0_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR6_0_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR6_0_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR6_0_SLOT_CAP
+#define BIFPLR6_0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR6_0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR6_0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR6_0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR6_0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR6_0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR6_0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR6_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR6_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR6_0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR6_0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR6_0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR6_0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR6_0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR6_0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR6_0_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR6_0_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR6_0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR6_0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR6_0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR6_0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR6_0_SLOT_CNTL
+#define BIFPLR6_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR6_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR6_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR6_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR6_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR6_0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR6_0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR6_0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR6_0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR6_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR6_0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR6_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR6_0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR6_0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR6_0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR6_0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR6_0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR6_0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR6_0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR6_0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR6_0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR6_0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR6_0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR6_0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR6_0_SLOT_STATUS
+#define BIFPLR6_0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR6_0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR6_0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR6_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR6_0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR6_0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR6_0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR6_0_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR6_0_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR6_0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR6_0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR6_0_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR6_0_ROOT_CNTL
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR6_0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR6_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR6_0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR6_0_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR6_0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR6_0_ROOT_CAP
+#define BIFPLR6_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR6_0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR6_0_ROOT_STATUS
+#define BIFPLR6_0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR6_0_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR6_0_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR6_0_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR6_0_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR6_0_DEVICE_CAP2
+#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR6_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR6_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR6_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR6_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR6_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR6_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR6_0_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR6_0_DEVICE_CNTL2
+#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR6_0_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR6_0_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR6_0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR6_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR6_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR6_0_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR6_0_DEVICE_STATUS2
+#define BIFPLR6_0_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR6_0_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_0_LINK_CAP2
+#define BIFPLR6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR6_0_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR6_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR6_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR6_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR6_0_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR6_0_LINK_CNTL2
+#define BIFPLR6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR6_0_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR6_0_LINK_STATUS2
+#define BIFPLR6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR6_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR6_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR6_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR6_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR6_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR6_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR6_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR6_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR6_0_SLOT_CAP2
+#define BIFPLR6_0_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR6_0_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_0_SLOT_CNTL2
+#define BIFPLR6_0_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR6_0_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_0_SLOT_STATUS2
+#define BIFPLR6_0_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR6_0_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_0_MSI_CAP_LIST
+#define BIFPLR6_0_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_0_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_0_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_0_MSI_MSG_CNTL
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR6_0_MSI_MSG_ADDR_LO
+#define BIFPLR6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR6_0_MSI_MSG_ADDR_HI
+#define BIFPLR6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_0_MSI_MSG_DATA
+#define BIFPLR6_0_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR6_0_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR6_0_MSI_MSG_DATA_64
+#define BIFPLR6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR6_0_SSID_CAP_LIST
+#define BIFPLR6_0_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_0_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_0_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_0_SSID_CAP
+#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR6_0_MSI_MAP_CAP_LIST
+#define BIFPLR6_0_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_0_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_0_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_0_MSI_MAP_CAP
+#define BIFPLR6_0_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR6_0_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR6_0_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR6_0_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR6_0_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR6_0_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR6_0_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_0_PCIE_PORT_VC_CNTL
+#define BIFPLR6_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR6_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR6_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR6_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR6_0_PCIE_PORT_VC_STATUS
+#define BIFPLR6_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR6_0_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR6_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR6_0_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR6_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR6_0_PCIE_UNCORR_ERR_MASK
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR6_0_PCIE_CORR_ERR_STATUS
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR6_0_PCIE_CORR_ERR_MASK
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR6_0_PCIE_HDR_LOG0
+#define BIFPLR6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_HDR_LOG1
+#define BIFPLR6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_HDR_LOG2
+#define BIFPLR6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_HDR_LOG3
+#define BIFPLR6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_ROOT_ERR_CMD
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR6_0_PCIE_ROOT_ERR_STATUS
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR6_0_PCIE_ERR_SRC_ID
+#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR6_0_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_LINK_CNTL3
+#define BIFPLR6_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR6_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR6_0_PCIE_LANE_ERROR_STATUS
+#define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_ACS_CAP
+#define BIFPLR6_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR6_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR6_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR6_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR6_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR6_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR6_0_PCIE_ACS_CNTL
+#define BIFPLR6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR6_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR6_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR6_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR6_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR6_0_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_MC_CAP
+#define BIFPLR6_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR6_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR6_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR6_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR6_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR6_0_PCIE_MC_CNTL
+#define BIFPLR6_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR6_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR6_0_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR6_0_PCIE_MC_ADDR0
+#define BIFPLR6_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR6_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR6_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR6_0_PCIE_MC_ADDR1
+#define BIFPLR6_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_RCV0
+#define BIFPLR6_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_RCV1
+#define BIFPLR6_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_BLOCK_ALL0
+#define BIFPLR6_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_BLOCK_ALL1
+#define BIFPLR6_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR6_0_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_L1_PM_SUB_CAP
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR6_0_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR6_0_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_DPC_CAP_LIST
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR6_0_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR6_0_PCIE_DPC_CNTL
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR6_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR6_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR6_0_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR6_0_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR6_0_PCIE_DPC_STATUS
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR6_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR6_0_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR6_0_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_STATUS
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_MASK
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_SEVERITY
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_SYSERROR
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_ESM_CAP_LIST
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_ESM_HEADER_1
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_ESM_HEADER_2
+#define BIFPLR6_0_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR6_0_PCIE_ESM_STATUS
+#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR6_0_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR6_0_PCIE_ESM_CTRL
+#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR6_0_PCIE_ESM_CAP_1
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_2
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_3
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR6_0_PCIE_ESM_CAP_4
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_5
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_6
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR6_0_PCIE_ESM_CAP_7
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR6_0_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_DATA_LINK_FEATURE_CAP
+#define BIFPLR6_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR6_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR6_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR6_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR6_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR6_0_DATA_LINK_FEATURE_STATUS
+#define BIFPLR6_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR6_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR6_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_LINK_CAP_16GT
+#define BIFPLR6_0_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR6_0_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_0_LINK_CNTL_16GT
+#define BIFPLR6_0_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR6_0_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_0_LINK_STATUS_16GT
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR6_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR6_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR6_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR6_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR6_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR6_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_MARGINING_PORT_CAP
+#define BIFPLR6_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR6_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR6_0_MARGINING_PORT_STATUS
+#define BIFPLR6_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR6_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR6_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR6_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_0_PCIE_CCIX_CAP_LIST
+#define BIFPLR6_0_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_0_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_0_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_CCIX_HEADER_1
+#define BIFPLR6_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR6_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR6_0_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_0_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR6_0_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR6_0_PCIE_CCIX_HEADER_2
+#define BIFPLR6_0_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR6_0_PCIE_CCIX_CAP
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR6_0_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR6_0_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR6_0_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR6_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_0_PCIE_CCIX_ESM_STATUS
+#define BIFPLR6_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR6_0_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR6_0_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR6_0_PCIE_CCIX_ESM_CNTL
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR6_0_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_0_PCIE_CCIX_TRANS_CAP
+#define BIFPLR6_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR6_0_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR6_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR6_0_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp0_pciedir_p
+//BIFP0_PCIEP_RESERVED
+#define BIFP0_PCIEP_RESERVED__RESERVED__SHIFT 0x0
+#define BIFP0_PCIEP_RESERVED__RESERVED_MASK 0xFFFFFFFFL
+//BIFP0_PCIEP_SCRATCH
+#define BIFP0_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP0_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP0_PCIEP_PORT_CNTL
+#define BIFP0_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP0_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP0_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP0_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP0_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP0_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP0_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP0_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x1a
+#define BIFP0_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP0_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP0_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP0_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP0_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP0_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x0003FF00L
+#define BIFP0_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP0_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+#define BIFP0_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x0C000000L
+//BIFP0_PCIE_TX_CNTL
+#define BIFP0_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP0_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP0_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP0_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP0_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP0_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP0_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP0_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP0_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT 0x1b
+#define BIFP0_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP0_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP0_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP0_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP0_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP0_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP0_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP0_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+#define BIFP0_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK 0x08000000L
+//BIFP0_PCIE_TX_REQUESTER_ID
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP0_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP0_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT 0x18
+#define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP0_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK 0x01000000L
+//BIFP0_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP0_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP0_PCIE_TX_SEQ
+#define BIFP0_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP0_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP0_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP0_PCIE_TX_REPLAY
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT 0xe
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK 0x00004000L
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP0_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP0_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP0_PCIE_TX_NOP_DLLP
+#define BIFP0_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT 0x0
+#define BIFP0_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT 0x18
+#define BIFP0_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK 0x00FFFFFFL
+#define BIFP0_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK 0x01000000L
+//BIFP0_PCIE_TX_CNTL_2
+//BIFP0_PCIE_TX_SKID_CTRL
+#define BIFP0_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT 0x0
+#define BIFP0_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT 0x4
+#define BIFP0_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK 0x0000000FL
+#define BIFP0_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK 0x00000010L
+//BIFP0_PCIE_TX_CREDITS_ADVT_P
+#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00003FFFL
+#define BIFP0_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x03FF0000L
+//BIFP0_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00003FFFL
+#define BIFP0_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x03FF0000L
+//BIFP0_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00003FFFL
+#define BIFP0_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x03FF0000L
+//BIFP0_PCIE_TX_CREDITS_INIT_P
+#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP0_PCIE_TX_CREDITS_INIT_NP
+#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP0_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP0_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP0_PCIE_TX_CREDITS_STATUS
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP0_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP0_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT 0x0
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT 0x3
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT 0x6
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT 0x8
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT 0x10
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT 0x19
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT 0x1c
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK 0x00000007L
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK 0x00000038L
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK 0x00000040L
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK 0x00003F00L
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK 0x003F0000L
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK 0x02000000L
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK 0xF0000000L
+//BIFP0_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT 0x0
+#define BIFP0_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK 0x0000FFFFL
+//BIFP0_PCIE_CCIX_STACKED_BASE
+#define BIFP0_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT 0x4
+#define BIFP0_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK 0xFFFFFFF0L
+//BIFP0_PCIE_CCIX_STACKED_LIMIT
+#define BIFP0_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT 0x4
+#define BIFP0_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK 0xFFFFFFF0L
+//BIFP0_PCIE_CCIX_MISC_STATUS
+#define BIFP0_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT 0x0
+#define BIFP0_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT 0x1
+#define BIFP0_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK 0x00000001L
+#define BIFP0_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK 0x00000002L
+//BIFP0_PCIE_P_PORT_LANE_STATUS
+#define BIFP0_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP0_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP0_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP0_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP0_PCIE_FC_P
+#define BIFP0_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP0_PCIE_FC_P__PH_CREDITS__SHIFT 0x10
+#define BIFP0_PCIE_FC_P__PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP0_PCIE_FC_P__PH_CREDITS_MASK 0x0FFF0000L
+//BIFP0_PCIE_FC_NP
+#define BIFP0_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP0_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x10
+#define BIFP0_PCIE_FC_NP__NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP0_PCIE_FC_NP__NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP0_PCIE_FC_CPL
+#define BIFP0_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP0_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x10
+#define BIFP0_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP0_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP0_PCIE_FC_P_VC1
+#define BIFP0_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT 0x0
+#define BIFP0_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT 0x10
+#define BIFP0_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP0_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK 0x0FFF0000L
+//BIFP0_PCIE_FC_NP_VC1
+#define BIFP0_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT 0x0
+#define BIFP0_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT 0x10
+#define BIFP0_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP0_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP0_PCIE_FC_CPL_VC1
+#define BIFP0_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT 0x0
+#define BIFP0_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT 0x10
+#define BIFP0_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP0_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP0_PCIE_ERR_CNTL
+#define BIFP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT 0x13
+#define BIFP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT 0x14
+#define BIFP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define BIFP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK 0x00080000L
+#define BIFP0_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK 0x00100000L
+//BIFP0_PCIE_RX_CNTL
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP0_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT 0x1c
+#define BIFP0_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT 0x1d
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+#define BIFP0_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK 0x10000000L
+#define BIFP0_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK 0x20000000L
+//BIFP0_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP0_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP0_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP0_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP0_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP0_PCIE_RX_CNTL3
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP0_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP0_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP0_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP0_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP0_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP0_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP0_PCIEP_NAK_COUNTER
+#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP0_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP0_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP0_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT 0x5
+#define BIFP0_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK 0x00000020L
+//BIFP0_PCIE_AER_PRIV_TRIGGER
+#define BIFP0_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT 0x0
+#define BIFP0_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT 0x1
+#define BIFP0_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT 0x2
+#define BIFP0_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK 0x00000001L
+#define BIFP0_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK 0x00000002L
+#define BIFP0_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK 0x00000004L
+//BIFP0_PCIE_LC_CNTL
+#define BIFP0_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP0_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP0_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP0_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP0_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP0_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP0_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP0_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP0_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP0_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP0_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP0_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP0_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP0_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP0_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP0_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP0_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP0_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP0_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP0_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP0_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP0_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP0_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP0_PCIE_LC_TRAINING_CNTL
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP0_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP0_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP0_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP0_PCIE_LC_N_FTS_CNTL
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT 0xa
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xe
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT 0xf
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK 0x00000400L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00004000L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK 0x00008000L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP0_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP0_PCIE_LC_SPEED_CNTL
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x3
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x4
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x9
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0xa
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xb
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xd
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xe
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0x10
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x11
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x12
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x13
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x14
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x15
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x16
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT 0x17
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT 0x18
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x19
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x1a
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1c
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1d
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1e
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1f
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000008L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000030L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000400L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00001800L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00002000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x0000C000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00010000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00020000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00040000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00080000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00100000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00200000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00400000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK 0x00800000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK 0x01000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x02000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x0C000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x10000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x20000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x40000000L
+#define BIFP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x80000000L
+//BIFP0_PCIE_LC_STATE0
+#define BIFP0_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP0_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP0_PCIE_LC_STATE1
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP0_PCIE_LC_STATE2
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP0_PCIE_LC_STATE3
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP0_PCIE_LC_STATE4
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP0_PCIE_LC_STATE5
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP0_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT 0x5
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT 0x6
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT 0x17
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT 0x1b
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000010L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK 0x00000020L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK 0x00000040L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK 0x07800000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK 0x78000000L
+//BIFP0_PCIE_LC_CNTL2
+#define BIFP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x13
+#define BIFP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP0_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x00080000L
+#define BIFP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP0_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP0_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP0_PCIE_LC_CDR_CNTL
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP0_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP0_PCIE_LC_LANE_CNTL
+#define BIFP0_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP0_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+//BIFP0_PCIE_LC_CNTL3
+#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP0_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP0_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP0_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP0_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP0_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT 0xe
+#define BIFP0_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT 0xf
+#define BIFP0_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP0_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP0_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP0_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP0_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP0_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP0_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP0_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP0_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP0_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK 0x00001000L
+#define BIFP0_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK 0x00002000L
+#define BIFP0_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK 0x00004000L
+#define BIFP0_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK 0x00008000L
+#define BIFP0_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP0_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP0_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP0_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP0_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP0_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK 0x80000000L
+//BIFP0_PCIE_LC_CNTL4
+#define BIFP0_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT 0x5
+#define BIFP0_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP0_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT 0xb
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP0_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT 0xf
+#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT 0x11
+#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP0_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP0_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP0_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK 0x00000010L
+#define BIFP0_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK 0x00000020L
+#define BIFP0_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP0_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP0_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK 0x00000300L
+#define BIFP0_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK 0x00000800L
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK 0x00001000L
+#define BIFP0_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP0_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP0_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK 0x00008000L
+#define BIFP0_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK 0x00010000L
+#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK 0x00020000L
+#define BIFP0_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK 0x003C0000L
+#define BIFP0_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP0_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP0_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP0_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP0_PCIE_LC_CNTL5
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT 0xa
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP0_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP0_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK 0x00000003L
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK 0x0000003CL
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK 0x000003C0L
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK 0x0000FC00L
+#define BIFP0_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK 0x001F0000L
+#define BIFP0_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK 0x00C00000L
+#define BIFP0_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP0_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP0_PCIE_LC_FORCE_COEFF
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT 0x0
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT 0x1
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT 0x7
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT 0xd
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT 0x13
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK 0x00000001L
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK 0x0000007EL
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK 0x00001F80L
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK 0x0007E000L
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK 0x00080000L
+#define BIFP0_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP0_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT 0x1e
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+#define BIFP0_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK 0x40000000L
+//BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT 0x0
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT 0x1
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT 0x7
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT 0xd
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT 0x13
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT 0x19
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK 0x00000001L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK 0x0000007EL
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK 0x00001F80L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK 0x0007E000L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK 0x01F80000L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK 0x7E000000L
+//BIFP0_PCIE_LC_CNTL6
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP0_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP0_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000003L
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x0000000CL
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000030L
+#define BIFP0_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK 0x000000C0L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP0_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP0_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP0_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP0_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP0_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP0_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP0_PCIE_LC_CNTL7
+#define BIFP0_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP0_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP0_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP0_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP0_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP0_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP0_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT 0x19
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP0_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP0_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP0_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP0_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP0_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP0_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP0_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP0_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP0_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP0_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP0_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP0_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP0_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK 0x01000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_RATES_MASK 0x06000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP0_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK 0x80000000L
+//BIFP0_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP0_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP0_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT 0x1e
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT 0x1f
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK 0x40000000L
+#define BIFP0_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK 0x80000000L
+//BIFP0_PCIEP_STRAP_LC
+#define BIFP0_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP0_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP0_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP0_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP0_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP0_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP0_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP0_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP0_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP0_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP0_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP0_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x13
+#define BIFP0_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT 0x14
+#define BIFP0_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT 0x15
+#define BIFP0_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP0_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00080000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK 0x00100000L
+#define BIFP0_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK 0x00200000L
+//BIFP0_PCIEP_STRAP_MISC
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT 0x6
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT 0x7
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK 0x00000040L
+#define BIFP0_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK 0x00000080L
+//BIFP0_PCIEP_STRAP_LC2
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT 0x1
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT 0x3
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT 0x4
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT 0x7
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK 0x00000001L
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK 0x00000006L
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK 0x00000008L
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK 0x00000070L
+#define BIFP0_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK 0x00000380L
+//BIFP0_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT 0x5
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT 0x1a
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT 0x1b
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT 0x1c
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK 0x00000020L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK 0x04000000L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK 0x08000000L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK 0x10000000L
+//BIFP0_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP0_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP0_PCIE_LC_PORT_ORDER
+#define BIFP0_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP0_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP0_PCIEP_BCH_ECC_CNTL
+#define BIFP0_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP0_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP0_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP0_PCIEP_HPGI_PRIVATE
+#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP0_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP0_PCIEP_HPGI
+#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP0_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP0_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP0_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP0_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP0_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP0_PCIEP_HCNT_DESCRIPTOR
+#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x00001FFFL
+#define BIFP0_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP0_PCIE_LC_CNTL8
+#define BIFP0_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT 0x3
+#define BIFP0_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT 0x7
+#define BIFP0_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT 0x9
+#define BIFP0_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT 0xa
+#define BIFP0_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT 0xb
+#define BIFP0_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT 0x11
+#define BIFP0_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT 0x19
+#define BIFP0_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1b
+#define BIFP0_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT 0x1c
+#define BIFP0_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x1d
+#define BIFP0_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x1e
+#define BIFP0_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK 0x00000003L
+#define BIFP0_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK 0x00000004L
+#define BIFP0_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK 0x00000078L
+#define BIFP0_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK 0x00000080L
+#define BIFP0_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK 0x00000100L
+#define BIFP0_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK 0x00000200L
+#define BIFP0_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK 0x00000400L
+#define BIFP0_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK 0x00000800L
+#define BIFP0_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK 0x00001000L
+#define BIFP0_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK 0x0001E000L
+#define BIFP0_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK 0x00020000L
+#define BIFP0_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK 0x003C0000L
+#define BIFP0_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL8__LC_FOM_TIME_MASK 0x01800000L
+#define BIFP0_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK 0x02000000L
+#define BIFP0_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x04000000L
+#define BIFP0_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x08000000L
+#define BIFP0_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK 0x10000000L
+#define BIFP0_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x20000000L
+#define BIFP0_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0xC0000000L
+//BIFP0_PCIE_LC_CNTL9
+#define BIFP0_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT 0x1
+#define BIFP0_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT 0x3
+#define BIFP0_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT 0xa
+#define BIFP0_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT 0xb
+#define BIFP0_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT 0xe
+#define BIFP0_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT 0x19
+#define BIFP0_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT 0x1b
+#define BIFP0_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT 0x1c
+#define BIFP0_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT 0x1d
+#define BIFP0_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT 0x1e
+#define BIFP0_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK 0x00000001L
+#define BIFP0_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK 0x00000006L
+#define BIFP0_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK 0x00000008L
+#define BIFP0_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK 0x00000030L
+#define BIFP0_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK 0x000000C0L
+#define BIFP0_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK 0x00000300L
+#define BIFP0_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK 0x00000400L
+#define BIFP0_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK 0x00000800L
+#define BIFP0_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK 0x00001000L
+#define BIFP0_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK 0x00002000L
+#define BIFP0_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK 0x00FFC000L
+#define BIFP0_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK 0x01000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK 0x02000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK 0x04000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK 0x08000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK 0x10000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK 0x20000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK 0x40000000L
+#define BIFP0_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK 0x80000000L
+//BIFP0_PCIE_LC_FORCE_COEFF2
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT 0x0
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT 0x1
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT 0x7
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT 0xd
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT 0x13
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK 0x00000001L
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK 0x0000007EL
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK 0x00001F80L
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK 0x0007E000L
+#define BIFP0_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK 0x00080000L
+//BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT 0x0
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT 0x1
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT 0x7
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT 0xd
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT 0x13
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT 0x19
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK 0x00000001L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK 0x0000007EL
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK 0x00001F80L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK 0x0007E000L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK 0x01F80000L
+#define BIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK 0x7E000000L
+//BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT 0x0
+#define BIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT 0x1
+#define BIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK 0x00000001L
+#define BIFP0_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK 0x00000002L
+//BIFP0_PCIE_LC_CNTL10
+#define BIFP0_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT 0x1
+#define BIFP0_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT 0x1b
+#define BIFP0_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT 0x1d
+#define BIFP0_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT 0x1e
+#define BIFP0_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK 0x00000001L
+#define BIFP0_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK 0x00000002L
+#define BIFP0_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK 0x0000000CL
+#define BIFP0_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK 0x00000030L
+#define BIFP0_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK 0x0000FFC0L
+#define BIFP0_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK 0x03FF0000L
+#define BIFP0_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK 0x04000000L
+#define BIFP0_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK 0x18000000L
+#define BIFP0_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK 0x20000000L
+#define BIFP0_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK 0x40000000L
+#define BIFP0_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK 0x80000000L
+//BIFP0_PCIE_LC_CNTL11
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT 0x1
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT 0x3
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT 0x5
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT 0x9
+#define BIFP0_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT 0xe
+#define BIFP0_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT 0xf
+#define BIFP0_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT 0x11
+#define BIFP0_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT 0x13
+#define BIFP0_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT 0x14
+#define BIFP0_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT 0x18
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT 0x1a
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT 0x1b
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT 0x1c
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT 0x1e
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK 0x00000002L
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK 0x00000004L
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK 0x00000018L
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK 0x000001E0L
+#define BIFP0_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK 0x00001E00L
+#define BIFP0_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK 0x00002000L
+#define BIFP0_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK 0x00004000L
+#define BIFP0_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK 0x00008000L
+#define BIFP0_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK 0x00010000L
+#define BIFP0_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK 0x00020000L
+#define BIFP0_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK 0x00040000L
+#define BIFP0_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK 0x00080000L
+#define BIFP0_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK 0x00100000L
+#define BIFP0_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_EN_MASK 0x00800000L
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK 0x03000000L
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK 0x04000000L
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK 0x08000000L
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK 0x30000000L
+#define BIFP0_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK 0xC0000000L
+//BIFP0_PCIE_LC_CNTL12
+#define BIFP0_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT 0x0
+#define BIFP0_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT 0x1
+#define BIFP0_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT 0x2
+#define BIFP0_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT 0x3
+#define BIFP0_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT 0x4
+#define BIFP0_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT 0x5
+#define BIFP0_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT 0x6
+#define BIFP0_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT 0x7
+#define BIFP0_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT 0x8
+#define BIFP0_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT 0x9
+#define BIFP0_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT 0xa
+#define BIFP0_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT 0xb
+#define BIFP0_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT 0xc
+#define BIFP0_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT 0xd
+#define BIFP0_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT 0xe
+#define BIFP0_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT 0xf
+#define BIFP0_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT 0x10
+#define BIFP0_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT 0x11
+#define BIFP0_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT 0x12
+#define BIFP0_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT 0x13
+#define BIFP0_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT 0x14
+#define BIFP0_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT 0x15
+#define BIFP0_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT 0x16
+#define BIFP0_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT 0x17
+#define BIFP0_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT 0x1f
+#define BIFP0_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK 0x00000001L
+#define BIFP0_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK 0x00000002L
+#define BIFP0_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK 0x00000004L
+#define BIFP0_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK 0x00000008L
+#define BIFP0_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK 0x00000010L
+#define BIFP0_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK 0x00000020L
+#define BIFP0_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK 0x00000040L
+#define BIFP0_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK 0x00000080L
+#define BIFP0_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK 0x00000100L
+#define BIFP0_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK 0x00000200L
+#define BIFP0_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK 0x00000400L
+#define BIFP0_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK 0x00000800L
+#define BIFP0_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK 0x00001000L
+#define BIFP0_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK 0x00002000L
+#define BIFP0_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK 0x00004000L
+#define BIFP0_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK 0x00008000L
+#define BIFP0_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK 0x00010000L
+#define BIFP0_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK 0x00020000L
+#define BIFP0_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK 0x00040000L
+#define BIFP0_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK 0x00080000L
+#define BIFP0_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK 0x00100000L
+#define BIFP0_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK 0x00200000L
+#define BIFP0_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK 0x00400000L
+#define BIFP0_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK 0x00800000L
+#define BIFP0_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK 0x80000000L
+//BIFP0_PCIE_LC_SAVE_RESTORE_1
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT 0x0
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT 0x1
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT 0x2
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT 0xa
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT 0xb
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT 0xc
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT 0xd
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT 0xe
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT 0x10
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK 0x00000001L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK 0x00000002L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK 0x000003FCL
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK 0x00000400L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK 0x00000800L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK 0x00001000L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK 0x00002000L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK 0x0000C000L
+#define BIFP0_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK 0xFFFF0000L
+//BIFP0_PCIE_LC_SAVE_RESTORE_2
+#define BIFP0_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT 0x0
+#define BIFP0_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK 0xFFFFFFFFL
+//BIFP0_PCIE_LC_SAVE_RESTORE_3
+#define BIFP0_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT 0x0
+#define BIFP0_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp1_pciedir_p
+//BIFP1_PCIEP_RESERVED
+#define BIFP1_PCIEP_RESERVED__RESERVED__SHIFT 0x0
+#define BIFP1_PCIEP_RESERVED__RESERVED_MASK 0xFFFFFFFFL
+//BIFP1_PCIEP_SCRATCH
+#define BIFP1_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP1_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP1_PCIEP_PORT_CNTL
+#define BIFP1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP1_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP1_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP1_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x1a
+#define BIFP1_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP1_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP1_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP1_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP1_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP1_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x0003FF00L
+#define BIFP1_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP1_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+#define BIFP1_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x0C000000L
+//BIFP1_PCIE_TX_CNTL
+#define BIFP1_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP1_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP1_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP1_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP1_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT 0x1b
+#define BIFP1_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP1_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP1_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP1_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP1_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP1_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP1_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP1_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+#define BIFP1_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK 0x08000000L
+//BIFP1_PCIE_TX_REQUESTER_ID
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP1_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP1_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT 0x18
+#define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP1_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK 0x01000000L
+//BIFP1_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP1_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP1_PCIE_TX_SEQ
+#define BIFP1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP1_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP1_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP1_PCIE_TX_REPLAY
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT 0xe
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK 0x00004000L
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP1_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP1_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP1_PCIE_TX_NOP_DLLP
+#define BIFP1_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT 0x0
+#define BIFP1_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT 0x18
+#define BIFP1_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK 0x00FFFFFFL
+#define BIFP1_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK 0x01000000L
+//BIFP1_PCIE_TX_CNTL_2
+//BIFP1_PCIE_TX_SKID_CTRL
+#define BIFP1_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT 0x0
+#define BIFP1_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT 0x4
+#define BIFP1_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK 0x0000000FL
+#define BIFP1_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK 0x00000010L
+//BIFP1_PCIE_TX_CREDITS_ADVT_P
+#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00003FFFL
+#define BIFP1_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x03FF0000L
+//BIFP1_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00003FFFL
+#define BIFP1_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x03FF0000L
+//BIFP1_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00003FFFL
+#define BIFP1_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x03FF0000L
+//BIFP1_PCIE_TX_CREDITS_INIT_P
+#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP1_PCIE_TX_CREDITS_INIT_NP
+#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP1_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP1_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP1_PCIE_TX_CREDITS_STATUS
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP1_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP1_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT 0x0
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT 0x3
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT 0x6
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT 0x8
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT 0x10
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT 0x19
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT 0x1c
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK 0x00000007L
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK 0x00000038L
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK 0x00000040L
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK 0x00003F00L
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK 0x003F0000L
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK 0x02000000L
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK 0xF0000000L
+//BIFP1_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT 0x0
+#define BIFP1_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK 0x0000FFFFL
+//BIFP1_PCIE_CCIX_STACKED_BASE
+#define BIFP1_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT 0x4
+#define BIFP1_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK 0xFFFFFFF0L
+//BIFP1_PCIE_CCIX_STACKED_LIMIT
+#define BIFP1_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT 0x4
+#define BIFP1_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK 0xFFFFFFF0L
+//BIFP1_PCIE_CCIX_MISC_STATUS
+#define BIFP1_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT 0x0
+#define BIFP1_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT 0x1
+#define BIFP1_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK 0x00000001L
+#define BIFP1_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK 0x00000002L
+//BIFP1_PCIE_P_PORT_LANE_STATUS
+#define BIFP1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP1_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP1_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP1_PCIE_FC_P
+#define BIFP1_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP1_PCIE_FC_P__PH_CREDITS__SHIFT 0x10
+#define BIFP1_PCIE_FC_P__PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP1_PCIE_FC_P__PH_CREDITS_MASK 0x0FFF0000L
+//BIFP1_PCIE_FC_NP
+#define BIFP1_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP1_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x10
+#define BIFP1_PCIE_FC_NP__NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP1_PCIE_FC_NP__NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP1_PCIE_FC_CPL
+#define BIFP1_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP1_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x10
+#define BIFP1_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP1_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP1_PCIE_FC_P_VC1
+#define BIFP1_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT 0x0
+#define BIFP1_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT 0x10
+#define BIFP1_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP1_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK 0x0FFF0000L
+//BIFP1_PCIE_FC_NP_VC1
+#define BIFP1_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT 0x0
+#define BIFP1_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT 0x10
+#define BIFP1_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP1_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP1_PCIE_FC_CPL_VC1
+#define BIFP1_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT 0x0
+#define BIFP1_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT 0x10
+#define BIFP1_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP1_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP1_PCIE_ERR_CNTL
+#define BIFP1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP1_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT 0x13
+#define BIFP1_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT 0x14
+#define BIFP1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP1_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP1_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP1_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP1_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP1_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP1_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP1_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP1_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define BIFP1_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK 0x00080000L
+#define BIFP1_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK 0x00100000L
+//BIFP1_PCIE_RX_CNTL
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP1_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP1_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT 0x1c
+#define BIFP1_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT 0x1d
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP1_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP1_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP1_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP1_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+#define BIFP1_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK 0x10000000L
+#define BIFP1_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK 0x20000000L
+//BIFP1_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP1_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP1_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP1_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP1_PCIE_RX_CNTL3
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP1_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP1_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP1_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP1_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP1_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP1_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP1_PCIEP_NAK_COUNTER
+#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP1_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP1_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP1_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT 0x5
+#define BIFP1_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK 0x00000020L
+//BIFP1_PCIE_AER_PRIV_TRIGGER
+#define BIFP1_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT 0x0
+#define BIFP1_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT 0x1
+#define BIFP1_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT 0x2
+#define BIFP1_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK 0x00000001L
+#define BIFP1_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK 0x00000002L
+#define BIFP1_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK 0x00000004L
+//BIFP1_PCIE_LC_CNTL
+#define BIFP1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP1_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP1_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP1_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP1_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP1_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP1_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP1_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP1_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP1_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP1_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP1_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP1_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP1_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP1_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP1_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP1_PCIE_LC_TRAINING_CNTL
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP1_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP1_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP1_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP1_PCIE_LC_N_FTS_CNTL
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT 0xa
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xe
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT 0xf
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK 0x00000400L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00004000L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK 0x00008000L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP1_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP1_PCIE_LC_SPEED_CNTL
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x3
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x4
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x9
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0xa
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xb
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xd
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xe
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0x10
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x11
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x12
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x13
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x14
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x15
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x16
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT 0x17
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT 0x18
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x19
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x1a
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1c
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1d
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1e
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1f
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000008L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000030L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000400L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00001800L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00002000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x0000C000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00010000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00020000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00040000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00080000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00100000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00200000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00400000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK 0x00800000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK 0x01000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x02000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x0C000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x10000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x20000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x40000000L
+#define BIFP1_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x80000000L
+//BIFP1_PCIE_LC_STATE0
+#define BIFP1_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP1_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP1_PCIE_LC_STATE1
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP1_PCIE_LC_STATE2
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP1_PCIE_LC_STATE3
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP1_PCIE_LC_STATE4
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP1_PCIE_LC_STATE5
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP1_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT 0x5
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT 0x6
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT 0x17
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT 0x1b
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000010L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK 0x00000020L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK 0x00000040L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK 0x07800000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK 0x78000000L
+//BIFP1_PCIE_LC_CNTL2
+#define BIFP1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP1_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x13
+#define BIFP1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP1_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP1_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP1_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP1_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP1_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP1_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP1_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x00080000L
+#define BIFP1_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP1_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP1_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP1_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP1_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP1_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP1_PCIE_LC_CDR_CNTL
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP1_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP1_PCIE_LC_LANE_CNTL
+#define BIFP1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP1_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+//BIFP1_PCIE_LC_CNTL3
+#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP1_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT 0xe
+#define BIFP1_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT 0xf
+#define BIFP1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP1_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP1_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP1_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP1_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP1_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP1_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP1_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP1_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK 0x00001000L
+#define BIFP1_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK 0x00002000L
+#define BIFP1_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK 0x00004000L
+#define BIFP1_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK 0x00008000L
+#define BIFP1_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP1_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP1_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP1_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP1_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP1_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK 0x80000000L
+//BIFP1_PCIE_LC_CNTL4
+#define BIFP1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT 0x5
+#define BIFP1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT 0xb
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT 0xf
+#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT 0x11
+#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP1_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP1_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK 0x00000010L
+#define BIFP1_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK 0x00000020L
+#define BIFP1_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP1_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP1_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK 0x00000300L
+#define BIFP1_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK 0x00000800L
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK 0x00001000L
+#define BIFP1_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP1_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP1_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK 0x00008000L
+#define BIFP1_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK 0x00010000L
+#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK 0x00020000L
+#define BIFP1_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK 0x003C0000L
+#define BIFP1_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP1_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP1_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP1_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP1_PCIE_LC_CNTL5
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT 0xa
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP1_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP1_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK 0x00000003L
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK 0x0000003CL
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK 0x000003C0L
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK 0x0000FC00L
+#define BIFP1_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK 0x001F0000L
+#define BIFP1_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK 0x00C00000L
+#define BIFP1_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP1_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP1_PCIE_LC_FORCE_COEFF
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT 0x0
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT 0x1
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT 0x7
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT 0xd
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT 0x13
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK 0x00000001L
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK 0x0000007EL
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK 0x00001F80L
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK 0x0007E000L
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK 0x00080000L
+#define BIFP1_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP1_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT 0x1e
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+#define BIFP1_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK 0x40000000L
+//BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT 0x0
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT 0x1
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT 0x7
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT 0xd
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT 0x13
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT 0x19
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK 0x00000001L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK 0x0000007EL
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK 0x00001F80L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK 0x0007E000L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK 0x01F80000L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK 0x7E000000L
+//BIFP1_PCIE_LC_CNTL6
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP1_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP1_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000003L
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x0000000CL
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000030L
+#define BIFP1_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK 0x000000C0L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP1_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP1_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP1_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP1_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP1_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP1_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP1_PCIE_LC_CNTL7
+#define BIFP1_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP1_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP1_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP1_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP1_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP1_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP1_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT 0x19
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP1_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP1_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP1_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP1_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP1_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP1_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP1_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP1_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP1_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP1_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP1_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP1_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP1_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK 0x01000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_RATES_MASK 0x06000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP1_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK 0x80000000L
+//BIFP1_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP1_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP1_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT 0x1e
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT 0x1f
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK 0x40000000L
+#define BIFP1_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK 0x80000000L
+//BIFP1_PCIEP_STRAP_LC
+#define BIFP1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP1_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x13
+#define BIFP1_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT 0x14
+#define BIFP1_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT 0x15
+#define BIFP1_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP1_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00080000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK 0x00100000L
+#define BIFP1_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK 0x00200000L
+//BIFP1_PCIEP_STRAP_MISC
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT 0x6
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT 0x7
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK 0x00000040L
+#define BIFP1_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK 0x00000080L
+//BIFP1_PCIEP_STRAP_LC2
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT 0x1
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT 0x3
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT 0x4
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT 0x7
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK 0x00000001L
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK 0x00000006L
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK 0x00000008L
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK 0x00000070L
+#define BIFP1_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK 0x00000380L
+//BIFP1_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT 0x5
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT 0x1a
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT 0x1b
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT 0x1c
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK 0x00000020L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK 0x04000000L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK 0x08000000L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK 0x10000000L
+//BIFP1_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP1_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP1_PCIE_LC_PORT_ORDER
+#define BIFP1_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP1_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP1_PCIEP_BCH_ECC_CNTL
+#define BIFP1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP1_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP1_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP1_PCIEP_HPGI_PRIVATE
+#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP1_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP1_PCIEP_HPGI
+#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP1_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP1_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP1_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP1_PCIEP_HCNT_DESCRIPTOR
+#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x00001FFFL
+#define BIFP1_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP1_PCIE_LC_CNTL8
+#define BIFP1_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT 0x3
+#define BIFP1_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT 0x7
+#define BIFP1_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT 0x9
+#define BIFP1_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT 0xa
+#define BIFP1_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT 0xb
+#define BIFP1_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT 0x11
+#define BIFP1_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT 0x19
+#define BIFP1_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1b
+#define BIFP1_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT 0x1c
+#define BIFP1_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x1d
+#define BIFP1_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x1e
+#define BIFP1_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK 0x00000003L
+#define BIFP1_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK 0x00000004L
+#define BIFP1_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK 0x00000078L
+#define BIFP1_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK 0x00000080L
+#define BIFP1_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK 0x00000100L
+#define BIFP1_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK 0x00000200L
+#define BIFP1_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK 0x00000400L
+#define BIFP1_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK 0x00000800L
+#define BIFP1_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK 0x00001000L
+#define BIFP1_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK 0x0001E000L
+#define BIFP1_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK 0x00020000L
+#define BIFP1_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK 0x003C0000L
+#define BIFP1_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL8__LC_FOM_TIME_MASK 0x01800000L
+#define BIFP1_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK 0x02000000L
+#define BIFP1_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x04000000L
+#define BIFP1_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x08000000L
+#define BIFP1_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK 0x10000000L
+#define BIFP1_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x20000000L
+#define BIFP1_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0xC0000000L
+//BIFP1_PCIE_LC_CNTL9
+#define BIFP1_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT 0x1
+#define BIFP1_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT 0x3
+#define BIFP1_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT 0xa
+#define BIFP1_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT 0xb
+#define BIFP1_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT 0xe
+#define BIFP1_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT 0x19
+#define BIFP1_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT 0x1b
+#define BIFP1_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT 0x1c
+#define BIFP1_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT 0x1d
+#define BIFP1_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT 0x1e
+#define BIFP1_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK 0x00000001L
+#define BIFP1_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK 0x00000006L
+#define BIFP1_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK 0x00000008L
+#define BIFP1_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK 0x00000030L
+#define BIFP1_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK 0x000000C0L
+#define BIFP1_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK 0x00000300L
+#define BIFP1_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK 0x00000400L
+#define BIFP1_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK 0x00000800L
+#define BIFP1_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK 0x00001000L
+#define BIFP1_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK 0x00002000L
+#define BIFP1_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK 0x00FFC000L
+#define BIFP1_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK 0x01000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK 0x02000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK 0x04000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK 0x08000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK 0x10000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK 0x20000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK 0x40000000L
+#define BIFP1_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK 0x80000000L
+//BIFP1_PCIE_LC_FORCE_COEFF2
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT 0x0
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT 0x1
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT 0x7
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT 0xd
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT 0x13
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK 0x00000001L
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK 0x0000007EL
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK 0x00001F80L
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK 0x0007E000L
+#define BIFP1_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK 0x00080000L
+//BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT 0x0
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT 0x1
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT 0x7
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT 0xd
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT 0x13
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT 0x19
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK 0x00000001L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK 0x0000007EL
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK 0x00001F80L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK 0x0007E000L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK 0x01F80000L
+#define BIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK 0x7E000000L
+//BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT 0x0
+#define BIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT 0x1
+#define BIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK 0x00000001L
+#define BIFP1_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK 0x00000002L
+//BIFP1_PCIE_LC_CNTL10
+#define BIFP1_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT 0x1
+#define BIFP1_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT 0x1b
+#define BIFP1_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT 0x1d
+#define BIFP1_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT 0x1e
+#define BIFP1_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK 0x00000001L
+#define BIFP1_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK 0x00000002L
+#define BIFP1_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK 0x0000000CL
+#define BIFP1_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK 0x00000030L
+#define BIFP1_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK 0x0000FFC0L
+#define BIFP1_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK 0x03FF0000L
+#define BIFP1_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK 0x04000000L
+#define BIFP1_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK 0x18000000L
+#define BIFP1_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK 0x20000000L
+#define BIFP1_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK 0x40000000L
+#define BIFP1_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK 0x80000000L
+//BIFP1_PCIE_LC_CNTL11
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT 0x1
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT 0x3
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT 0x5
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT 0x9
+#define BIFP1_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT 0xe
+#define BIFP1_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT 0xf
+#define BIFP1_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT 0x11
+#define BIFP1_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT 0x13
+#define BIFP1_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT 0x14
+#define BIFP1_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT 0x18
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT 0x1a
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT 0x1b
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT 0x1c
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT 0x1e
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK 0x00000002L
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK 0x00000004L
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK 0x00000018L
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK 0x000001E0L
+#define BIFP1_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK 0x00001E00L
+#define BIFP1_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK 0x00002000L
+#define BIFP1_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK 0x00004000L
+#define BIFP1_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK 0x00008000L
+#define BIFP1_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK 0x00010000L
+#define BIFP1_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK 0x00020000L
+#define BIFP1_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK 0x00040000L
+#define BIFP1_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK 0x00080000L
+#define BIFP1_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK 0x00100000L
+#define BIFP1_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_EN_MASK 0x00800000L
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK 0x03000000L
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK 0x04000000L
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK 0x08000000L
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK 0x30000000L
+#define BIFP1_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK 0xC0000000L
+//BIFP1_PCIE_LC_CNTL12
+#define BIFP1_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT 0x0
+#define BIFP1_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT 0x1
+#define BIFP1_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT 0x2
+#define BIFP1_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT 0x3
+#define BIFP1_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT 0x4
+#define BIFP1_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT 0x5
+#define BIFP1_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT 0x6
+#define BIFP1_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT 0x7
+#define BIFP1_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT 0x8
+#define BIFP1_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT 0x9
+#define BIFP1_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT 0xa
+#define BIFP1_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT 0xb
+#define BIFP1_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT 0xc
+#define BIFP1_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT 0xd
+#define BIFP1_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT 0xe
+#define BIFP1_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT 0xf
+#define BIFP1_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT 0x10
+#define BIFP1_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT 0x11
+#define BIFP1_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT 0x12
+#define BIFP1_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT 0x13
+#define BIFP1_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT 0x14
+#define BIFP1_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT 0x15
+#define BIFP1_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT 0x16
+#define BIFP1_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT 0x17
+#define BIFP1_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT 0x1f
+#define BIFP1_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK 0x00000001L
+#define BIFP1_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK 0x00000002L
+#define BIFP1_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK 0x00000004L
+#define BIFP1_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK 0x00000008L
+#define BIFP1_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK 0x00000010L
+#define BIFP1_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK 0x00000020L
+#define BIFP1_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK 0x00000040L
+#define BIFP1_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK 0x00000080L
+#define BIFP1_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK 0x00000100L
+#define BIFP1_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK 0x00000200L
+#define BIFP1_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK 0x00000400L
+#define BIFP1_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK 0x00000800L
+#define BIFP1_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK 0x00001000L
+#define BIFP1_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK 0x00002000L
+#define BIFP1_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK 0x00004000L
+#define BIFP1_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK 0x00008000L
+#define BIFP1_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK 0x00010000L
+#define BIFP1_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK 0x00020000L
+#define BIFP1_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK 0x00040000L
+#define BIFP1_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK 0x00080000L
+#define BIFP1_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK 0x00100000L
+#define BIFP1_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK 0x00200000L
+#define BIFP1_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK 0x00400000L
+#define BIFP1_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK 0x00800000L
+#define BIFP1_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK 0x80000000L
+//BIFP1_PCIE_LC_SAVE_RESTORE_1
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT 0x0
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT 0x1
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT 0x2
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT 0xa
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT 0xb
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT 0xc
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT 0xd
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT 0xe
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT 0x10
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK 0x00000001L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK 0x00000002L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK 0x000003FCL
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK 0x00000400L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK 0x00000800L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK 0x00001000L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK 0x00002000L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK 0x0000C000L
+#define BIFP1_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK 0xFFFF0000L
+//BIFP1_PCIE_LC_SAVE_RESTORE_2
+#define BIFP1_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT 0x0
+#define BIFP1_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK 0xFFFFFFFFL
+//BIFP1_PCIE_LC_SAVE_RESTORE_3
+#define BIFP1_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT 0x0
+#define BIFP1_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp2_pciedir_p
+//BIFP2_PCIEP_RESERVED
+#define BIFP2_PCIEP_RESERVED__RESERVED__SHIFT 0x0
+#define BIFP2_PCIEP_RESERVED__RESERVED_MASK 0xFFFFFFFFL
+//BIFP2_PCIEP_SCRATCH
+#define BIFP2_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP2_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP2_PCIEP_PORT_CNTL
+#define BIFP2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP2_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP2_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP2_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x1a
+#define BIFP2_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP2_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP2_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP2_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP2_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP2_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x0003FF00L
+#define BIFP2_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP2_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+#define BIFP2_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x0C000000L
+//BIFP2_PCIE_TX_CNTL
+#define BIFP2_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP2_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP2_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP2_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP2_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT 0x1b
+#define BIFP2_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP2_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP2_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP2_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP2_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP2_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP2_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP2_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+#define BIFP2_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK 0x08000000L
+//BIFP2_PCIE_TX_REQUESTER_ID
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP2_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP2_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT 0x18
+#define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP2_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK 0x01000000L
+//BIFP2_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP2_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP2_PCIE_TX_SEQ
+#define BIFP2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP2_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP2_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP2_PCIE_TX_REPLAY
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT 0xe
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK 0x00004000L
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP2_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP2_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP2_PCIE_TX_NOP_DLLP
+#define BIFP2_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT 0x0
+#define BIFP2_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT 0x18
+#define BIFP2_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK 0x00FFFFFFL
+#define BIFP2_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK 0x01000000L
+//BIFP2_PCIE_TX_CNTL_2
+//BIFP2_PCIE_TX_SKID_CTRL
+#define BIFP2_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT 0x0
+#define BIFP2_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT 0x4
+#define BIFP2_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK 0x0000000FL
+#define BIFP2_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK 0x00000010L
+//BIFP2_PCIE_TX_CREDITS_ADVT_P
+#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00003FFFL
+#define BIFP2_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x03FF0000L
+//BIFP2_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00003FFFL
+#define BIFP2_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x03FF0000L
+//BIFP2_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00003FFFL
+#define BIFP2_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x03FF0000L
+//BIFP2_PCIE_TX_CREDITS_INIT_P
+#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP2_PCIE_TX_CREDITS_INIT_NP
+#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP2_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP2_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP2_PCIE_TX_CREDITS_STATUS
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP2_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP2_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT 0x0
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT 0x3
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT 0x6
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT 0x8
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT 0x10
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT 0x19
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT 0x1c
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK 0x00000007L
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK 0x00000038L
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK 0x00000040L
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK 0x00003F00L
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK 0x003F0000L
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK 0x02000000L
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK 0xF0000000L
+//BIFP2_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT 0x0
+#define BIFP2_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK 0x0000FFFFL
+//BIFP2_PCIE_CCIX_STACKED_BASE
+#define BIFP2_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT 0x4
+#define BIFP2_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK 0xFFFFFFF0L
+//BIFP2_PCIE_CCIX_STACKED_LIMIT
+#define BIFP2_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT 0x4
+#define BIFP2_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK 0xFFFFFFF0L
+//BIFP2_PCIE_CCIX_MISC_STATUS
+#define BIFP2_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT 0x0
+#define BIFP2_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT 0x1
+#define BIFP2_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK 0x00000001L
+#define BIFP2_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK 0x00000002L
+//BIFP2_PCIE_P_PORT_LANE_STATUS
+#define BIFP2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP2_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP2_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP2_PCIE_FC_P
+#define BIFP2_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP2_PCIE_FC_P__PH_CREDITS__SHIFT 0x10
+#define BIFP2_PCIE_FC_P__PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP2_PCIE_FC_P__PH_CREDITS_MASK 0x0FFF0000L
+//BIFP2_PCIE_FC_NP
+#define BIFP2_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP2_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x10
+#define BIFP2_PCIE_FC_NP__NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP2_PCIE_FC_NP__NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP2_PCIE_FC_CPL
+#define BIFP2_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP2_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x10
+#define BIFP2_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP2_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP2_PCIE_FC_P_VC1
+#define BIFP2_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT 0x0
+#define BIFP2_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT 0x10
+#define BIFP2_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP2_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK 0x0FFF0000L
+//BIFP2_PCIE_FC_NP_VC1
+#define BIFP2_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT 0x0
+#define BIFP2_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT 0x10
+#define BIFP2_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP2_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP2_PCIE_FC_CPL_VC1
+#define BIFP2_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT 0x0
+#define BIFP2_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT 0x10
+#define BIFP2_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP2_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP2_PCIE_ERR_CNTL
+#define BIFP2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP2_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT 0x13
+#define BIFP2_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT 0x14
+#define BIFP2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP2_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP2_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP2_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP2_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP2_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP2_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP2_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP2_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define BIFP2_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK 0x00080000L
+#define BIFP2_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK 0x00100000L
+//BIFP2_PCIE_RX_CNTL
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP2_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP2_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT 0x1c
+#define BIFP2_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT 0x1d
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP2_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP2_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP2_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP2_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+#define BIFP2_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK 0x10000000L
+#define BIFP2_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK 0x20000000L
+//BIFP2_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP2_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP2_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP2_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP2_PCIE_RX_CNTL3
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP2_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP2_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP2_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP2_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP2_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP2_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP2_PCIEP_NAK_COUNTER
+#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP2_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP2_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP2_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT 0x5
+#define BIFP2_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK 0x00000020L
+//BIFP2_PCIE_AER_PRIV_TRIGGER
+#define BIFP2_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT 0x0
+#define BIFP2_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT 0x1
+#define BIFP2_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT 0x2
+#define BIFP2_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK 0x00000001L
+#define BIFP2_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK 0x00000002L
+#define BIFP2_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK 0x00000004L
+//BIFP2_PCIE_LC_CNTL
+#define BIFP2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP2_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP2_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP2_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP2_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP2_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP2_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP2_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP2_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP2_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP2_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP2_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP2_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP2_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP2_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP2_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP2_PCIE_LC_TRAINING_CNTL
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP2_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP2_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP2_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP2_PCIE_LC_N_FTS_CNTL
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT 0xa
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xe
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT 0xf
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK 0x00000400L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00004000L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK 0x00008000L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP2_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP2_PCIE_LC_SPEED_CNTL
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x3
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x4
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x9
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0xa
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xb
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xd
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xe
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0x10
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x11
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x12
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x13
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x14
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x15
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x16
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT 0x17
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT 0x18
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x19
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x1a
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1c
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1d
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1e
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1f
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000008L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000030L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000400L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00001800L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00002000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x0000C000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00010000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00020000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00040000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00080000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00100000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00200000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00400000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK 0x00800000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK 0x01000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x02000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x0C000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x10000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x20000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x40000000L
+#define BIFP2_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x80000000L
+//BIFP2_PCIE_LC_STATE0
+#define BIFP2_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP2_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP2_PCIE_LC_STATE1
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP2_PCIE_LC_STATE2
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP2_PCIE_LC_STATE3
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP2_PCIE_LC_STATE4
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP2_PCIE_LC_STATE5
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP2_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT 0x5
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT 0x6
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT 0x17
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT 0x1b
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000010L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK 0x00000020L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK 0x00000040L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK 0x07800000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK 0x78000000L
+//BIFP2_PCIE_LC_CNTL2
+#define BIFP2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP2_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x13
+#define BIFP2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP2_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP2_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP2_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP2_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP2_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP2_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP2_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x00080000L
+#define BIFP2_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP2_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP2_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP2_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP2_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP2_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP2_PCIE_LC_CDR_CNTL
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP2_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP2_PCIE_LC_LANE_CNTL
+#define BIFP2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP2_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+//BIFP2_PCIE_LC_CNTL3
+#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP2_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT 0xe
+#define BIFP2_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT 0xf
+#define BIFP2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP2_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP2_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP2_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP2_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP2_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP2_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP2_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP2_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK 0x00001000L
+#define BIFP2_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK 0x00002000L
+#define BIFP2_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK 0x00004000L
+#define BIFP2_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK 0x00008000L
+#define BIFP2_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP2_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP2_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP2_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP2_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP2_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK 0x80000000L
+//BIFP2_PCIE_LC_CNTL4
+#define BIFP2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT 0x5
+#define BIFP2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT 0xb
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT 0xf
+#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT 0x11
+#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP2_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP2_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK 0x00000010L
+#define BIFP2_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK 0x00000020L
+#define BIFP2_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP2_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP2_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK 0x00000300L
+#define BIFP2_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK 0x00000800L
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK 0x00001000L
+#define BIFP2_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP2_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP2_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK 0x00008000L
+#define BIFP2_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK 0x00010000L
+#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK 0x00020000L
+#define BIFP2_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK 0x003C0000L
+#define BIFP2_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP2_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP2_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP2_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP2_PCIE_LC_CNTL5
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT 0xa
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP2_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP2_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK 0x00000003L
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK 0x0000003CL
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK 0x000003C0L
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK 0x0000FC00L
+#define BIFP2_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK 0x001F0000L
+#define BIFP2_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK 0x00C00000L
+#define BIFP2_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP2_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP2_PCIE_LC_FORCE_COEFF
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT 0x0
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT 0x1
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT 0x7
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT 0xd
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT 0x13
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK 0x00000001L
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK 0x0000007EL
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK 0x00001F80L
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK 0x0007E000L
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK 0x00080000L
+#define BIFP2_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP2_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT 0x1e
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+#define BIFP2_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK 0x40000000L
+//BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT 0x0
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT 0x1
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT 0x7
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT 0xd
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT 0x13
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT 0x19
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK 0x00000001L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK 0x0000007EL
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK 0x00001F80L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK 0x0007E000L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK 0x01F80000L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK 0x7E000000L
+//BIFP2_PCIE_LC_CNTL6
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP2_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP2_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000003L
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x0000000CL
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000030L
+#define BIFP2_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK 0x000000C0L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP2_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP2_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP2_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP2_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP2_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP2_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP2_PCIE_LC_CNTL7
+#define BIFP2_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP2_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP2_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP2_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP2_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP2_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP2_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT 0x19
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP2_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP2_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP2_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP2_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP2_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP2_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP2_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP2_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP2_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP2_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP2_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP2_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP2_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK 0x01000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_RATES_MASK 0x06000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP2_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK 0x80000000L
+//BIFP2_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP2_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP2_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT 0x1e
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT 0x1f
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK 0x40000000L
+#define BIFP2_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK 0x80000000L
+//BIFP2_PCIEP_STRAP_LC
+#define BIFP2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP2_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x13
+#define BIFP2_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT 0x14
+#define BIFP2_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT 0x15
+#define BIFP2_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP2_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00080000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK 0x00100000L
+#define BIFP2_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK 0x00200000L
+//BIFP2_PCIEP_STRAP_MISC
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT 0x6
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT 0x7
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK 0x00000040L
+#define BIFP2_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK 0x00000080L
+//BIFP2_PCIEP_STRAP_LC2
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT 0x1
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT 0x3
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT 0x4
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT 0x7
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK 0x00000001L
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK 0x00000006L
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK 0x00000008L
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK 0x00000070L
+#define BIFP2_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK 0x00000380L
+//BIFP2_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT 0x5
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT 0x1a
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT 0x1b
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT 0x1c
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK 0x00000020L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK 0x04000000L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK 0x08000000L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK 0x10000000L
+//BIFP2_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP2_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP2_PCIE_LC_PORT_ORDER
+#define BIFP2_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP2_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP2_PCIEP_BCH_ECC_CNTL
+#define BIFP2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP2_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP2_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP2_PCIEP_HPGI_PRIVATE
+#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP2_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP2_PCIEP_HPGI
+#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP2_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP2_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP2_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP2_PCIEP_HCNT_DESCRIPTOR
+#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x00001FFFL
+#define BIFP2_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP2_PCIE_LC_CNTL8
+#define BIFP2_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT 0x3
+#define BIFP2_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT 0x7
+#define BIFP2_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT 0x9
+#define BIFP2_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT 0xa
+#define BIFP2_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT 0xb
+#define BIFP2_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT 0x11
+#define BIFP2_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT 0x19
+#define BIFP2_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1b
+#define BIFP2_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT 0x1c
+#define BIFP2_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x1d
+#define BIFP2_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x1e
+#define BIFP2_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK 0x00000003L
+#define BIFP2_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK 0x00000004L
+#define BIFP2_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK 0x00000078L
+#define BIFP2_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK 0x00000080L
+#define BIFP2_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK 0x00000100L
+#define BIFP2_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK 0x00000200L
+#define BIFP2_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK 0x00000400L
+#define BIFP2_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK 0x00000800L
+#define BIFP2_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK 0x00001000L
+#define BIFP2_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK 0x0001E000L
+#define BIFP2_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK 0x00020000L
+#define BIFP2_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK 0x003C0000L
+#define BIFP2_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL8__LC_FOM_TIME_MASK 0x01800000L
+#define BIFP2_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK 0x02000000L
+#define BIFP2_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x04000000L
+#define BIFP2_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x08000000L
+#define BIFP2_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK 0x10000000L
+#define BIFP2_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x20000000L
+#define BIFP2_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0xC0000000L
+//BIFP2_PCIE_LC_CNTL9
+#define BIFP2_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT 0x1
+#define BIFP2_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT 0x3
+#define BIFP2_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT 0xa
+#define BIFP2_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT 0xb
+#define BIFP2_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT 0xe
+#define BIFP2_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT 0x19
+#define BIFP2_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT 0x1b
+#define BIFP2_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT 0x1c
+#define BIFP2_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT 0x1d
+#define BIFP2_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT 0x1e
+#define BIFP2_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK 0x00000001L
+#define BIFP2_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK 0x00000006L
+#define BIFP2_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK 0x00000008L
+#define BIFP2_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK 0x00000030L
+#define BIFP2_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK 0x000000C0L
+#define BIFP2_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK 0x00000300L
+#define BIFP2_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK 0x00000400L
+#define BIFP2_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK 0x00000800L
+#define BIFP2_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK 0x00001000L
+#define BIFP2_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK 0x00002000L
+#define BIFP2_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK 0x00FFC000L
+#define BIFP2_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK 0x01000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK 0x02000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK 0x04000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK 0x08000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK 0x10000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK 0x20000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK 0x40000000L
+#define BIFP2_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK 0x80000000L
+//BIFP2_PCIE_LC_FORCE_COEFF2
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT 0x0
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT 0x1
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT 0x7
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT 0xd
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT 0x13
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK 0x00000001L
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK 0x0000007EL
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK 0x00001F80L
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK 0x0007E000L
+#define BIFP2_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK 0x00080000L
+//BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT 0x0
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT 0x1
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT 0x7
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT 0xd
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT 0x13
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT 0x19
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK 0x00000001L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK 0x0000007EL
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK 0x00001F80L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK 0x0007E000L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK 0x01F80000L
+#define BIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK 0x7E000000L
+//BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT 0x0
+#define BIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT 0x1
+#define BIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK 0x00000001L
+#define BIFP2_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK 0x00000002L
+//BIFP2_PCIE_LC_CNTL10
+#define BIFP2_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT 0x1
+#define BIFP2_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT 0x1b
+#define BIFP2_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT 0x1d
+#define BIFP2_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT 0x1e
+#define BIFP2_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK 0x00000001L
+#define BIFP2_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK 0x00000002L
+#define BIFP2_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK 0x0000000CL
+#define BIFP2_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK 0x00000030L
+#define BIFP2_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK 0x0000FFC0L
+#define BIFP2_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK 0x03FF0000L
+#define BIFP2_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK 0x04000000L
+#define BIFP2_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK 0x18000000L
+#define BIFP2_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK 0x20000000L
+#define BIFP2_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK 0x40000000L
+#define BIFP2_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK 0x80000000L
+//BIFP2_PCIE_LC_CNTL11
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT 0x1
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT 0x3
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT 0x5
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT 0x9
+#define BIFP2_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT 0xe
+#define BIFP2_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT 0xf
+#define BIFP2_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT 0x11
+#define BIFP2_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT 0x13
+#define BIFP2_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT 0x14
+#define BIFP2_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT 0x18
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT 0x1a
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT 0x1b
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT 0x1c
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT 0x1e
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK 0x00000002L
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK 0x00000004L
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK 0x00000018L
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK 0x000001E0L
+#define BIFP2_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK 0x00001E00L
+#define BIFP2_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK 0x00002000L
+#define BIFP2_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK 0x00004000L
+#define BIFP2_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK 0x00008000L
+#define BIFP2_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK 0x00010000L
+#define BIFP2_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK 0x00020000L
+#define BIFP2_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK 0x00040000L
+#define BIFP2_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK 0x00080000L
+#define BIFP2_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK 0x00100000L
+#define BIFP2_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_EN_MASK 0x00800000L
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK 0x03000000L
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK 0x04000000L
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK 0x08000000L
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK 0x30000000L
+#define BIFP2_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK 0xC0000000L
+//BIFP2_PCIE_LC_CNTL12
+#define BIFP2_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT 0x0
+#define BIFP2_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT 0x1
+#define BIFP2_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT 0x2
+#define BIFP2_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT 0x3
+#define BIFP2_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT 0x4
+#define BIFP2_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT 0x5
+#define BIFP2_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT 0x6
+#define BIFP2_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT 0x7
+#define BIFP2_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT 0x8
+#define BIFP2_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT 0x9
+#define BIFP2_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT 0xa
+#define BIFP2_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT 0xb
+#define BIFP2_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT 0xc
+#define BIFP2_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT 0xd
+#define BIFP2_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT 0xe
+#define BIFP2_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT 0xf
+#define BIFP2_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT 0x10
+#define BIFP2_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT 0x11
+#define BIFP2_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT 0x12
+#define BIFP2_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT 0x13
+#define BIFP2_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT 0x14
+#define BIFP2_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT 0x15
+#define BIFP2_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT 0x16
+#define BIFP2_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT 0x17
+#define BIFP2_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT 0x1f
+#define BIFP2_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK 0x00000001L
+#define BIFP2_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK 0x00000002L
+#define BIFP2_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK 0x00000004L
+#define BIFP2_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK 0x00000008L
+#define BIFP2_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK 0x00000010L
+#define BIFP2_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK 0x00000020L
+#define BIFP2_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK 0x00000040L
+#define BIFP2_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK 0x00000080L
+#define BIFP2_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK 0x00000100L
+#define BIFP2_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK 0x00000200L
+#define BIFP2_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK 0x00000400L
+#define BIFP2_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK 0x00000800L
+#define BIFP2_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK 0x00001000L
+#define BIFP2_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK 0x00002000L
+#define BIFP2_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK 0x00004000L
+#define BIFP2_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK 0x00008000L
+#define BIFP2_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK 0x00010000L
+#define BIFP2_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK 0x00020000L
+#define BIFP2_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK 0x00040000L
+#define BIFP2_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK 0x00080000L
+#define BIFP2_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK 0x00100000L
+#define BIFP2_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK 0x00200000L
+#define BIFP2_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK 0x00400000L
+#define BIFP2_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK 0x00800000L
+#define BIFP2_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK 0x80000000L
+//BIFP2_PCIE_LC_SAVE_RESTORE_1
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT 0x0
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT 0x1
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT 0x2
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT 0xa
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT 0xb
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT 0xc
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT 0xd
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT 0xe
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT 0x10
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK 0x00000001L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK 0x00000002L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK 0x000003FCL
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK 0x00000400L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK 0x00000800L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK 0x00001000L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK 0x00002000L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK 0x0000C000L
+#define BIFP2_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK 0xFFFF0000L
+//BIFP2_PCIE_LC_SAVE_RESTORE_2
+#define BIFP2_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT 0x0
+#define BIFP2_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK 0xFFFFFFFFL
+//BIFP2_PCIE_LC_SAVE_RESTORE_3
+#define BIFP2_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT 0x0
+#define BIFP2_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp3_pciedir_p
+//BIFP3_PCIEP_RESERVED
+#define BIFP3_PCIEP_RESERVED__RESERVED__SHIFT 0x0
+#define BIFP3_PCIEP_RESERVED__RESERVED_MASK 0xFFFFFFFFL
+//BIFP3_PCIEP_SCRATCH
+#define BIFP3_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP3_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP3_PCIEP_PORT_CNTL
+#define BIFP3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP3_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP3_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP3_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x1a
+#define BIFP3_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP3_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP3_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP3_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP3_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP3_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x0003FF00L
+#define BIFP3_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP3_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+#define BIFP3_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x0C000000L
+//BIFP3_PCIE_TX_CNTL
+#define BIFP3_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP3_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP3_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP3_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP3_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT 0x1b
+#define BIFP3_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP3_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP3_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP3_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP3_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP3_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP3_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP3_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+#define BIFP3_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK 0x08000000L
+//BIFP3_PCIE_TX_REQUESTER_ID
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP3_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP3_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT 0x18
+#define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP3_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK 0x01000000L
+//BIFP3_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP3_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP3_PCIE_TX_SEQ
+#define BIFP3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP3_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP3_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP3_PCIE_TX_REPLAY
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT 0xe
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK 0x00004000L
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP3_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP3_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP3_PCIE_TX_NOP_DLLP
+#define BIFP3_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT 0x0
+#define BIFP3_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT 0x18
+#define BIFP3_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK 0x00FFFFFFL
+#define BIFP3_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK 0x01000000L
+//BIFP3_PCIE_TX_CNTL_2
+//BIFP3_PCIE_TX_SKID_CTRL
+#define BIFP3_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT 0x0
+#define BIFP3_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT 0x4
+#define BIFP3_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK 0x0000000FL
+#define BIFP3_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK 0x00000010L
+//BIFP3_PCIE_TX_CREDITS_ADVT_P
+#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00003FFFL
+#define BIFP3_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x03FF0000L
+//BIFP3_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00003FFFL
+#define BIFP3_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x03FF0000L
+//BIFP3_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00003FFFL
+#define BIFP3_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x03FF0000L
+//BIFP3_PCIE_TX_CREDITS_INIT_P
+#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP3_PCIE_TX_CREDITS_INIT_NP
+#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP3_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP3_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP3_PCIE_TX_CREDITS_STATUS
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP3_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP3_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT 0x0
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT 0x3
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT 0x6
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT 0x8
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT 0x10
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT 0x19
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT 0x1c
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK 0x00000007L
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK 0x00000038L
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK 0x00000040L
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK 0x00003F00L
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK 0x003F0000L
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK 0x02000000L
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK 0xF0000000L
+//BIFP3_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT 0x0
+#define BIFP3_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK 0x0000FFFFL
+//BIFP3_PCIE_CCIX_STACKED_BASE
+#define BIFP3_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT 0x4
+#define BIFP3_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK 0xFFFFFFF0L
+//BIFP3_PCIE_CCIX_STACKED_LIMIT
+#define BIFP3_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT 0x4
+#define BIFP3_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK 0xFFFFFFF0L
+//BIFP3_PCIE_CCIX_MISC_STATUS
+#define BIFP3_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT 0x0
+#define BIFP3_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT 0x1
+#define BIFP3_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK 0x00000001L
+#define BIFP3_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK 0x00000002L
+//BIFP3_PCIE_P_PORT_LANE_STATUS
+#define BIFP3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP3_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP3_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP3_PCIE_FC_P
+#define BIFP3_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP3_PCIE_FC_P__PH_CREDITS__SHIFT 0x10
+#define BIFP3_PCIE_FC_P__PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP3_PCIE_FC_P__PH_CREDITS_MASK 0x0FFF0000L
+//BIFP3_PCIE_FC_NP
+#define BIFP3_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP3_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x10
+#define BIFP3_PCIE_FC_NP__NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP3_PCIE_FC_NP__NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP3_PCIE_FC_CPL
+#define BIFP3_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP3_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x10
+#define BIFP3_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP3_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP3_PCIE_FC_P_VC1
+#define BIFP3_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT 0x0
+#define BIFP3_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT 0x10
+#define BIFP3_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP3_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK 0x0FFF0000L
+//BIFP3_PCIE_FC_NP_VC1
+#define BIFP3_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT 0x0
+#define BIFP3_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT 0x10
+#define BIFP3_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP3_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP3_PCIE_FC_CPL_VC1
+#define BIFP3_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT 0x0
+#define BIFP3_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT 0x10
+#define BIFP3_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP3_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP3_PCIE_ERR_CNTL
+#define BIFP3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP3_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT 0x13
+#define BIFP3_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT 0x14
+#define BIFP3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP3_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP3_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP3_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP3_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP3_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP3_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP3_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP3_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define BIFP3_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK 0x00080000L
+#define BIFP3_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK 0x00100000L
+//BIFP3_PCIE_RX_CNTL
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP3_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP3_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT 0x1c
+#define BIFP3_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT 0x1d
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP3_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP3_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP3_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP3_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+#define BIFP3_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK 0x10000000L
+#define BIFP3_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK 0x20000000L
+//BIFP3_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP3_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP3_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP3_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP3_PCIE_RX_CNTL3
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP3_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP3_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP3_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP3_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP3_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP3_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP3_PCIEP_NAK_COUNTER
+#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP3_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP3_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP3_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT 0x5
+#define BIFP3_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK 0x00000020L
+//BIFP3_PCIE_AER_PRIV_TRIGGER
+#define BIFP3_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT 0x0
+#define BIFP3_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT 0x1
+#define BIFP3_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT 0x2
+#define BIFP3_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK 0x00000001L
+#define BIFP3_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK 0x00000002L
+#define BIFP3_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK 0x00000004L
+//BIFP3_PCIE_LC_CNTL
+#define BIFP3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP3_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP3_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP3_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP3_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP3_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP3_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP3_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP3_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP3_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP3_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP3_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP3_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP3_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP3_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP3_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP3_PCIE_LC_TRAINING_CNTL
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP3_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP3_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP3_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP3_PCIE_LC_N_FTS_CNTL
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT 0xa
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xe
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT 0xf
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK 0x00000400L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00004000L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK 0x00008000L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP3_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP3_PCIE_LC_SPEED_CNTL
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x3
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x4
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x9
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0xa
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xb
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xd
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xe
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0x10
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x11
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x12
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x13
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x14
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x15
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x16
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT 0x17
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT 0x18
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x19
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x1a
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1c
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1d
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1e
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1f
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000008L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000030L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000400L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00001800L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00002000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x0000C000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00010000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00020000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00040000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00080000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00100000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00200000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00400000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK 0x00800000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK 0x01000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x02000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x0C000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x10000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x20000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x40000000L
+#define BIFP3_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x80000000L
+//BIFP3_PCIE_LC_STATE0
+#define BIFP3_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP3_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP3_PCIE_LC_STATE1
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP3_PCIE_LC_STATE2
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP3_PCIE_LC_STATE3
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP3_PCIE_LC_STATE4
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP3_PCIE_LC_STATE5
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP3_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT 0x5
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT 0x6
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT 0x17
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT 0x1b
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000010L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK 0x00000020L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK 0x00000040L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK 0x07800000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK 0x78000000L
+//BIFP3_PCIE_LC_CNTL2
+#define BIFP3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP3_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x13
+#define BIFP3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP3_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP3_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP3_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP3_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP3_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP3_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP3_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x00080000L
+#define BIFP3_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP3_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP3_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP3_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP3_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP3_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP3_PCIE_LC_CDR_CNTL
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP3_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP3_PCIE_LC_LANE_CNTL
+#define BIFP3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP3_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+//BIFP3_PCIE_LC_CNTL3
+#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP3_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT 0xe
+#define BIFP3_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT 0xf
+#define BIFP3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP3_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP3_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP3_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP3_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP3_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP3_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP3_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP3_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK 0x00001000L
+#define BIFP3_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK 0x00002000L
+#define BIFP3_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK 0x00004000L
+#define BIFP3_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK 0x00008000L
+#define BIFP3_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP3_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP3_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP3_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP3_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP3_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK 0x80000000L
+//BIFP3_PCIE_LC_CNTL4
+#define BIFP3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT 0x5
+#define BIFP3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT 0xb
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT 0xf
+#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT 0x11
+#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP3_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP3_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK 0x00000010L
+#define BIFP3_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK 0x00000020L
+#define BIFP3_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP3_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP3_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK 0x00000300L
+#define BIFP3_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK 0x00000800L
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK 0x00001000L
+#define BIFP3_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP3_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP3_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK 0x00008000L
+#define BIFP3_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK 0x00010000L
+#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK 0x00020000L
+#define BIFP3_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK 0x003C0000L
+#define BIFP3_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP3_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP3_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP3_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP3_PCIE_LC_CNTL5
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT 0xa
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP3_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP3_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK 0x00000003L
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK 0x0000003CL
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK 0x000003C0L
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK 0x0000FC00L
+#define BIFP3_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK 0x001F0000L
+#define BIFP3_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK 0x00C00000L
+#define BIFP3_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP3_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP3_PCIE_LC_FORCE_COEFF
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT 0x0
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT 0x1
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT 0x7
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT 0xd
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT 0x13
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK 0x00000001L
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK 0x0000007EL
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK 0x00001F80L
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK 0x0007E000L
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK 0x00080000L
+#define BIFP3_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP3_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT 0x1e
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+#define BIFP3_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK 0x40000000L
+//BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT 0x0
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT 0x1
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT 0x7
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT 0xd
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT 0x13
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT 0x19
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK 0x00000001L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK 0x0000007EL
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK 0x00001F80L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK 0x0007E000L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK 0x01F80000L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK 0x7E000000L
+//BIFP3_PCIE_LC_CNTL6
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP3_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP3_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000003L
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x0000000CL
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000030L
+#define BIFP3_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK 0x000000C0L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP3_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP3_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP3_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP3_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP3_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP3_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP3_PCIE_LC_CNTL7
+#define BIFP3_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP3_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP3_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP3_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP3_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP3_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP3_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT 0x19
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP3_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP3_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP3_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP3_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP3_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP3_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP3_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP3_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP3_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP3_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP3_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP3_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP3_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK 0x01000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_RATES_MASK 0x06000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP3_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK 0x80000000L
+//BIFP3_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP3_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP3_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT 0x1e
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT 0x1f
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK 0x40000000L
+#define BIFP3_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK 0x80000000L
+//BIFP3_PCIEP_STRAP_LC
+#define BIFP3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP3_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x13
+#define BIFP3_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT 0x14
+#define BIFP3_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT 0x15
+#define BIFP3_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP3_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00080000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK 0x00100000L
+#define BIFP3_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK 0x00200000L
+//BIFP3_PCIEP_STRAP_MISC
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT 0x6
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT 0x7
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK 0x00000040L
+#define BIFP3_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK 0x00000080L
+//BIFP3_PCIEP_STRAP_LC2
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT 0x1
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT 0x3
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT 0x4
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT 0x7
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK 0x00000001L
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK 0x00000006L
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK 0x00000008L
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK 0x00000070L
+#define BIFP3_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK 0x00000380L
+//BIFP3_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT 0x5
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT 0x1a
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT 0x1b
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT 0x1c
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK 0x00000020L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK 0x04000000L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK 0x08000000L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK 0x10000000L
+//BIFP3_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP3_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP3_PCIE_LC_PORT_ORDER
+#define BIFP3_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP3_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP3_PCIEP_BCH_ECC_CNTL
+#define BIFP3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP3_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP3_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP3_PCIEP_HPGI_PRIVATE
+#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP3_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP3_PCIEP_HPGI
+#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP3_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP3_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP3_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP3_PCIEP_HCNT_DESCRIPTOR
+#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x00001FFFL
+#define BIFP3_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP3_PCIE_LC_CNTL8
+#define BIFP3_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT 0x3
+#define BIFP3_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT 0x7
+#define BIFP3_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT 0x9
+#define BIFP3_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT 0xa
+#define BIFP3_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT 0xb
+#define BIFP3_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT 0x11
+#define BIFP3_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT 0x19
+#define BIFP3_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1b
+#define BIFP3_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT 0x1c
+#define BIFP3_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x1d
+#define BIFP3_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x1e
+#define BIFP3_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK 0x00000003L
+#define BIFP3_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK 0x00000004L
+#define BIFP3_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK 0x00000078L
+#define BIFP3_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK 0x00000080L
+#define BIFP3_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK 0x00000100L
+#define BIFP3_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK 0x00000200L
+#define BIFP3_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK 0x00000400L
+#define BIFP3_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK 0x00000800L
+#define BIFP3_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK 0x00001000L
+#define BIFP3_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK 0x0001E000L
+#define BIFP3_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK 0x00020000L
+#define BIFP3_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK 0x003C0000L
+#define BIFP3_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL8__LC_FOM_TIME_MASK 0x01800000L
+#define BIFP3_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK 0x02000000L
+#define BIFP3_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x04000000L
+#define BIFP3_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x08000000L
+#define BIFP3_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK 0x10000000L
+#define BIFP3_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x20000000L
+#define BIFP3_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0xC0000000L
+//BIFP3_PCIE_LC_CNTL9
+#define BIFP3_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT 0x1
+#define BIFP3_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT 0x3
+#define BIFP3_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT 0xa
+#define BIFP3_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT 0xb
+#define BIFP3_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT 0xe
+#define BIFP3_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT 0x19
+#define BIFP3_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT 0x1b
+#define BIFP3_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT 0x1c
+#define BIFP3_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT 0x1d
+#define BIFP3_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT 0x1e
+#define BIFP3_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK 0x00000001L
+#define BIFP3_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK 0x00000006L
+#define BIFP3_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK 0x00000008L
+#define BIFP3_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK 0x00000030L
+#define BIFP3_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK 0x000000C0L
+#define BIFP3_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK 0x00000300L
+#define BIFP3_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK 0x00000400L
+#define BIFP3_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK 0x00000800L
+#define BIFP3_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK 0x00001000L
+#define BIFP3_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK 0x00002000L
+#define BIFP3_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK 0x00FFC000L
+#define BIFP3_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK 0x01000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK 0x02000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK 0x04000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK 0x08000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK 0x10000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK 0x20000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK 0x40000000L
+#define BIFP3_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK 0x80000000L
+//BIFP3_PCIE_LC_FORCE_COEFF2
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT 0x0
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT 0x1
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT 0x7
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT 0xd
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT 0x13
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK 0x00000001L
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK 0x0000007EL
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK 0x00001F80L
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK 0x0007E000L
+#define BIFP3_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK 0x00080000L
+//BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT 0x0
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT 0x1
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT 0x7
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT 0xd
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT 0x13
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT 0x19
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK 0x00000001L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK 0x0000007EL
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK 0x00001F80L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK 0x0007E000L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK 0x01F80000L
+#define BIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK 0x7E000000L
+//BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT 0x0
+#define BIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT 0x1
+#define BIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK 0x00000001L
+#define BIFP3_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK 0x00000002L
+//BIFP3_PCIE_LC_CNTL10
+#define BIFP3_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT 0x1
+#define BIFP3_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT 0x1b
+#define BIFP3_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT 0x1d
+#define BIFP3_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT 0x1e
+#define BIFP3_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK 0x00000001L
+#define BIFP3_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK 0x00000002L
+#define BIFP3_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK 0x0000000CL
+#define BIFP3_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK 0x00000030L
+#define BIFP3_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK 0x0000FFC0L
+#define BIFP3_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK 0x03FF0000L
+#define BIFP3_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK 0x04000000L
+#define BIFP3_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK 0x18000000L
+#define BIFP3_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK 0x20000000L
+#define BIFP3_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK 0x40000000L
+#define BIFP3_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK 0x80000000L
+//BIFP3_PCIE_LC_CNTL11
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT 0x1
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT 0x3
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT 0x5
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT 0x9
+#define BIFP3_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT 0xe
+#define BIFP3_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT 0xf
+#define BIFP3_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT 0x11
+#define BIFP3_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT 0x13
+#define BIFP3_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT 0x14
+#define BIFP3_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT 0x18
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT 0x1a
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT 0x1b
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT 0x1c
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT 0x1e
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK 0x00000002L
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK 0x00000004L
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK 0x00000018L
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK 0x000001E0L
+#define BIFP3_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK 0x00001E00L
+#define BIFP3_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK 0x00002000L
+#define BIFP3_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK 0x00004000L
+#define BIFP3_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK 0x00008000L
+#define BIFP3_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK 0x00010000L
+#define BIFP3_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK 0x00020000L
+#define BIFP3_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK 0x00040000L
+#define BIFP3_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK 0x00080000L
+#define BIFP3_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK 0x00100000L
+#define BIFP3_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_EN_MASK 0x00800000L
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK 0x03000000L
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK 0x04000000L
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK 0x08000000L
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK 0x30000000L
+#define BIFP3_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK 0xC0000000L
+//BIFP3_PCIE_LC_CNTL12
+#define BIFP3_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT 0x0
+#define BIFP3_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT 0x1
+#define BIFP3_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT 0x2
+#define BIFP3_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT 0x3
+#define BIFP3_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT 0x4
+#define BIFP3_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT 0x5
+#define BIFP3_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT 0x6
+#define BIFP3_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT 0x7
+#define BIFP3_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT 0x8
+#define BIFP3_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT 0x9
+#define BIFP3_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT 0xa
+#define BIFP3_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT 0xb
+#define BIFP3_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT 0xc
+#define BIFP3_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT 0xd
+#define BIFP3_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT 0xe
+#define BIFP3_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT 0xf
+#define BIFP3_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT 0x10
+#define BIFP3_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT 0x11
+#define BIFP3_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT 0x12
+#define BIFP3_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT 0x13
+#define BIFP3_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT 0x14
+#define BIFP3_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT 0x15
+#define BIFP3_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT 0x16
+#define BIFP3_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT 0x17
+#define BIFP3_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT 0x1f
+#define BIFP3_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK 0x00000001L
+#define BIFP3_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK 0x00000002L
+#define BIFP3_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK 0x00000004L
+#define BIFP3_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK 0x00000008L
+#define BIFP3_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK 0x00000010L
+#define BIFP3_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK 0x00000020L
+#define BIFP3_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK 0x00000040L
+#define BIFP3_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK 0x00000080L
+#define BIFP3_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK 0x00000100L
+#define BIFP3_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK 0x00000200L
+#define BIFP3_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK 0x00000400L
+#define BIFP3_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK 0x00000800L
+#define BIFP3_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK 0x00001000L
+#define BIFP3_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK 0x00002000L
+#define BIFP3_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK 0x00004000L
+#define BIFP3_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK 0x00008000L
+#define BIFP3_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK 0x00010000L
+#define BIFP3_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK 0x00020000L
+#define BIFP3_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK 0x00040000L
+#define BIFP3_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK 0x00080000L
+#define BIFP3_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK 0x00100000L
+#define BIFP3_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK 0x00200000L
+#define BIFP3_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK 0x00400000L
+#define BIFP3_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK 0x00800000L
+#define BIFP3_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK 0x80000000L
+//BIFP3_PCIE_LC_SAVE_RESTORE_1
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT 0x0
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT 0x1
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT 0x2
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT 0xa
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT 0xb
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT 0xc
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT 0xd
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT 0xe
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT 0x10
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK 0x00000001L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK 0x00000002L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK 0x000003FCL
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK 0x00000400L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK 0x00000800L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK 0x00001000L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK 0x00002000L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK 0x0000C000L
+#define BIFP3_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK 0xFFFF0000L
+//BIFP3_PCIE_LC_SAVE_RESTORE_2
+#define BIFP3_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT 0x0
+#define BIFP3_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK 0xFFFFFFFFL
+//BIFP3_PCIE_LC_SAVE_RESTORE_3
+#define BIFP3_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT 0x0
+#define BIFP3_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp4_pciedir_p
+//BIFP4_PCIEP_RESERVED
+#define BIFP4_PCIEP_RESERVED__RESERVED__SHIFT 0x0
+#define BIFP4_PCIEP_RESERVED__RESERVED_MASK 0xFFFFFFFFL
+//BIFP4_PCIEP_SCRATCH
+#define BIFP4_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP4_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP4_PCIEP_PORT_CNTL
+#define BIFP4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP4_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP4_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP4_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x1a
+#define BIFP4_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP4_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP4_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP4_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP4_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP4_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x0003FF00L
+#define BIFP4_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP4_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+#define BIFP4_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x0C000000L
+//BIFP4_PCIE_TX_CNTL
+#define BIFP4_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP4_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP4_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP4_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP4_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT 0x1b
+#define BIFP4_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP4_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP4_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP4_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP4_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP4_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP4_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP4_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+#define BIFP4_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK 0x08000000L
+//BIFP4_PCIE_TX_REQUESTER_ID
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP4_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP4_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT 0x18
+#define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP4_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK 0x01000000L
+//BIFP4_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP4_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP4_PCIE_TX_SEQ
+#define BIFP4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP4_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP4_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP4_PCIE_TX_REPLAY
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT 0xe
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK 0x00004000L
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP4_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP4_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP4_PCIE_TX_NOP_DLLP
+#define BIFP4_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT 0x0
+#define BIFP4_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT 0x18
+#define BIFP4_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK 0x00FFFFFFL
+#define BIFP4_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK 0x01000000L
+//BIFP4_PCIE_TX_CNTL_2
+//BIFP4_PCIE_TX_SKID_CTRL
+#define BIFP4_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT 0x0
+#define BIFP4_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT 0x4
+#define BIFP4_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK 0x0000000FL
+#define BIFP4_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK 0x00000010L
+//BIFP4_PCIE_TX_CREDITS_ADVT_P
+#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00003FFFL
+#define BIFP4_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x03FF0000L
+//BIFP4_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00003FFFL
+#define BIFP4_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x03FF0000L
+//BIFP4_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00003FFFL
+#define BIFP4_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x03FF0000L
+//BIFP4_PCIE_TX_CREDITS_INIT_P
+#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP4_PCIE_TX_CREDITS_INIT_NP
+#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP4_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP4_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP4_PCIE_TX_CREDITS_STATUS
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP4_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP4_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT 0x0
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT 0x3
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT 0x6
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT 0x8
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT 0x10
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT 0x19
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT 0x1c
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK 0x00000007L
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK 0x00000038L
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK 0x00000040L
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK 0x00003F00L
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK 0x003F0000L
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK 0x02000000L
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK 0xF0000000L
+//BIFP4_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT 0x0
+#define BIFP4_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK 0x0000FFFFL
+//BIFP4_PCIE_CCIX_STACKED_BASE
+#define BIFP4_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT 0x4
+#define BIFP4_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK 0xFFFFFFF0L
+//BIFP4_PCIE_CCIX_STACKED_LIMIT
+#define BIFP4_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT 0x4
+#define BIFP4_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK 0xFFFFFFF0L
+//BIFP4_PCIE_CCIX_MISC_STATUS
+#define BIFP4_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT 0x0
+#define BIFP4_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT 0x1
+#define BIFP4_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK 0x00000001L
+#define BIFP4_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK 0x00000002L
+//BIFP4_PCIE_P_PORT_LANE_STATUS
+#define BIFP4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP4_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP4_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP4_PCIE_FC_P
+#define BIFP4_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP4_PCIE_FC_P__PH_CREDITS__SHIFT 0x10
+#define BIFP4_PCIE_FC_P__PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP4_PCIE_FC_P__PH_CREDITS_MASK 0x0FFF0000L
+//BIFP4_PCIE_FC_NP
+#define BIFP4_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP4_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x10
+#define BIFP4_PCIE_FC_NP__NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP4_PCIE_FC_NP__NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP4_PCIE_FC_CPL
+#define BIFP4_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP4_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x10
+#define BIFP4_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP4_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP4_PCIE_FC_P_VC1
+#define BIFP4_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT 0x0
+#define BIFP4_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT 0x10
+#define BIFP4_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP4_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK 0x0FFF0000L
+//BIFP4_PCIE_FC_NP_VC1
+#define BIFP4_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT 0x0
+#define BIFP4_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT 0x10
+#define BIFP4_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP4_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP4_PCIE_FC_CPL_VC1
+#define BIFP4_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT 0x0
+#define BIFP4_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT 0x10
+#define BIFP4_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP4_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP4_PCIE_ERR_CNTL
+#define BIFP4_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP4_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT 0x13
+#define BIFP4_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT 0x14
+#define BIFP4_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP4_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP4_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP4_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP4_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP4_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP4_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP4_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP4_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP4_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP4_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define BIFP4_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK 0x00080000L
+#define BIFP4_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK 0x00100000L
+//BIFP4_PCIE_RX_CNTL
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP4_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP4_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT 0x1c
+#define BIFP4_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT 0x1d
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP4_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP4_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP4_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP4_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP4_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP4_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+#define BIFP4_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK 0x10000000L
+#define BIFP4_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK 0x20000000L
+//BIFP4_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP4_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP4_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP4_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP4_PCIE_RX_CNTL3
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP4_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP4_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP4_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP4_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP4_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP4_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP4_PCIEP_NAK_COUNTER
+#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP4_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP4_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP4_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT 0x5
+#define BIFP4_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK 0x00000020L
+//BIFP4_PCIE_AER_PRIV_TRIGGER
+#define BIFP4_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT 0x0
+#define BIFP4_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT 0x1
+#define BIFP4_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT 0x2
+#define BIFP4_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK 0x00000001L
+#define BIFP4_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK 0x00000002L
+#define BIFP4_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK 0x00000004L
+//BIFP4_PCIE_LC_CNTL
+#define BIFP4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP4_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP4_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP4_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP4_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP4_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP4_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP4_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP4_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP4_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP4_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP4_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP4_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP4_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP4_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP4_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP4_PCIE_LC_TRAINING_CNTL
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP4_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP4_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP4_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP4_PCIE_LC_N_FTS_CNTL
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT 0xa
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xe
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT 0xf
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK 0x00000400L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00004000L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK 0x00008000L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP4_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP4_PCIE_LC_SPEED_CNTL
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x3
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x4
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x9
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0xa
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xb
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xd
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xe
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0x10
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x11
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x12
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x13
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x14
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x15
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x16
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT 0x17
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT 0x18
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x19
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x1a
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1c
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1d
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1e
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1f
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000008L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000030L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000400L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00001800L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00002000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x0000C000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00010000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00020000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00040000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00080000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00100000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00200000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00400000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK 0x00800000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK 0x01000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x02000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x0C000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x10000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x20000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x40000000L
+#define BIFP4_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x80000000L
+//BIFP4_PCIE_LC_STATE0
+#define BIFP4_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP4_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP4_PCIE_LC_STATE1
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP4_PCIE_LC_STATE2
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP4_PCIE_LC_STATE3
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP4_PCIE_LC_STATE4
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP4_PCIE_LC_STATE5
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP4_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT 0x5
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT 0x6
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT 0x17
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT 0x1b
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000010L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK 0x00000020L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK 0x00000040L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK 0x07800000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK 0x78000000L
+//BIFP4_PCIE_LC_CNTL2
+#define BIFP4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP4_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x13
+#define BIFP4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP4_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP4_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP4_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP4_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP4_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP4_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP4_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x00080000L
+#define BIFP4_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP4_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP4_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP4_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP4_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP4_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP4_PCIE_LC_CDR_CNTL
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP4_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP4_PCIE_LC_LANE_CNTL
+#define BIFP4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP4_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+//BIFP4_PCIE_LC_CNTL3
+#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP4_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT 0xe
+#define BIFP4_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT 0xf
+#define BIFP4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP4_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP4_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP4_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP4_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP4_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP4_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP4_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP4_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK 0x00001000L
+#define BIFP4_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK 0x00002000L
+#define BIFP4_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK 0x00004000L
+#define BIFP4_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK 0x00008000L
+#define BIFP4_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP4_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP4_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP4_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP4_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP4_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK 0x80000000L
+//BIFP4_PCIE_LC_CNTL4
+#define BIFP4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT 0x5
+#define BIFP4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT 0xb
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT 0xf
+#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT 0x11
+#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP4_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP4_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK 0x00000010L
+#define BIFP4_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK 0x00000020L
+#define BIFP4_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP4_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP4_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK 0x00000300L
+#define BIFP4_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK 0x00000800L
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK 0x00001000L
+#define BIFP4_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP4_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP4_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK 0x00008000L
+#define BIFP4_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK 0x00010000L
+#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK 0x00020000L
+#define BIFP4_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK 0x003C0000L
+#define BIFP4_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP4_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP4_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP4_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP4_PCIE_LC_CNTL5
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT 0xa
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP4_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP4_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK 0x00000003L
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK 0x0000003CL
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK 0x000003C0L
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK 0x0000FC00L
+#define BIFP4_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK 0x001F0000L
+#define BIFP4_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK 0x00C00000L
+#define BIFP4_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP4_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP4_PCIE_LC_FORCE_COEFF
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT 0x0
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT 0x1
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT 0x7
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT 0xd
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT 0x13
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK 0x00000001L
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK 0x0000007EL
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK 0x00001F80L
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK 0x0007E000L
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK 0x00080000L
+#define BIFP4_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP4_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT 0x1e
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+#define BIFP4_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK 0x40000000L
+//BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT 0x0
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT 0x1
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT 0x7
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT 0xd
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT 0x13
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT 0x19
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK 0x00000001L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK 0x0000007EL
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK 0x00001F80L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK 0x0007E000L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK 0x01F80000L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK 0x7E000000L
+//BIFP4_PCIE_LC_CNTL6
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP4_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP4_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000003L
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x0000000CL
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000030L
+#define BIFP4_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK 0x000000C0L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP4_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP4_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP4_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP4_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP4_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP4_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP4_PCIE_LC_CNTL7
+#define BIFP4_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP4_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP4_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP4_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP4_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP4_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP4_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT 0x19
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP4_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP4_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP4_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP4_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP4_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP4_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP4_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP4_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP4_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP4_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP4_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP4_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP4_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK 0x01000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_RATES_MASK 0x06000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP4_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK 0x80000000L
+//BIFP4_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP4_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP4_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT 0x1e
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT 0x1f
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK 0x40000000L
+#define BIFP4_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK 0x80000000L
+//BIFP4_PCIEP_STRAP_LC
+#define BIFP4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP4_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x13
+#define BIFP4_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT 0x14
+#define BIFP4_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT 0x15
+#define BIFP4_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP4_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00080000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK 0x00100000L
+#define BIFP4_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK 0x00200000L
+//BIFP4_PCIEP_STRAP_MISC
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT 0x6
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT 0x7
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK 0x00000040L
+#define BIFP4_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK 0x00000080L
+//BIFP4_PCIEP_STRAP_LC2
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT 0x1
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT 0x3
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT 0x4
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT 0x7
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK 0x00000001L
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK 0x00000006L
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK 0x00000008L
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK 0x00000070L
+#define BIFP4_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK 0x00000380L
+//BIFP4_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT 0x5
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT 0x1a
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT 0x1b
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT 0x1c
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK 0x00000020L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK 0x04000000L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK 0x08000000L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK 0x10000000L
+//BIFP4_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP4_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP4_PCIE_LC_PORT_ORDER
+#define BIFP4_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP4_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP4_PCIEP_BCH_ECC_CNTL
+#define BIFP4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP4_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP4_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP4_PCIEP_HPGI_PRIVATE
+#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP4_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP4_PCIEP_HPGI
+#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP4_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP4_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP4_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP4_PCIEP_HCNT_DESCRIPTOR
+#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x00001FFFL
+#define BIFP4_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP4_PCIE_LC_CNTL8
+#define BIFP4_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT 0x3
+#define BIFP4_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT 0x7
+#define BIFP4_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT 0x9
+#define BIFP4_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT 0xa
+#define BIFP4_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT 0xb
+#define BIFP4_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT 0x11
+#define BIFP4_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT 0x19
+#define BIFP4_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1b
+#define BIFP4_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT 0x1c
+#define BIFP4_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x1d
+#define BIFP4_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x1e
+#define BIFP4_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK 0x00000003L
+#define BIFP4_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK 0x00000004L
+#define BIFP4_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK 0x00000078L
+#define BIFP4_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK 0x00000080L
+#define BIFP4_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK 0x00000100L
+#define BIFP4_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK 0x00000200L
+#define BIFP4_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK 0x00000400L
+#define BIFP4_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK 0x00000800L
+#define BIFP4_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK 0x00001000L
+#define BIFP4_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK 0x0001E000L
+#define BIFP4_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK 0x00020000L
+#define BIFP4_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK 0x003C0000L
+#define BIFP4_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL8__LC_FOM_TIME_MASK 0x01800000L
+#define BIFP4_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK 0x02000000L
+#define BIFP4_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x04000000L
+#define BIFP4_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x08000000L
+#define BIFP4_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK 0x10000000L
+#define BIFP4_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x20000000L
+#define BIFP4_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0xC0000000L
+//BIFP4_PCIE_LC_CNTL9
+#define BIFP4_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT 0x1
+#define BIFP4_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT 0x3
+#define BIFP4_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT 0xa
+#define BIFP4_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT 0xb
+#define BIFP4_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT 0xe
+#define BIFP4_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT 0x19
+#define BIFP4_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT 0x1b
+#define BIFP4_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT 0x1c
+#define BIFP4_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT 0x1d
+#define BIFP4_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT 0x1e
+#define BIFP4_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK 0x00000001L
+#define BIFP4_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK 0x00000006L
+#define BIFP4_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK 0x00000008L
+#define BIFP4_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK 0x00000030L
+#define BIFP4_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK 0x000000C0L
+#define BIFP4_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK 0x00000300L
+#define BIFP4_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK 0x00000400L
+#define BIFP4_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK 0x00000800L
+#define BIFP4_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK 0x00001000L
+#define BIFP4_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK 0x00002000L
+#define BIFP4_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK 0x00FFC000L
+#define BIFP4_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK 0x01000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK 0x02000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK 0x04000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK 0x08000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK 0x10000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK 0x20000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK 0x40000000L
+#define BIFP4_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK 0x80000000L
+//BIFP4_PCIE_LC_FORCE_COEFF2
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT 0x0
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT 0x1
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT 0x7
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT 0xd
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT 0x13
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK 0x00000001L
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK 0x0000007EL
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK 0x00001F80L
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK 0x0007E000L
+#define BIFP4_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK 0x00080000L
+//BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT 0x0
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT 0x1
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT 0x7
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT 0xd
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT 0x13
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT 0x19
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK 0x00000001L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK 0x0000007EL
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK 0x00001F80L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK 0x0007E000L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK 0x01F80000L
+#define BIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK 0x7E000000L
+//BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT 0x0
+#define BIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT 0x1
+#define BIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK 0x00000001L
+#define BIFP4_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK 0x00000002L
+//BIFP4_PCIE_LC_CNTL10
+#define BIFP4_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT 0x1
+#define BIFP4_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT 0x1b
+#define BIFP4_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT 0x1d
+#define BIFP4_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT 0x1e
+#define BIFP4_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK 0x00000001L
+#define BIFP4_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK 0x00000002L
+#define BIFP4_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK 0x0000000CL
+#define BIFP4_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK 0x00000030L
+#define BIFP4_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK 0x0000FFC0L
+#define BIFP4_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK 0x03FF0000L
+#define BIFP4_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK 0x04000000L
+#define BIFP4_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK 0x18000000L
+#define BIFP4_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK 0x20000000L
+#define BIFP4_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK 0x40000000L
+#define BIFP4_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK 0x80000000L
+//BIFP4_PCIE_LC_CNTL11
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT 0x1
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT 0x3
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT 0x5
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT 0x9
+#define BIFP4_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT 0xe
+#define BIFP4_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT 0xf
+#define BIFP4_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT 0x11
+#define BIFP4_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT 0x13
+#define BIFP4_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT 0x14
+#define BIFP4_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT 0x18
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT 0x1a
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT 0x1b
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT 0x1c
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT 0x1e
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK 0x00000002L
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK 0x00000004L
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK 0x00000018L
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK 0x000001E0L
+#define BIFP4_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK 0x00001E00L
+#define BIFP4_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK 0x00002000L
+#define BIFP4_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK 0x00004000L
+#define BIFP4_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK 0x00008000L
+#define BIFP4_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK 0x00010000L
+#define BIFP4_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK 0x00020000L
+#define BIFP4_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK 0x00040000L
+#define BIFP4_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK 0x00080000L
+#define BIFP4_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK 0x00100000L
+#define BIFP4_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_EN_MASK 0x00800000L
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK 0x03000000L
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK 0x04000000L
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK 0x08000000L
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK 0x30000000L
+#define BIFP4_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK 0xC0000000L
+//BIFP4_PCIE_LC_CNTL12
+#define BIFP4_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT 0x0
+#define BIFP4_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT 0x1
+#define BIFP4_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT 0x2
+#define BIFP4_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT 0x3
+#define BIFP4_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT 0x4
+#define BIFP4_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT 0x5
+#define BIFP4_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT 0x6
+#define BIFP4_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT 0x7
+#define BIFP4_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT 0x8
+#define BIFP4_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT 0x9
+#define BIFP4_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT 0xa
+#define BIFP4_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT 0xb
+#define BIFP4_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT 0xc
+#define BIFP4_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT 0xd
+#define BIFP4_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT 0xe
+#define BIFP4_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT 0xf
+#define BIFP4_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT 0x10
+#define BIFP4_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT 0x11
+#define BIFP4_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT 0x12
+#define BIFP4_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT 0x13
+#define BIFP4_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT 0x14
+#define BIFP4_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT 0x15
+#define BIFP4_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT 0x16
+#define BIFP4_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT 0x17
+#define BIFP4_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT 0x1f
+#define BIFP4_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK 0x00000001L
+#define BIFP4_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK 0x00000002L
+#define BIFP4_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK 0x00000004L
+#define BIFP4_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK 0x00000008L
+#define BIFP4_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK 0x00000010L
+#define BIFP4_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK 0x00000020L
+#define BIFP4_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK 0x00000040L
+#define BIFP4_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK 0x00000080L
+#define BIFP4_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK 0x00000100L
+#define BIFP4_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK 0x00000200L
+#define BIFP4_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK 0x00000400L
+#define BIFP4_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK 0x00000800L
+#define BIFP4_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK 0x00001000L
+#define BIFP4_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK 0x00002000L
+#define BIFP4_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK 0x00004000L
+#define BIFP4_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK 0x00008000L
+#define BIFP4_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK 0x00010000L
+#define BIFP4_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK 0x00020000L
+#define BIFP4_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK 0x00040000L
+#define BIFP4_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK 0x00080000L
+#define BIFP4_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK 0x00100000L
+#define BIFP4_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK 0x00200000L
+#define BIFP4_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK 0x00400000L
+#define BIFP4_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK 0x00800000L
+#define BIFP4_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK 0x80000000L
+//BIFP4_PCIE_LC_SAVE_RESTORE_1
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT 0x0
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT 0x1
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT 0x2
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT 0xa
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT 0xb
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT 0xc
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT 0xd
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT 0xe
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT 0x10
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK 0x00000001L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK 0x00000002L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK 0x000003FCL
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK 0x00000400L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK 0x00000800L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK 0x00001000L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK 0x00002000L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK 0x0000C000L
+#define BIFP4_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK 0xFFFF0000L
+//BIFP4_PCIE_LC_SAVE_RESTORE_2
+#define BIFP4_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT 0x0
+#define BIFP4_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK 0xFFFFFFFFL
+//BIFP4_PCIE_LC_SAVE_RESTORE_3
+#define BIFP4_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT 0x0
+#define BIFP4_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp5_pciedir_p
+//BIFP5_PCIEP_RESERVED
+#define BIFP5_PCIEP_RESERVED__RESERVED__SHIFT 0x0
+#define BIFP5_PCIEP_RESERVED__RESERVED_MASK 0xFFFFFFFFL
+//BIFP5_PCIEP_SCRATCH
+#define BIFP5_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP5_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP5_PCIEP_PORT_CNTL
+#define BIFP5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP5_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP5_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP5_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x1a
+#define BIFP5_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP5_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP5_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP5_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP5_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP5_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x0003FF00L
+#define BIFP5_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP5_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+#define BIFP5_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x0C000000L
+//BIFP5_PCIE_TX_CNTL
+#define BIFP5_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP5_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP5_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP5_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP5_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT 0x1b
+#define BIFP5_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP5_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP5_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP5_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP5_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP5_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP5_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP5_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+#define BIFP5_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK 0x08000000L
+//BIFP5_PCIE_TX_REQUESTER_ID
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP5_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP5_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT 0x18
+#define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP5_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK 0x01000000L
+//BIFP5_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP5_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP5_PCIE_TX_SEQ
+#define BIFP5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP5_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP5_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP5_PCIE_TX_REPLAY
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT 0xe
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK 0x00004000L
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP5_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP5_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP5_PCIE_TX_NOP_DLLP
+#define BIFP5_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT 0x0
+#define BIFP5_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT 0x18
+#define BIFP5_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK 0x00FFFFFFL
+#define BIFP5_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK 0x01000000L
+//BIFP5_PCIE_TX_CNTL_2
+//BIFP5_PCIE_TX_SKID_CTRL
+#define BIFP5_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT 0x0
+#define BIFP5_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT 0x4
+#define BIFP5_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK 0x0000000FL
+#define BIFP5_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK 0x00000010L
+//BIFP5_PCIE_TX_CREDITS_ADVT_P
+#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00003FFFL
+#define BIFP5_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x03FF0000L
+//BIFP5_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00003FFFL
+#define BIFP5_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x03FF0000L
+//BIFP5_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00003FFFL
+#define BIFP5_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x03FF0000L
+//BIFP5_PCIE_TX_CREDITS_INIT_P
+#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP5_PCIE_TX_CREDITS_INIT_NP
+#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP5_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP5_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP5_PCIE_TX_CREDITS_STATUS
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP5_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP5_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT 0x0
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT 0x3
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT 0x6
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT 0x8
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT 0x10
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT 0x19
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT 0x1c
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK 0x00000007L
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK 0x00000038L
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK 0x00000040L
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK 0x00003F00L
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK 0x003F0000L
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK 0x02000000L
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK 0xF0000000L
+//BIFP5_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT 0x0
+#define BIFP5_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK 0x0000FFFFL
+//BIFP5_PCIE_CCIX_STACKED_BASE
+#define BIFP5_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT 0x4
+#define BIFP5_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK 0xFFFFFFF0L
+//BIFP5_PCIE_CCIX_STACKED_LIMIT
+#define BIFP5_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT 0x4
+#define BIFP5_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK 0xFFFFFFF0L
+//BIFP5_PCIE_CCIX_MISC_STATUS
+#define BIFP5_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT 0x0
+#define BIFP5_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT 0x1
+#define BIFP5_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK 0x00000001L
+#define BIFP5_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK 0x00000002L
+//BIFP5_PCIE_P_PORT_LANE_STATUS
+#define BIFP5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP5_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP5_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP5_PCIE_FC_P
+#define BIFP5_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP5_PCIE_FC_P__PH_CREDITS__SHIFT 0x10
+#define BIFP5_PCIE_FC_P__PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP5_PCIE_FC_P__PH_CREDITS_MASK 0x0FFF0000L
+//BIFP5_PCIE_FC_NP
+#define BIFP5_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP5_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x10
+#define BIFP5_PCIE_FC_NP__NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP5_PCIE_FC_NP__NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP5_PCIE_FC_CPL
+#define BIFP5_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP5_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x10
+#define BIFP5_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP5_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP5_PCIE_FC_P_VC1
+#define BIFP5_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT 0x0
+#define BIFP5_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT 0x10
+#define BIFP5_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP5_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK 0x0FFF0000L
+//BIFP5_PCIE_FC_NP_VC1
+#define BIFP5_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT 0x0
+#define BIFP5_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT 0x10
+#define BIFP5_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP5_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP5_PCIE_FC_CPL_VC1
+#define BIFP5_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT 0x0
+#define BIFP5_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT 0x10
+#define BIFP5_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP5_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP5_PCIE_ERR_CNTL
+#define BIFP5_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP5_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT 0x13
+#define BIFP5_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT 0x14
+#define BIFP5_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP5_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP5_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP5_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP5_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP5_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP5_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP5_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP5_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP5_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP5_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define BIFP5_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK 0x00080000L
+#define BIFP5_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK 0x00100000L
+//BIFP5_PCIE_RX_CNTL
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP5_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP5_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT 0x1c
+#define BIFP5_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT 0x1d
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP5_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP5_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP5_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP5_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP5_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP5_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+#define BIFP5_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK 0x10000000L
+#define BIFP5_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK 0x20000000L
+//BIFP5_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP5_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP5_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP5_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP5_PCIE_RX_CNTL3
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP5_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP5_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP5_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP5_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP5_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP5_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP5_PCIEP_NAK_COUNTER
+#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP5_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP5_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP5_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT 0x5
+#define BIFP5_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK 0x00000020L
+//BIFP5_PCIE_AER_PRIV_TRIGGER
+#define BIFP5_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT 0x0
+#define BIFP5_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT 0x1
+#define BIFP5_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT 0x2
+#define BIFP5_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK 0x00000001L
+#define BIFP5_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK 0x00000002L
+#define BIFP5_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK 0x00000004L
+//BIFP5_PCIE_LC_CNTL
+#define BIFP5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP5_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP5_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP5_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP5_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP5_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP5_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP5_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP5_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP5_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP5_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP5_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP5_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP5_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP5_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP5_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP5_PCIE_LC_TRAINING_CNTL
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP5_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP5_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP5_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP5_PCIE_LC_N_FTS_CNTL
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT 0xa
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xe
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT 0xf
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK 0x00000400L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00004000L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK 0x00008000L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP5_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP5_PCIE_LC_SPEED_CNTL
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x3
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x4
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x9
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0xa
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xb
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xd
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xe
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0x10
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x11
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x12
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x13
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x14
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x15
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x16
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT 0x17
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT 0x18
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x19
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x1a
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1c
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1d
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1e
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1f
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000008L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000030L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000400L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00001800L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00002000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x0000C000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00010000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00020000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00040000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00080000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00100000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00200000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00400000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK 0x00800000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK 0x01000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x02000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x0C000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x10000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x20000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x40000000L
+#define BIFP5_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x80000000L
+//BIFP5_PCIE_LC_STATE0
+#define BIFP5_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP5_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP5_PCIE_LC_STATE1
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP5_PCIE_LC_STATE2
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP5_PCIE_LC_STATE3
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP5_PCIE_LC_STATE4
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP5_PCIE_LC_STATE5
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP5_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT 0x5
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT 0x6
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT 0x17
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT 0x1b
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000010L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK 0x00000020L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK 0x00000040L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK 0x07800000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK 0x78000000L
+//BIFP5_PCIE_LC_CNTL2
+#define BIFP5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP5_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x13
+#define BIFP5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP5_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP5_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP5_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP5_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP5_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP5_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP5_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x00080000L
+#define BIFP5_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP5_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP5_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP5_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP5_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP5_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP5_PCIE_LC_CDR_CNTL
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP5_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP5_PCIE_LC_LANE_CNTL
+#define BIFP5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP5_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+//BIFP5_PCIE_LC_CNTL3
+#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP5_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT 0xe
+#define BIFP5_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT 0xf
+#define BIFP5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP5_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP5_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP5_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP5_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP5_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP5_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP5_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP5_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK 0x00001000L
+#define BIFP5_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK 0x00002000L
+#define BIFP5_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK 0x00004000L
+#define BIFP5_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK 0x00008000L
+#define BIFP5_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP5_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP5_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP5_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP5_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP5_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK 0x80000000L
+//BIFP5_PCIE_LC_CNTL4
+#define BIFP5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT 0x5
+#define BIFP5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT 0xb
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT 0xf
+#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT 0x11
+#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP5_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP5_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK 0x00000010L
+#define BIFP5_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK 0x00000020L
+#define BIFP5_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP5_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP5_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK 0x00000300L
+#define BIFP5_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK 0x00000800L
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK 0x00001000L
+#define BIFP5_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP5_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP5_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK 0x00008000L
+#define BIFP5_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK 0x00010000L
+#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK 0x00020000L
+#define BIFP5_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK 0x003C0000L
+#define BIFP5_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP5_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP5_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP5_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP5_PCIE_LC_CNTL5
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT 0xa
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP5_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP5_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK 0x00000003L
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK 0x0000003CL
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK 0x000003C0L
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK 0x0000FC00L
+#define BIFP5_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK 0x001F0000L
+#define BIFP5_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK 0x00C00000L
+#define BIFP5_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP5_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP5_PCIE_LC_FORCE_COEFF
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT 0x0
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT 0x1
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT 0x7
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT 0xd
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT 0x13
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK 0x00000001L
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK 0x0000007EL
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK 0x00001F80L
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK 0x0007E000L
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK 0x00080000L
+#define BIFP5_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP5_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT 0x1e
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+#define BIFP5_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK 0x40000000L
+//BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT 0x0
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT 0x1
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT 0x7
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT 0xd
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT 0x13
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT 0x19
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK 0x00000001L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK 0x0000007EL
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK 0x00001F80L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK 0x0007E000L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK 0x01F80000L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK 0x7E000000L
+//BIFP5_PCIE_LC_CNTL6
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP5_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP5_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000003L
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x0000000CL
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000030L
+#define BIFP5_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK 0x000000C0L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP5_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP5_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP5_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP5_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP5_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP5_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP5_PCIE_LC_CNTL7
+#define BIFP5_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP5_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP5_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP5_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP5_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP5_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP5_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT 0x19
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP5_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP5_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP5_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP5_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP5_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP5_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP5_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP5_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP5_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP5_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP5_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP5_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP5_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK 0x01000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_RATES_MASK 0x06000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP5_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK 0x80000000L
+//BIFP5_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP5_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP5_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT 0x1e
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT 0x1f
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK 0x40000000L
+#define BIFP5_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK 0x80000000L
+//BIFP5_PCIEP_STRAP_LC
+#define BIFP5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP5_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x13
+#define BIFP5_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT 0x14
+#define BIFP5_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT 0x15
+#define BIFP5_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP5_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00080000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK 0x00100000L
+#define BIFP5_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK 0x00200000L
+//BIFP5_PCIEP_STRAP_MISC
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT 0x6
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT 0x7
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK 0x00000040L
+#define BIFP5_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK 0x00000080L
+//BIFP5_PCIEP_STRAP_LC2
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT 0x1
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT 0x3
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT 0x4
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT 0x7
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK 0x00000001L
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK 0x00000006L
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK 0x00000008L
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK 0x00000070L
+#define BIFP5_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK 0x00000380L
+//BIFP5_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT 0x5
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT 0x1a
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT 0x1b
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT 0x1c
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK 0x00000020L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK 0x04000000L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK 0x08000000L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK 0x10000000L
+//BIFP5_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP5_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP5_PCIE_LC_PORT_ORDER
+#define BIFP5_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP5_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP5_PCIEP_BCH_ECC_CNTL
+#define BIFP5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP5_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP5_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP5_PCIEP_HPGI_PRIVATE
+#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP5_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP5_PCIEP_HPGI
+#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP5_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP5_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP5_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP5_PCIEP_HCNT_DESCRIPTOR
+#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x00001FFFL
+#define BIFP5_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP5_PCIE_LC_CNTL8
+#define BIFP5_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT 0x3
+#define BIFP5_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT 0x7
+#define BIFP5_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT 0x9
+#define BIFP5_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT 0xa
+#define BIFP5_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT 0xb
+#define BIFP5_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT 0x11
+#define BIFP5_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT 0x19
+#define BIFP5_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1b
+#define BIFP5_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT 0x1c
+#define BIFP5_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x1d
+#define BIFP5_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x1e
+#define BIFP5_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK 0x00000003L
+#define BIFP5_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK 0x00000004L
+#define BIFP5_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK 0x00000078L
+#define BIFP5_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK 0x00000080L
+#define BIFP5_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK 0x00000100L
+#define BIFP5_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK 0x00000200L
+#define BIFP5_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK 0x00000400L
+#define BIFP5_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK 0x00000800L
+#define BIFP5_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK 0x00001000L
+#define BIFP5_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK 0x0001E000L
+#define BIFP5_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK 0x00020000L
+#define BIFP5_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK 0x003C0000L
+#define BIFP5_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL8__LC_FOM_TIME_MASK 0x01800000L
+#define BIFP5_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK 0x02000000L
+#define BIFP5_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x04000000L
+#define BIFP5_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x08000000L
+#define BIFP5_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK 0x10000000L
+#define BIFP5_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x20000000L
+#define BIFP5_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0xC0000000L
+//BIFP5_PCIE_LC_CNTL9
+#define BIFP5_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT 0x1
+#define BIFP5_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT 0x3
+#define BIFP5_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT 0xa
+#define BIFP5_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT 0xb
+#define BIFP5_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT 0xe
+#define BIFP5_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT 0x19
+#define BIFP5_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT 0x1b
+#define BIFP5_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT 0x1c
+#define BIFP5_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT 0x1d
+#define BIFP5_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT 0x1e
+#define BIFP5_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK 0x00000001L
+#define BIFP5_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK 0x00000006L
+#define BIFP5_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK 0x00000008L
+#define BIFP5_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK 0x00000030L
+#define BIFP5_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK 0x000000C0L
+#define BIFP5_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK 0x00000300L
+#define BIFP5_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK 0x00000400L
+#define BIFP5_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK 0x00000800L
+#define BIFP5_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK 0x00001000L
+#define BIFP5_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK 0x00002000L
+#define BIFP5_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK 0x00FFC000L
+#define BIFP5_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK 0x01000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK 0x02000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK 0x04000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK 0x08000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK 0x10000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK 0x20000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK 0x40000000L
+#define BIFP5_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK 0x80000000L
+//BIFP5_PCIE_LC_FORCE_COEFF2
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT 0x0
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT 0x1
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT 0x7
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT 0xd
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT 0x13
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK 0x00000001L
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK 0x0000007EL
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK 0x00001F80L
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK 0x0007E000L
+#define BIFP5_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK 0x00080000L
+//BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT 0x0
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT 0x1
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT 0x7
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT 0xd
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT 0x13
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT 0x19
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK 0x00000001L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK 0x0000007EL
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK 0x00001F80L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK 0x0007E000L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK 0x01F80000L
+#define BIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK 0x7E000000L
+//BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT 0x0
+#define BIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT 0x1
+#define BIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK 0x00000001L
+#define BIFP5_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK 0x00000002L
+//BIFP5_PCIE_LC_CNTL10
+#define BIFP5_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT 0x1
+#define BIFP5_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT 0x1b
+#define BIFP5_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT 0x1d
+#define BIFP5_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT 0x1e
+#define BIFP5_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK 0x00000001L
+#define BIFP5_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK 0x00000002L
+#define BIFP5_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK 0x0000000CL
+#define BIFP5_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK 0x00000030L
+#define BIFP5_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK 0x0000FFC0L
+#define BIFP5_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK 0x03FF0000L
+#define BIFP5_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK 0x04000000L
+#define BIFP5_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK 0x18000000L
+#define BIFP5_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK 0x20000000L
+#define BIFP5_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK 0x40000000L
+#define BIFP5_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK 0x80000000L
+//BIFP5_PCIE_LC_CNTL11
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT 0x1
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT 0x3
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT 0x5
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT 0x9
+#define BIFP5_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT 0xe
+#define BIFP5_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT 0xf
+#define BIFP5_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT 0x11
+#define BIFP5_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT 0x13
+#define BIFP5_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT 0x14
+#define BIFP5_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT 0x18
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT 0x1a
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT 0x1b
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT 0x1c
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT 0x1e
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK 0x00000002L
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK 0x00000004L
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK 0x00000018L
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK 0x000001E0L
+#define BIFP5_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK 0x00001E00L
+#define BIFP5_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK 0x00002000L
+#define BIFP5_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK 0x00004000L
+#define BIFP5_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK 0x00008000L
+#define BIFP5_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK 0x00010000L
+#define BIFP5_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK 0x00020000L
+#define BIFP5_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK 0x00040000L
+#define BIFP5_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK 0x00080000L
+#define BIFP5_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK 0x00100000L
+#define BIFP5_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_EN_MASK 0x00800000L
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK 0x03000000L
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK 0x04000000L
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK 0x08000000L
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK 0x30000000L
+#define BIFP5_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK 0xC0000000L
+//BIFP5_PCIE_LC_CNTL12
+#define BIFP5_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT 0x0
+#define BIFP5_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT 0x1
+#define BIFP5_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT 0x2
+#define BIFP5_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT 0x3
+#define BIFP5_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT 0x4
+#define BIFP5_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT 0x5
+#define BIFP5_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT 0x6
+#define BIFP5_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT 0x7
+#define BIFP5_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT 0x8
+#define BIFP5_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT 0x9
+#define BIFP5_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT 0xa
+#define BIFP5_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT 0xb
+#define BIFP5_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT 0xc
+#define BIFP5_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT 0xd
+#define BIFP5_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT 0xe
+#define BIFP5_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT 0xf
+#define BIFP5_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT 0x10
+#define BIFP5_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT 0x11
+#define BIFP5_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT 0x12
+#define BIFP5_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT 0x13
+#define BIFP5_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT 0x14
+#define BIFP5_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT 0x15
+#define BIFP5_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT 0x16
+#define BIFP5_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT 0x17
+#define BIFP5_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT 0x1f
+#define BIFP5_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK 0x00000001L
+#define BIFP5_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK 0x00000002L
+#define BIFP5_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK 0x00000004L
+#define BIFP5_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK 0x00000008L
+#define BIFP5_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK 0x00000010L
+#define BIFP5_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK 0x00000020L
+#define BIFP5_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK 0x00000040L
+#define BIFP5_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK 0x00000080L
+#define BIFP5_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK 0x00000100L
+#define BIFP5_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK 0x00000200L
+#define BIFP5_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK 0x00000400L
+#define BIFP5_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK 0x00000800L
+#define BIFP5_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK 0x00001000L
+#define BIFP5_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK 0x00002000L
+#define BIFP5_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK 0x00004000L
+#define BIFP5_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK 0x00008000L
+#define BIFP5_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK 0x00010000L
+#define BIFP5_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK 0x00020000L
+#define BIFP5_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK 0x00040000L
+#define BIFP5_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK 0x00080000L
+#define BIFP5_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK 0x00100000L
+#define BIFP5_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK 0x00200000L
+#define BIFP5_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK 0x00400000L
+#define BIFP5_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK 0x00800000L
+#define BIFP5_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK 0x80000000L
+//BIFP5_PCIE_LC_SAVE_RESTORE_1
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT 0x0
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT 0x1
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT 0x2
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT 0xa
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT 0xb
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT 0xc
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT 0xd
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT 0xe
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT 0x10
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK 0x00000001L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK 0x00000002L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK 0x000003FCL
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK 0x00000400L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK 0x00000800L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK 0x00001000L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK 0x00002000L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK 0x0000C000L
+#define BIFP5_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK 0xFFFF0000L
+//BIFP5_PCIE_LC_SAVE_RESTORE_2
+#define BIFP5_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT 0x0
+#define BIFP5_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK 0xFFFFFFFFL
+//BIFP5_PCIE_LC_SAVE_RESTORE_3
+#define BIFP5_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT 0x0
+#define BIFP5_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifp6_pciedir_p
+//BIFP6_PCIEP_RESERVED
+#define BIFP6_PCIEP_RESERVED__RESERVED__SHIFT 0x0
+#define BIFP6_PCIEP_RESERVED__RESERVED_MASK 0xFFFFFFFFL
+//BIFP6_PCIEP_SCRATCH
+#define BIFP6_PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0
+#define BIFP6_PCIEP_SCRATCH__PCIEP_SCRATCH_MASK 0xFFFFFFFFL
+//BIFP6_PCIEP_PORT_CNTL
+#define BIFP6_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT 0x0
+#define BIFP6_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT 0x1
+#define BIFP6_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT 0x2
+#define BIFP6_PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT 0x3
+#define BIFP6_PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT 0x4
+#define BIFP6_PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT 0x5
+#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT 0x8
+#define BIFP6_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT 0x12
+#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT 0x18
+#define BIFP6_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT 0x1a
+#define BIFP6_PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK 0x00000001L
+#define BIFP6_PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK 0x00000002L
+#define BIFP6_PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK 0x00000004L
+#define BIFP6_PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK 0x00000008L
+#define BIFP6_PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK 0x00000010L
+#define BIFP6_PCIEP_PORT_CNTL__PMI_BM_DIS_MASK 0x00000020L
+#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK 0x0003FF00L
+#define BIFP6_PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK 0x001C0000L
+#define BIFP6_PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK 0x03000000L
+#define BIFP6_PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK 0x0C000000L
+//BIFP6_PCIE_TX_CNTL
+#define BIFP6_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define BIFP6_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define BIFP6_PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT 0xe
+#define BIFP6_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT 0xf
+#define BIFP6_PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT 0x14
+#define BIFP6_PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT 0x15
+#define BIFP6_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT 0x16
+#define BIFP6_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT 0x17
+#define BIFP6_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE__SHIFT 0x1b
+#define BIFP6_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define BIFP6_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define BIFP6_PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK 0x00004000L
+#define BIFP6_PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK 0x00008000L
+#define BIFP6_PCIE_TX_CNTL__TX_CPL_PASS_P_MASK 0x00100000L
+#define BIFP6_PCIE_TX_CNTL__TX_NP_PASS_P_MASK 0x00200000L
+#define BIFP6_PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK 0x00400000L
+#define BIFP6_PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK 0x00800000L
+#define BIFP6_PCIE_TX_CNTL__TX_SWAP_RTRC_WITH_BFRC_ENABLE_MASK 0x08000000L
+//BIFP6_PCIE_TX_REQUESTER_ID
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define BIFP6_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//BIFP6_PCIE_TX_VENDOR_SPECIFIC
+#define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT 0x0
+#define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND__SHIFT 0x18
+#define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP6_PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_SEND_MASK 0x01000000L
+//BIFP6_PCIE_TX_REQUEST_NUM_CNTL
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT 0x18
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT 0x1e
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT 0x1f
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK 0x3F000000L
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK 0x40000000L
+#define BIFP6_PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK 0x80000000L
+//BIFP6_PCIE_TX_SEQ
+#define BIFP6_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT 0x0
+#define BIFP6_PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT 0x10
+#define BIFP6_PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_SEQ__TX_ACKD_SEQ_MASK 0x0FFF0000L
+//BIFP6_PCIE_TX_REPLAY
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT 0x0
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS__SHIFT 0xe
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT 0xf
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT 0x10
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK 0x00000007L
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_DIS_MASK 0x00004000L
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK 0x00008000L
+#define BIFP6_PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK 0xFFFF0000L
+//BIFP6_PCIE_TX_ACK_LATENCY_LIMIT
+#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT 0x0
+#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT 0xc
+#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK 0x00001000L
+//BIFP6_PCIE_TX_NOP_DLLP
+#define BIFP6_PCIE_TX_NOP_DLLP__TX_NOP_DATA__SHIFT 0x0
+#define BIFP6_PCIE_TX_NOP_DLLP__TX_NOP_SEND__SHIFT 0x18
+#define BIFP6_PCIE_TX_NOP_DLLP__TX_NOP_DATA_MASK 0x00FFFFFFL
+#define BIFP6_PCIE_TX_NOP_DLLP__TX_NOP_SEND_MASK 0x01000000L
+//BIFP6_PCIE_TX_CNTL_2
+//BIFP6_PCIE_TX_SKID_CTRL
+#define BIFP6_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT__SHIFT 0x0
+#define BIFP6_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN__SHIFT 0x4
+#define BIFP6_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_LIMIT_MASK 0x0000000FL
+#define BIFP6_PCIE_TX_SKID_CTRL__TX_SKID_CREDIT_OVERRIDE_EN_MASK 0x00000010L
+//BIFP6_PCIE_TX_CREDITS_ADVT_P
+#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK 0x00003FFFL
+#define BIFP6_PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK 0x03FF0000L
+//BIFP6_PCIE_TX_CREDITS_ADVT_NP
+#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK 0x00003FFFL
+#define BIFP6_PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK 0x03FF0000L
+//BIFP6_PCIE_TX_CREDITS_ADVT_CPL
+#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK 0x00003FFFL
+#define BIFP6_PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK 0x03FF0000L
+//BIFP6_PCIE_TX_CREDITS_INIT_P
+#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK 0x00FF0000L
+//BIFP6_PCIE_TX_CREDITS_INIT_NP
+#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK 0x00FF0000L
+//BIFP6_PCIE_TX_CREDITS_INIT_CPL
+#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK 0x00000FFFL
+#define BIFP6_PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK 0x00FF0000L
+//BIFP6_PCIE_TX_CREDITS_STATUS
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT 0x1
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT 0x2
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT 0x3
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT 0x4
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT 0x5
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT 0x11
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT 0x12
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT 0x13
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT 0x14
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT 0x15
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK 0x00000001L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK 0x00000002L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK 0x00000004L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK 0x00000008L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK 0x00000010L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK 0x00000020L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK 0x00010000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK 0x00020000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK 0x00040000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK 0x00080000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK 0x00100000L
+#define BIFP6_PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK 0x00200000L
+//BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT 0x0
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT 0x4
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT 0x8
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT 0x10
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT 0x14
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT 0x18
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK 0x00000007L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK 0x00000070L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK 0x00000700L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK 0x00070000L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK 0x00700000L
+#define BIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK 0x07000000L
+//BIFP6_PCIE_TX_CCIX_PORT_CNTL0
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE__SHIFT 0x0
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC__SHIFT 0x3
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC__SHIFT 0x6
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID__SHIFT 0x8
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID__SHIFT 0x10
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN__SHIFT 0x19
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS__SHIFT 0x1c
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_REQATTR_MEMTYPE_MASK 0x00000007L
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_CCIX_TC_MASK 0x00000038L
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_NONSEC_MASK 0x00000040L
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_TGT_ID_MASK 0x00003F00L
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_SRC_ID_MASK 0x003F0000L
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__RXCCIX_RECEIVE_OPT_HDR_EN_MASK 0x02000000L
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL0__TXCCIX_MSG_REQ_QOS_MASK 0xF0000000L
+//BIFP6_PCIE_TX_CCIX_PORT_CNTL1
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID__SHIFT 0x0
+#define BIFP6_PCIE_TX_CCIX_PORT_CNTL1__TXCCIX_PCIE_TGT_ROUTING_ID_MASK 0x0000FFFFL
+//BIFP6_PCIE_CCIX_STACKED_BASE
+#define BIFP6_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE__SHIFT 0x4
+#define BIFP6_PCIE_CCIX_STACKED_BASE__CCIX_STACKED_ADDR_BASE_MASK 0xFFFFFFF0L
+//BIFP6_PCIE_CCIX_STACKED_LIMIT
+#define BIFP6_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT__SHIFT 0x4
+#define BIFP6_PCIE_CCIX_STACKED_LIMIT__CCIX_STACKED_ADDR_LIMIT_MASK 0xFFFFFFF0L
+//BIFP6_PCIE_CCIX_MISC_STATUS
+#define BIFP6_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR__SHIFT 0x0
+#define BIFP6_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR__SHIFT 0x1
+#define BIFP6_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_POSTED_UR_MASK 0x00000001L
+#define BIFP6_PCIE_CCIX_MISC_STATUS__RXCCIX_ERR_NON_POSTED_UR_MASK 0x00000002L
+//BIFP6_PCIE_P_PORT_LANE_STATUS
+#define BIFP6_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT 0x0
+#define BIFP6_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1
+#define BIFP6_PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK 0x00000001L
+#define BIFP6_PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK 0x0000007EL
+//BIFP6_PCIE_FC_P
+#define BIFP6_PCIE_FC_P__PD_CREDITS__SHIFT 0x0
+#define BIFP6_PCIE_FC_P__PH_CREDITS__SHIFT 0x10
+#define BIFP6_PCIE_FC_P__PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP6_PCIE_FC_P__PH_CREDITS_MASK 0x0FFF0000L
+//BIFP6_PCIE_FC_NP
+#define BIFP6_PCIE_FC_NP__NPD_CREDITS__SHIFT 0x0
+#define BIFP6_PCIE_FC_NP__NPH_CREDITS__SHIFT 0x10
+#define BIFP6_PCIE_FC_NP__NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP6_PCIE_FC_NP__NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP6_PCIE_FC_CPL
+#define BIFP6_PCIE_FC_CPL__CPLD_CREDITS__SHIFT 0x0
+#define BIFP6_PCIE_FC_CPL__CPLH_CREDITS__SHIFT 0x10
+#define BIFP6_PCIE_FC_CPL__CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP6_PCIE_FC_CPL__CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP6_PCIE_FC_P_VC1
+#define BIFP6_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS__SHIFT 0x0
+#define BIFP6_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS__SHIFT 0x10
+#define BIFP6_PCIE_FC_P_VC1__ADVT_FC_VC1_PD_CREDITS_MASK 0x0000FFFFL
+#define BIFP6_PCIE_FC_P_VC1__ADVT_FC_VC1_PH_CREDITS_MASK 0x0FFF0000L
+//BIFP6_PCIE_FC_NP_VC1
+#define BIFP6_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS__SHIFT 0x0
+#define BIFP6_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS__SHIFT 0x10
+#define BIFP6_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPD_CREDITS_MASK 0x0000FFFFL
+#define BIFP6_PCIE_FC_NP_VC1__ADVT_FC_VC1_NPH_CREDITS_MASK 0x0FFF0000L
+//BIFP6_PCIE_FC_CPL_VC1
+#define BIFP6_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS__SHIFT 0x0
+#define BIFP6_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS__SHIFT 0x10
+#define BIFP6_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLD_CREDITS_MASK 0x0000FFFFL
+#define BIFP6_PCIE_FC_CPL_VC1__ADVT_FC_VC1_CPLH_CREDITS_MASK 0x0FFF0000L
+//BIFP6_PCIE_ERR_CNTL
+#define BIFP6_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define BIFP6_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT 0x1
+#define BIFP6_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT 0x2
+#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT 0x4
+#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT 0x5
+#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT 0x6
+#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT 0x7
+#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define BIFP6_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT 0xe
+#define BIFP6_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT 0xf
+#define BIFP6_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT 0x10
+#define BIFP6_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define BIFP6_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define BIFP6_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP__SHIFT 0x13
+#define BIFP6_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP__SHIFT 0x14
+#define BIFP6_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define BIFP6_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK 0x00000002L
+#define BIFP6_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK 0x00000004L
+#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK 0x00000010L
+#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK 0x00000020L
+#define BIFP6_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK 0x00000040L
+#define BIFP6_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK 0x00000080L
+#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define BIFP6_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define BIFP6_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK 0x00004000L
+#define BIFP6_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK 0x00008000L
+#define BIFP6_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK 0x00010000L
+#define BIFP6_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define BIFP6_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define BIFP6_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_DLLP_MASK 0x00080000L
+#define BIFP6_PCIE_ERR_CNTL__AER_PRIV_MASK_BAD_TLP_MASK 0x00100000L
+//BIFP6_PCIE_RX_CNTL
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT 0x0
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT 0x1
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT 0x2
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT 0x3
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT 0x4
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT 0x5
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT 0x6
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT 0x7
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT 0xa
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT 0xb
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT 0xc
+#define BIFP6_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT 0xd
+#define BIFP6_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT 0xf
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT 0x10
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT 0x13
+#define BIFP6_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT 0x17
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define BIFP6_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define BIFP6_PCIE_RX_CNTL__CTO_MASK_PRIV__SHIFT 0x1c
+#define BIFP6_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE__SHIFT 0x1d
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK 0x00000001L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK 0x00000002L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK 0x00000004L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK 0x00000008L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK 0x00000010L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK 0x00000020L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK 0x00000040L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK 0x00000080L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK 0x00000400L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK 0x00000800L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK 0x00001000L
+#define BIFP6_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK 0x00002000L
+#define BIFP6_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK 0x00008000L
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK 0x00070000L
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK 0x00080000L
+#define BIFP6_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK 0x00800000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define BIFP6_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define BIFP6_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+#define BIFP6_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+#define BIFP6_PCIE_RX_CNTL__CTO_MASK_PRIV_MASK 0x10000000L
+#define BIFP6_PCIE_RX_CNTL__RX_SWAP_RTRC_TO_BFRC_ENABLE_MASK 0x20000000L
+//BIFP6_PCIE_RX_EXPECTED_SEQNUM
+#define BIFP6_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT 0x0
+#define BIFP6_PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK 0x00000FFFL
+//BIFP6_PCIE_RX_VENDOR_SPECIFIC
+#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT 0x0
+#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT 0x18
+#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK 0x00FFFFFFL
+#define BIFP6_PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK 0x01000000L
+//BIFP6_PCIE_RX_CNTL3
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT 0x0
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT 0x1
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT 0x2
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT 0x3
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT 0x4
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK 0x00000001L
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK 0x00000002L
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK 0x00000004L
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK 0x00000008L
+#define BIFP6_PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK 0x00000010L
+//BIFP6_PCIE_RX_CREDITS_ALLOCATED_P
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT 0x0
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT 0x10
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK 0x00000FFFL
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK 0x00FF0000L
+//BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT 0x0
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT 0x10
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK 0x00000FFFL
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK 0x00FF0000L
+//BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT 0x0
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT 0x10
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK 0x00000FFFL
+#define BIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK 0x00FF0000L
+//BIFP6_PCIEP_ERROR_INJECT_PHYSICAL
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT 0x0
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT 0x2
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT 0x4
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT 0x6
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT 0x8
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT 0xa
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT 0xc
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT 0xe
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT 0x10
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT 0x12
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT 0x14
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT 0x16
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK 0x00000003L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK 0x0000000CL
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK 0x00000030L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK 0x000000C0L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK 0x00000300L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK 0x00000C00L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK 0x00003000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK 0x0000C000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK 0x00030000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK 0x000C0000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK 0x00300000L
+#define BIFP6_PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK 0x00C00000L
+//BIFP6_PCIEP_ERROR_INJECT_TRANSACTION
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT 0x0
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT 0x2
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT 0x4
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT 0x6
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT 0x8
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT 0xa
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT 0xc
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT 0xe
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT 0x10
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT 0x12
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK 0x00000003L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK 0x0000000CL
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK 0x00000030L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK 0x000000C0L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK 0x00000300L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK 0x00000C00L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK 0x00003000L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK 0x0000C000L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK 0x00030000L
+#define BIFP6_PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK 0x000C0000L
+//BIFP6_PCIEP_NAK_COUNTER
+#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT 0x0
+#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT 0x10
+#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK 0x0000FFFFL
+#define BIFP6_PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK 0xFFFF0000L
+//BIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS
+//BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE__SHIFT 0x0
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE__SHIFT 0xa
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR__SHIFT 0xf
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE__SHIFT 0x1a
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR__SHIFT 0x1f
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_VALUE_MASK 0x000003FFL
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_SCALE_MASK 0x00001C00L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_SNOOP_THRESHOLD_REQR_MASK 0x00008000L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_SCALE_MASK 0x1C000000L
+#define BIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES__RX_LTR_NONSNOOP_THRESHOLD_REQR_MASK 0x80000000L
+//BIFP6_PCIE_AER_PRIV_UNCORRECTABLE_MASK
+#define BIFP6_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK__SHIFT 0x5
+#define BIFP6_PCIE_AER_PRIV_UNCORRECTABLE_MASK__PRIV_SURP_DOWN_MASK_MASK 0x00000020L
+//BIFP6_PCIE_AER_PRIV_TRIGGER
+#define BIFP6_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION__SHIFT 0x0
+#define BIFP6_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE__SHIFT 0x1
+#define BIFP6_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES__SHIFT 0x2
+#define BIFP6_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FAKE_DL_ACTIVE_TRANSITION_MASK 0x00000001L
+#define BIFP6_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_DL_INACTIVE_MASK 0x00000002L
+#define BIFP6_PCIE_AER_PRIV_TRIGGER__PRIV_SURP_DOWN_FORCE_AER_IN_ALL_DL_STATES_MASK 0x00000004L
+//BIFP6_PCIE_LC_CNTL
+#define BIFP6_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT 0x1
+#define BIFP6_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL__LC_RESET_LINK__SHIFT 0x3
+#define BIFP6_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT 0x11
+#define BIFP6_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT 0x14
+#define BIFP6_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT 0x19
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT 0x1b
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT 0x1c
+#define BIFP6_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT 0x1d
+#define BIFP6_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT 0x1e
+#define BIFP6_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK 0x00000002L
+#define BIFP6_PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK 0x00000004L
+#define BIFP6_PCIE_LC_CNTL__LC_RESET_LINK_MASK 0x00000008L
+#define BIFP6_PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK 0x000000F0L
+#define BIFP6_PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK 0x00000F00L
+#define BIFP6_PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK 0x0000F000L
+#define BIFP6_PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK 0x00010000L
+#define BIFP6_PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK 0x00020000L
+#define BIFP6_PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK 0x000C0000L
+#define BIFP6_PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK 0x00100000L
+#define BIFP6_PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK 0x00800000L
+#define BIFP6_PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK 0x01000000L
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_COUNT_MASK 0x06000000L
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK 0x08000000L
+#define BIFP6_PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK 0x10000000L
+#define BIFP6_PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK 0x20000000L
+#define BIFP6_PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK 0x40000000L
+#define BIFP6_PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK 0x80000000L
+//BIFP6_PCIE_LC_TRAINING_CNTL
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT 0x0
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT 0x4
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT 0x5
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT 0x6
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT 0x7
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT 0x8
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT 0xb
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT 0xc
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT 0xd
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT 0xe
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT 0xf
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT 0x10
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT 0x11
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT 0x12
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT 0x13
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT 0x14
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT 0x15
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT 0x16
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT 0x18
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT 0x19
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT 0x1a
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT 0x1b
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT 0x1c
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT 0x1d
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT 0x1e
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK 0x0000000FL
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK 0x00000010L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK 0x00000020L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK 0x00000040L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK 0x00000080L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK 0x00000700L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK 0x00000800L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK 0x00001000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK 0x00002000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK 0x00004000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK 0x00008000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK 0x00010000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK 0x00020000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK 0x00040000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK 0x00080000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK 0x00100000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK 0x00200000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK 0x00C00000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK 0x01000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK 0x02000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK 0x04000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK 0x08000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK 0x10000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK 0x20000000L
+#define BIFP6_PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK 0xC0000000L
+//BIFP6_PCIE_LC_LINK_WIDTH_CNTL
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT 0x0
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT 0x7
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT 0x8
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT 0x9
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT 0xa
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT 0xb
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT 0xc
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT 0xd
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT 0xe
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT 0xf
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT 0x12
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT 0x13
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT 0x14
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT 0x17
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT 0x18
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT 0x19
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT 0x1a
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT 0x1b
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT 0x1c
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT 0x1d
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT 0x1e
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT 0x1f
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK 0x00000007L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK 0x00000080L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK 0x00000100L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK 0x00000200L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK 0x00000400L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK 0x00000800L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK 0x00002000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK 0x00004000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK 0x00008000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK 0x00020000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK 0x00040000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK 0x00080000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK 0x00100000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK 0x00600000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK 0x00800000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK 0x01000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK 0x02000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK 0x04000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK 0x08000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK 0x10000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK 0x20000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK 0x40000000L
+#define BIFP6_PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK 0x80000000L
+//BIFP6_PCIE_LC_N_FTS_CNTL
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT 0x0
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT 0x8
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT 0x9
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL__SHIFT 0xa
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT 0xe
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL__SHIFT 0xf
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT 0x10
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT 0x18
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK 0x000000FFL
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK 0x00000100L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK 0x00000200L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_EIE_SEL_MASK 0x00000400L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK 0x00004000L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_16GT_CNTL_MASK 0x00008000L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK 0x00FF0000L
+#define BIFP6_PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK 0xFF000000L
+//BIFP6_PCIE_LC_SPEED_CNTL
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT 0x3
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT 0x4
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT 0x6
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT 0x7
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT 0x8
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT 0x9
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT 0xa
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0xb
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0xd
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xe
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT 0x10
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT 0x11
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT 0x12
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT 0x13
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT 0x14
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT 0x15
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT 0x16
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4__SHIFT 0x17
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4__SHIFT 0x18
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT 0x19
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT 0x1a
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT 0x1c
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT 0x1d
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT 0x1e
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT 0x1f
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK 0x00000008L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK 0x00000030L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK 0x00000040L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK 0x00000080L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK 0x00000100L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK 0x00000200L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK 0x00000400L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x00001800L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00002000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0x0000C000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK 0x00010000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK 0x00020000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK 0x00040000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK 0x00080000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK 0x00100000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK 0x00200000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK 0x00400000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN4_MASK 0x00800000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN4_MASK 0x01000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK 0x02000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK 0x0C000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK 0x10000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK 0x20000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK 0x40000000L
+#define BIFP6_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK 0x80000000L
+//BIFP6_PCIE_LC_STATE0
+#define BIFP6_PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT 0x0
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT 0x8
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT 0x10
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT 0x18
+#define BIFP6_PCIE_LC_STATE0__LC_CURRENT_STATE_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE1_MASK 0x00003F00L
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE2_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_STATE0__LC_PREV_STATE3_MASK 0x3F000000L
+//BIFP6_PCIE_LC_STATE1
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT 0x0
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT 0x8
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT 0x10
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT 0x18
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE4_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE5_MASK 0x00003F00L
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE6_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_STATE1__LC_PREV_STATE7_MASK 0x3F000000L
+//BIFP6_PCIE_LC_STATE2
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT 0x0
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT 0x8
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT 0x10
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT 0x18
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE8_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE9_MASK 0x00003F00L
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE10_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_STATE2__LC_PREV_STATE11_MASK 0x3F000000L
+//BIFP6_PCIE_LC_STATE3
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT 0x0
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT 0x8
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT 0x10
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT 0x18
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE12_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE13_MASK 0x00003F00L
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE14_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_STATE3__LC_PREV_STATE15_MASK 0x3F000000L
+//BIFP6_PCIE_LC_STATE4
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT 0x0
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT 0x8
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT 0x10
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT 0x18
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE16_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE17_MASK 0x00003F00L
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE18_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_STATE4__LC_PREV_STATE19_MASK 0x3F000000L
+//BIFP6_PCIE_LC_STATE5
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT 0x0
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT 0x8
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT 0x10
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT 0x18
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE20_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE21_MASK 0x00003F00L
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE22_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_STATE5__LC_PREV_STATE23_MASK 0x3F000000L
+//BIFP6_PCIE_LINK_MANAGEMENT_CNTL2
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT 0x0
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT 0x1
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT 0x2
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT 0x3
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT 0x4
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN__SHIFT 0x5
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN__SHIFT 0x6
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT 0x7
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT 0xb
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT 0xf
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT 0x13
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4__SHIFT 0x17
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4__SHIFT 0x1b
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK 0x00000001L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK 0x00000002L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK 0x00000004L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK 0x00000008L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK 0x00000010L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_TX_EN_MASK 0x00000020L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_RX_EN_MASK 0x00000040L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK 0x00000780L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK 0x00007800L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK 0x00078000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK 0x00780000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G4_MASK 0x07800000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G4_MASK 0x78000000L
+//BIFP6_PCIE_LC_CNTL2
+#define BIFP6_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT 0x7
+#define BIFP6_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT 0x9
+#define BIFP6_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT 0xa
+#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT 0xb
+#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT 0xe
+#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT 0x11
+#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT 0x13
+#define BIFP6_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT 0x14
+#define BIFP6_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT 0x19
+#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define BIFP6_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT 0x1c
+#define BIFP6_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT 0x1d
+#define BIFP6_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK 0x0000003FL
+#define BIFP6_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK 0x00000040L
+#define BIFP6_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK 0x00000080L
+#define BIFP6_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK 0x00000100L
+#define BIFP6_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK 0x00000200L
+#define BIFP6_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK 0x00000400L
+#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK 0x00000800L
+#define BIFP6_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK 0x00001000L
+#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK 0x00002000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK 0x00010000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK 0x00020000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK 0x00040000L
+#define BIFP6_PCIE_LC_CNTL2__LC_CONSECUTIVE_EIOS_RESET_EN_MASK 0x00080000L
+#define BIFP6_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK 0x00100000L
+#define BIFP6_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK 0x01800000L
+#define BIFP6_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK 0x02000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK 0x04000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK 0x10000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK 0x60000000L
+#define BIFP6_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK 0x80000000L
+//BIFP6_PCIE_LC_BW_CHANGE_CNTL
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT 0x0
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT 0x1
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT 0x2
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT 0x3
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT 0x4
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT 0x5
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT 0x6
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT 0x7
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT 0x8
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT 0x9
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT 0xa
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT 0xb
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK 0x00000001L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK 0x00000002L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK 0x00000004L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK 0x00000010L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK 0x00000020L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK 0x00000040L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK 0x00000080L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK 0x00000100L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK 0x00000200L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK 0x00000400L
+#define BIFP6_PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK 0x00000800L
+//BIFP6_PCIE_LC_CDR_CNTL
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT 0x0
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT 0xc
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT 0x18
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK 0x00000FFFL
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK 0x00FFF000L
+#define BIFP6_PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK 0x03000000L
+//BIFP6_PCIE_LC_LANE_CNTL
+#define BIFP6_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT 0x0
+#define BIFP6_PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK 0x0000FFFFL
+//BIFP6_PCIE_LC_CNTL3
+#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT 0x1
+#define BIFP6_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT 0x3
+#define BIFP6_PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT 0x5
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT 0x9
+#define BIFP6_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT 0xa
+#define BIFP6_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT 0xb
+#define BIFP6_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE__SHIFT 0xe
+#define BIFP6_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY__SHIFT 0xf
+#define BIFP6_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT 0x11
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT 0x13
+#define BIFP6_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT 0x1e
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK 0x00000001L
+#define BIFP6_PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK 0x00000006L
+#define BIFP6_PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK 0x00000008L
+#define BIFP6_PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK 0x00000010L
+#define BIFP6_PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK 0x00000020L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK 0x000000C0L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000100L
+#define BIFP6_PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK 0x00000200L
+#define BIFP6_PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK 0x00000400L
+#define BIFP6_PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK 0x00000800L
+#define BIFP6_PCIE_LC_CNTL3__LC_LINK_DOWN_SPD_CHG_EN_MASK 0x00001000L
+#define BIFP6_PCIE_LC_CNTL3__LC_CLR_DELAY_DLLP_WHEN_NO_AUTO_EQ_MASK 0x00002000L
+#define BIFP6_PCIE_LC_CNTL3__LC_MULT_AUTO_SPD_CHG_ON_LAST_RATE_MASK 0x00004000L
+#define BIFP6_PCIE_LC_CNTL3__LC_CLEAR_RXSTANDBY_ON_RATE_UPDATE_ONLY_MASK 0x00008000L
+#define BIFP6_PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK 0x00020000L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK 0x00040000L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK 0x00180000L
+#define BIFP6_PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL3__LC_POWERDOWN_P0_WAIT_FOR_REFCLKACK_ON_L1_EXIT_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK 0x00800000L
+#define BIFP6_PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK 0x03000000L
+#define BIFP6_PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK 0x3C000000L
+#define BIFP6_PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK 0x40000000L
+#define BIFP6_PCIE_LC_CNTL3__LC_AUTO_RECOVERY_DIS_MASK 0x80000000L
+//BIFP6_PCIE_LC_CNTL4
+#define BIFP6_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT 0x3
+#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL4__LC_REDO_EQ_8GT__SHIFT 0x5
+#define BIFP6_PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT 0x7
+#define BIFP6_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT 0xa
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT__SHIFT 0xb
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT 0xe
+#define BIFP6_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT__SHIFT 0xf
+#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT__SHIFT 0x11
+#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL4__LC_TX_SWING__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT 0x19
+#define BIFP6_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK 0x00000003L
+#define BIFP6_PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK 0x00000004L
+#define BIFP6_PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK 0x00000008L
+#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_8GT_MASK 0x00000010L
+#define BIFP6_PCIE_LC_CNTL4__LC_REDO_EQ_8GT_MASK 0x00000020L
+#define BIFP6_PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK 0x00000040L
+#define BIFP6_PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK 0x00000080L
+#define BIFP6_PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_8GT_MASK 0x00000300L
+#define BIFP6_PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK 0x00000400L
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_8GT_MASK 0x00000800L
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_8GT_MASK 0x00001000L
+#define BIFP6_PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK 0x00002000L
+#define BIFP6_PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK 0x00004000L
+#define BIFP6_PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_8GT_MASK 0x00008000L
+#define BIFP6_PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_8GT_MASK 0x00010000L
+#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_8GT_MASK 0x00020000L
+#define BIFP6_PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_8GT_MASK 0x003C0000L
+#define BIFP6_PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL4__LC_TX_SWING_MASK 0x00800000L
+#define BIFP6_PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK 0x01000000L
+#define BIFP6_PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK 0x02000000L
+#define BIFP6_PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK 0xFC000000L
+//BIFP6_PCIE_LC_CNTL5
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_PRESET__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_CURSOR__SHIFT 0xa
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT 0x19
+#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT 0x1b
+#define BIFP6_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT 0x1c
+#define BIFP6_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT 0x1d
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_EQ_SETTINGS_RATE_MASK 0x00000003L
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_PRESET_MASK 0x0000003CL
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_PRE_CURSOR_MASK 0x000003C0L
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_CURSOR_MASK 0x0000FC00L
+#define BIFP6_PCIE_LC_CNTL5__LC_LOCAL_POST_CURSOR_MASK 0x001F0000L
+#define BIFP6_PCIE_LC_CNTL5__LC_RXSTANDBY_ON_SPEED_CHANGE_ONLY_EN_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL5__LC_SAFE_RECOVER_CNTL_MASK 0x00C00000L
+#define BIFP6_PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK 0x01000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK 0x02000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK 0x04000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK 0x08000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK 0x10000000L
+#define BIFP6_PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK 0xE0000000L
+//BIFP6_PCIE_LC_FORCE_COEFF
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT__SHIFT 0x0
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT__SHIFT 0x1
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT__SHIFT 0x7
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT__SHIFT 0xd
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT__SHIFT 0x13
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT 0x14
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_8GT_MASK 0x00000001L
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_8GT_MASK 0x0000007EL
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_8GT_MASK 0x00001F80L
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_8GT_MASK 0x0007E000L
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_8GT_MASK 0x00080000L
+#define BIFP6_PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK 0x00100000L
+//BIFP6_PCIE_LC_BEST_EQ_SETTINGS
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT 0x0
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT 0x4
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT 0xa
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT 0x10
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT 0x16
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE__SHIFT 0x1e
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK 0x0000000FL
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK 0x000003F0L
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK 0x0000FC00L
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK 0x003F0000L
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK 0x3FC00000L
+#define BIFP6_PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_SETTINGS_RATE_MASK 0x40000000L
+//BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT__SHIFT 0x0
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT__SHIFT 0x1
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT__SHIFT 0x7
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT__SHIFT 0xd
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT__SHIFT 0x13
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT__SHIFT 0x19
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_8GT_MASK 0x00000001L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_8GT_MASK 0x0000007EL
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_8GT_MASK 0x00001F80L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_8GT_MASK 0x0007E000L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_8GT_MASK 0x01F80000L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_8GT_MASK 0x7E000000L
+//BIFP6_PCIE_LC_CNTL6
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_16GT__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT 0x9
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT 0xe
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT 0x13
+#define BIFP6_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT 0x14
+#define BIFP6_PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK 0x00000003L
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK 0x0000000CL
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK 0x00000030L
+#define BIFP6_PCIE_LC_CNTL6__LC_SPC_MODE_16GT_MASK 0x000000C0L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_EN_MASK 0x00000100L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK 0x00001E00L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK 0x00002000L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK 0x0000C000L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK 0x00030000L
+#define BIFP6_PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK 0x00040000L
+#define BIFP6_PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK 0x00080000L
+#define BIFP6_PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK 0x00100000L
+#define BIFP6_PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL6__LC_P2_ENTRY_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK 0x00800000L
+#define BIFP6_PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK 0x7F000000L
+#define BIFP6_PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK 0x80000000L
+//BIFP6_PCIE_LC_CNTL7
+#define BIFP6_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT 0x1
+#define BIFP6_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT 0x3
+#define BIFP6_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0__SHIFT 0x5
+#define BIFP6_PCIE_LC_CNTL7__LC_LOCK_REVERSAL__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS__SHIFT 0x7
+#define BIFP6_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT 0x9
+#define BIFP6_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG__SHIFT 0xa
+#define BIFP6_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN__SHIFT 0xb
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_RATES__SHIFT 0x19
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT 0x1b
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT 0x1c
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT 0x1d
+#define BIFP6_PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT 0x1e
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK 0x00000001L
+#define BIFP6_PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK 0x00000002L
+#define BIFP6_PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK 0x00000004L
+#define BIFP6_PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK 0x00000008L
+#define BIFP6_PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK 0x00000010L
+#define BIFP6_PCIE_LC_CNTL7__LC_CLEAR_REVERSE_ATTEMPT_IN_L0_MASK 0x00000020L
+#define BIFP6_PCIE_LC_CNTL7__LC_LOCK_REVERSAL_MASK 0x00000040L
+#define BIFP6_PCIE_LC_CNTL7__LC_FORCE_RX_EQ_IN_PROGRESS_MASK 0x00000080L
+#define BIFP6_PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK 0x00000100L
+#define BIFP6_PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK 0x00000200L
+#define BIFP6_PCIE_LC_CNTL7__LC_WAIT_FOR_LANES_IN_CONFIG_MASK 0x00000400L
+#define BIFP6_PCIE_LC_CNTL7__LC_REQ_COEFFS_FOR_TXMARGIN_EN_MASK 0x00000800L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK 0x00001000L
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK 0x001FE000L
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK 0x00800000L
+#define BIFP6_PCIE_LC_CNTL7__LC_AUTO_REJECT_AFTER_TIMEOUT_MASK 0x01000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_RATES_MASK 0x06000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK 0x08000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK 0x10000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK 0x20000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK 0x40000000L
+#define BIFP6_PCIE_LC_CNTL7__LC_ESM_ENTRY_MODE_MASK 0x80000000L
+//BIFP6_PCIE_LINK_MANAGEMENT_STATUS
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT 0x0
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT 0x1
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT 0x2
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT 0x3
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT 0x4
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT 0x5
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT 0x6
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT 0x7
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT 0x8
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT 0x9
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT 0xa
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT 0xb
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT 0xc
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT 0xd
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK 0x00000001L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK 0x00000002L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK 0x00000004L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK 0x00000008L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK 0x00000010L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK 0x00000020L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK 0x00000040L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK 0x00000080L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK 0x00000100L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK 0x00000200L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK 0x00000400L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK 0x00000800L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK 0x00001000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK 0x00002000L
+//BIFP6_PCIE_LINK_MANAGEMENT_MASK
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT 0x0
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x1
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT 0x2
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT 0x3
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT 0x4
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT 0x5
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT 0x6
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT 0x7
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT 0x8
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT 0x9
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT 0xa
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT 0xb
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT 0xc
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT 0xd
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK 0x00000001L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000002L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK 0x00000004L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK 0x00000008L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK 0x00000010L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK 0x00000020L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK 0x00000040L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK 0x00000080L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK 0x00000100L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK 0x00000200L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK 0x00000400L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK 0x00000800L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK 0x00001000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK 0x00002000L
+//BIFP6_PCIE_LINK_MANAGEMENT_CNTL
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT 0x0
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT 0x3
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT 0x7
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT 0xb
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT 0xc
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT 0xd
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT 0xf
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT 0x11
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT 0x12
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT 0x13
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT 0x17
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT 0x1b
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT__SHIFT 0x1e
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT__SHIFT 0x1f
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK 0x00000007L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK 0x00000078L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK 0x00000780L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK 0x00000800L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK 0x00001000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK 0x00006000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK 0x00018000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK 0x00020000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK 0x00040000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK 0x00780000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK 0x07800000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK 0x38000000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_8GT_MASK 0x40000000L
+#define BIFP6_PCIE_LINK_MANAGEMENT_CNTL__EQ_REQ_RCVD_16GT_MASK 0x80000000L
+//BIFP6_PCIEP_STRAP_LC
+#define BIFP6_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT 0x0
+#define BIFP6_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT 0x2
+#define BIFP6_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT 0x4
+#define BIFP6_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT 0x6
+#define BIFP6_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT 0x8
+#define BIFP6_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT 0xb
+#define BIFP6_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT 0xc
+#define BIFP6_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT 0xd
+#define BIFP6_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT 0xe
+#define BIFP6_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT 0xf
+#define BIFP6_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT 0x10
+#define BIFP6_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x13
+#define BIFP6_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP__SHIFT 0x14
+#define BIFP6_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP__SHIFT 0x15
+#define BIFP6_PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK 0x00000003L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK 0x0000000CL
+#define BIFP6_PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK 0x00000030L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK 0x000000C0L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK 0x00000700L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK 0x00000800L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK 0x00001000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK 0x00002000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK 0x00004000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK 0x00008000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK 0x00070000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00080000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_RTM1_PRESENCE_DET_SUPP_MASK 0x00100000L
+#define BIFP6_PCIEP_STRAP_LC__STRAP_RTM2_PRESENCE_DET_SUPP_MASK 0x00200000L
+//BIFP6_PCIEP_STRAP_MISC
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT 0x0
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT 0x1
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT 0x2
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT 0x3
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT 0x5
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_CCIX_EN__SHIFT 0x6
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT__SHIFT 0x7
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK 0x00000001L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK 0x00000002L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK 0x00000004L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK 0x00000018L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK 0x00000020L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_CCIX_EN_MASK 0x00000040L
+#define BIFP6_PCIEP_STRAP_MISC__STRAP_CCIX_OPT_TLP_FMT_SUPPORT_MASK 0x00000080L
+//BIFP6_PCIEP_STRAP_LC2
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP__SHIFT 0x1
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED__SHIFT 0x3
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME__SHIFT 0x4
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT__SHIFT 0x7
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_MODE_SUPPORTED_MASK 0x00000001L
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_PHY_REACH_LEN_CAP_MASK 0x00000006L
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_RECAL_NEEDED_MASK 0x00000008L
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_CALIB_TIME_MASK 0x00000070L
+#define BIFP6_PCIEP_STRAP_LC2__STRAP_ESM_QUICK_EQ_TIMEOUT_MASK 0x00000380L
+//BIFP6_PCIE_LC_L1_PM_SUBSTATE
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT 0x0
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT 0x1
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT 0x2
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT 0x3
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT 0x4
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN__SHIFT 0x5
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT 0x6
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT 0x8
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT 0x10
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT 0x14
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT__SHIFT 0x17
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN__SHIFT 0x1a
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2__SHIFT 0x1b
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY__SHIFT 0x1c
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK 0x00000004L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK 0x00000008L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK 0x00000010L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_CLKREQ_FILTER_EN_MASK 0x00000020L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK 0x000000C0L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK 0x00001F00L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK 0x00070000L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK 0x00700000L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_DEFER_L1_2_EXIT_MASK 0x03800000L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_AUX_COUNT_REFCLK_INCREMENT_EN_MASK 0x04000000L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_IGNORE_RX_ELEC_IDLE_IN_L1_2_MASK 0x08000000L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE__LC_SKIP_L1_2_POWERDOWN_IN_ABORTED_ENTRY_MASK 0x10000000L
+//BIFP6_PCIE_LC_L1_PM_SUBSTATE2
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT 0x0
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT 0x8
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK 0x000000FFL
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK 0x00000700L
+#define BIFP6_PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK 0x03FF0000L
+//BIFP6_PCIE_LC_PORT_ORDER
+#define BIFP6_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT 0x0
+#define BIFP6_PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK 0x0000000FL
+//BIFP6_PCIEP_BCH_ECC_CNTL
+#define BIFP6_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT 0x0
+#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT 0x8
+#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT 0x10
+#define BIFP6_PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK 0x00000001L
+#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK 0x0000FF00L
+#define BIFP6_PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK 0xFFFF0000L
+//BIFP6_PCIEP_HPGI_PRIVATE
+#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE__SHIFT 0x3
+#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE__SHIFT 0x6
+#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_CHANGED_PRIVATE_MASK 0x00000008L
+#define BIFP6_PCIEP_HPGI_PRIVATE__PRESENCE_DETECT_STATE_PRIVATE_MASK 0x00000040L
+//BIFP6_PCIEP_HPGI
+#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN__SHIFT 0x0
+#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN__SHIFT 0x1
+#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN__SHIFT 0x2
+#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN__SHIFT 0x3
+#define BIFP6_PCIEP_HPGI__REG_HPGI_HOOK__SHIFT 0x7
+#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS__SHIFT 0x8
+#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS__SHIFT 0x9
+#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS__SHIFT 0xa
+#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS__SHIFT 0xb
+#define BIFP6_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS__SHIFT 0xf
+#define BIFP6_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN__SHIFT 0x10
+#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SMI_EN_MASK 0x00000001L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_ASSERT_TO_SCI_EN_MASK 0x00000002L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SMI_EN_MASK 0x00000004L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_DEASSERT_TO_SCI_EN_MASK 0x00000008L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_HOOK_MASK 0x00000080L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SMI_STATUS_MASK 0x00000100L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_ASSERT_TO_SCI_STATUS_MASK 0x00000200L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SMI_STATUS_MASK 0x00000400L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_DEASSERT_TO_SCI_STATUS_MASK 0x00000800L
+#define BIFP6_PCIEP_HPGI__HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS_MASK 0x00008000L
+#define BIFP6_PCIEP_HPGI__REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN_MASK 0x00010000L
+//BIFP6_PCIEP_HCNT_DESCRIPTOR
+#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM__SHIFT 0x0
+#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE__SHIFT 0x1f
+#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_SLOT_NUM_MASK 0x00001FFFL
+#define BIFP6_PCIEP_HCNT_DESCRIPTOR__HTPLG_CNTL_DESCRIPTOR_PORT_ACTIVE_MASK 0x80000000L
+//BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP6_PCIE_LC_CNTL8
+#define BIFP6_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT__SHIFT 0x3
+#define BIFP6_PCIE_LC_CNTL8__LC_REDO_EQ_16GT__SHIFT 0x7
+#define BIFP6_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT__SHIFT 0x9
+#define BIFP6_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT__SHIFT 0xa
+#define BIFP6_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT__SHIFT 0xb
+#define BIFP6_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN__SHIFT 0x11
+#define BIFP6_PCIE_LC_CNTL8__LC_EQTS2_PRESET__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL8__LC_FOM_TIME__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH__SHIFT 0x19
+#define BIFP6_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS__SHIFT 0x1b
+#define BIFP6_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN__SHIFT 0x1c
+#define BIFP6_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT 0x1d
+#define BIFP6_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT 0x1e
+#define BIFP6_PCIE_LC_CNTL8__LC_EQ_SEARCH_MODE_16GT_MASK 0x00000003L
+#define BIFP6_PCIE_LC_CNTL8__LC_BYPASS_EQ_16GT_MASK 0x00000004L
+#define BIFP6_PCIE_LC_CNTL8__LC_BYPASS_EQ_PRESET_16GT_MASK 0x00000078L
+#define BIFP6_PCIE_LC_CNTL8__LC_REDO_EQ_16GT_MASK 0x00000080L
+#define BIFP6_PCIE_LC_CNTL8__LC_USC_EQ_NOT_REQD_16GT_MASK 0x00000100L
+#define BIFP6_PCIE_LC_CNTL8__LC_USC_GO_TO_EQ_16GT_MASK 0x00000200L
+#define BIFP6_PCIE_LC_CNTL8__LC_UNEXPECTED_COEFFS_RCVD_16GT_MASK 0x00000400L
+#define BIFP6_PCIE_LC_CNTL8__LC_BYPASS_EQ_REQ_PHASE_16GT_MASK 0x00000800L
+#define BIFP6_PCIE_LC_CNTL8__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_16GT_MASK 0x00001000L
+#define BIFP6_PCIE_LC_CNTL8__LC_FORCE_PRESET_VALUE_16GT_MASK 0x0001E000L
+#define BIFP6_PCIE_LC_CNTL8__LC_EQTS2_PRESET_EN_MASK 0x00020000L
+#define BIFP6_PCIE_LC_CNTL8__LC_EQTS2_PRESET_MASK 0x003C0000L
+#define BIFP6_PCIE_LC_CNTL8__LC_USE_EQTS2_PRESET_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL8__LC_FOM_TIME_MASK 0x01800000L
+#define BIFP6_PCIE_LC_CNTL8__LC_SAFE_EQ_SEARCH_MASK 0x02000000L
+#define BIFP6_PCIE_LC_CNTL8__LC_DONT_CHECK_EQTS_IN_RCFG_MASK 0x04000000L
+#define BIFP6_PCIE_LC_CNTL8__LC_DELAY_COEFF_UPDATE_DIS_MASK 0x08000000L
+#define BIFP6_PCIE_LC_CNTL8__LC_8GT_EQ_REDO_EN_MASK 0x10000000L
+#define BIFP6_PCIE_LC_CNTL8__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK 0x20000000L
+#define BIFP6_PCIE_LC_CNTL8__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK 0xC0000000L
+//BIFP6_PCIE_LC_CNTL9
+#define BIFP6_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE__SHIFT 0x1
+#define BIFP6_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE__SHIFT 0x3
+#define BIFP6_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG__SHIFT 0xa
+#define BIFP6_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN__SHIFT 0xb
+#define BIFP6_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS__SHIFT 0xe
+#define BIFP6_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO__SHIFT 0x19
+#define BIFP6_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN__SHIFT 0x1b
+#define BIFP6_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN__SHIFT 0x1c
+#define BIFP6_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN__SHIFT 0x1d
+#define BIFP6_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN__SHIFT 0x1e
+#define BIFP6_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_EN_MASK 0x00000001L
+#define BIFP6_PCIE_LC_CNTL9__LC_OVERRIDE_RETIMER_PRESENCE_MASK 0x00000006L
+#define BIFP6_PCIE_LC_CNTL9__LC_IGNORE_RETIMER_PRESENCE_MASK 0x00000008L
+#define BIFP6_PCIE_LC_CNTL9__LC_RETIMER_PRESENCE_MASK 0x00000030L
+#define BIFP6_PCIE_LC_CNTL9__LC_ESM_RATE0_TIMER_FACTOR_MASK 0x000000C0L
+#define BIFP6_PCIE_LC_CNTL9__LC_ESM_RATE1_TIMER_FACTOR_MASK 0x00000300L
+#define BIFP6_PCIE_LC_CNTL9__LC_DELAY_CLEAR_LANE_OFF_AFTER_LOOPBACK_SPD_CHG_MASK 0x00000400L
+#define BIFP6_PCIE_LC_CNTL9__LC_LOOPBACK_RXEQEVAL_EN_MASK 0x00000800L
+#define BIFP6_PCIE_LC_CNTL9__LC_EX_SEARCH_TRAVERSAL_MODE_MASK 0x00001000L
+#define BIFP6_PCIE_LC_CNTL9__LC_LOCK_IN_EQ_RESPONSE_MASK 0x00002000L
+#define BIFP6_PCIE_LC_CNTL9__LC_USC_ACCEPTABLE_PRESETS_MASK 0x00FFC000L
+#define BIFP6_PCIE_LC_CNTL9__LC_DSC_ACCEPT_8GT_EQ_REDO_MASK 0x01000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_DSC_ACCEPT_16GT_EQ_REDO_MASK 0x02000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_USC_HW_8GT_EQ_REDO_EN_MASK 0x04000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_USC_HW_16GT_EQ_REDO_EN_MASK 0x08000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_DELAY_DETECTED_TSX_RCV_EN_MASK 0x10000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_RST_FAILING_SPD_CHANGE_CNT_ON_SUCCESS_EN_MASK 0x20000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_INDEPENDENT_CHIP_PCS_REFCLKREQ_EN_MASK 0x40000000L
+#define BIFP6_PCIE_LC_CNTL9__LC_DETECT_4SPC_EIEOS_AS_VALID_TSX_EN_MASK 0x80000000L
+//BIFP6_PCIE_LC_FORCE_COEFF2
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT__SHIFT 0x0
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT__SHIFT 0x1
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT__SHIFT 0x7
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT__SHIFT 0xd
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT__SHIFT 0x13
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_COEFF_16GT_MASK 0x00000001L
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_PRE_CURSOR_16GT_MASK 0x0000007EL
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_CURSOR_16GT_MASK 0x00001F80L
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_FORCE_POST_CURSOR_16GT_MASK 0x0007E000L
+#define BIFP6_PCIE_LC_FORCE_COEFF2__LC_3X3_COEFF_SEARCH_EN_16GT_MASK 0x00080000L
+//BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT__SHIFT 0x0
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT__SHIFT 0x1
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT__SHIFT 0x7
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT__SHIFT 0xd
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT__SHIFT 0x13
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT__SHIFT 0x19
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_16GT_MASK 0x00000001L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_PRE_CURSOR_REQ_16GT_MASK 0x0000007EL
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_CURSOR_REQ_16GT_MASK 0x00001F80L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FORCE_POST_CURSOR_REQ_16GT_MASK 0x0007E000L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_FS_OTHER_END_16GT_MASK 0x01F80000L
+#define BIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF2__LC_LF_OTHER_END_16GT_MASK 0x7E000000L
+//BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER__SHIFT 0x0
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL__SHIFT 0x10
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_COUNTER_MASK 0x0000FFFFL
+#define BIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_LC__PERF_TXCLK_EVENT_SEL_MASK 0x00FF0000L
+//BIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES
+#define BIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING__SHIFT 0x0
+#define BIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING__SHIFT 0x1
+#define BIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_TRANSMIT_MUX_OUTPUT_GATING_MASK 0x00000001L
+#define BIFP6_PCIE_LC_FINE_GRAIN_CLK_GATE_OVERRIDES__LC_DISABLE_SYMBOL_MUX_OUTPUT_GATING_MASK 0x00000002L
+//BIFP6_PCIE_LC_CNTL10
+#define BIFP6_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN__SHIFT 0x1
+#define BIFP6_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED__SHIFT 0x1b
+#define BIFP6_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES__SHIFT 0x1d
+#define BIFP6_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION__SHIFT 0x1e
+#define BIFP6_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL10__LC_ENFORCE_SINGLE_L1_SUBSTATE_CLK_PDWN_ASSERTION_EN_MASK 0x00000001L
+#define BIFP6_PCIE_LC_CNTL10__LC_RXEQEVAL_AFTER_BYPASSED_EQ_EN_MASK 0x00000002L
+#define BIFP6_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_8GT_MASK 0x0000000CL
+#define BIFP6_PCIE_LC_CNTL10__LC_ENH_PRESET_SEARCH_SEL_16GT_MASK 0x00000030L
+#define BIFP6_PCIE_LC_CNTL10__LC_PRESET_MASK_8GT_MASK 0x0000FFC0L
+#define BIFP6_PCIE_LC_CNTL10__LC_PRESET_MASK_16GT_MASK 0x03FF0000L
+#define BIFP6_PCIE_LC_CNTL10__LC_USE_LONG_SERIAL_QUICKSIM_TIMEOUTS_MASK 0x04000000L
+#define BIFP6_PCIE_LC_CNTL10__LC_TRAINING_BITS_REQUIRED_MASK 0x18000000L
+#define BIFP6_PCIE_LC_CNTL10__LC_REFCLK_OFF_NO_RCVR_LANES_MASK 0x20000000L
+#define BIFP6_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN3_PRESET_CONVERSION_MASK 0x40000000L
+#define BIFP6_PCIE_LC_CNTL10__LC_ALWAYS_PERFORM_GEN4_PRESET_CONVERSION_MASK 0x80000000L
+//BIFP6_PCIE_LC_CNTL11
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE__SHIFT 0x1
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE__SHIFT 0x3
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE__SHIFT 0x5
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE__SHIFT 0x9
+#define BIFP6_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER__SHIFT 0xe
+#define BIFP6_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN__SHIFT 0xf
+#define BIFP6_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK__SHIFT 0x11
+#define BIFP6_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG__SHIFT 0x13
+#define BIFP6_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN__SHIFT 0x14
+#define BIFP6_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_EN__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD__SHIFT 0x18
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_MODE__SHIFT 0x1a
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_DONE__SHIFT 0x1b
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED__SHIFT 0x1c
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE__SHIFT 0x1e
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_EN_MASK 0x00000001L
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_MODE_MASK 0x00000002L
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_PORT_MASK 0x00000004L
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_RATE_MASK 0x00000018L
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_VALUE_MASK 0x000001E0L
+#define BIFP6_PCIE_LC_CNTL11__LC_DEFAULT_PRESET_OVERRIDE_LANE_MASK 0x00001E00L
+#define BIFP6_PCIE_LC_CNTL11__LC_LOOPBACK_WAIT_FOR_ALL_ACTIVE_LANES_MASK 0x00002000L
+#define BIFP6_PCIE_LC_CNTL11__LC_USE_SEPARATE_RXRECOVER_TIMER_MASK 0x00004000L
+#define BIFP6_PCIE_LC_CNTL11__LC_RXRECOVER_IN_POLL_ACTIVE_EN_MASK 0x00008000L
+#define BIFP6_PCIE_LC_CNTL11__LC_RXRECOVER_IN_CONFIG_EN_MASK 0x00010000L
+#define BIFP6_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_RECOVERY_LOCK_MASK 0x00020000L
+#define BIFP6_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_POLL_ACTIVE_MASK 0x00040000L
+#define BIFP6_PCIE_LC_CNTL11__LC_ASSERT_RXSTANDBY_FOR_RXRECOVER_IN_CONFIG_MASK 0x00080000L
+#define BIFP6_PCIE_LC_CNTL11__LC_HOLD_RXSTANDBY_UNTIL_EI_EXIT_IN_POLL_ACTIVE_EN_MASK 0x00100000L
+#define BIFP6_PCIE_LC_CNTL11__LC_HOLD_REFCLKREQ_UNTIL_L1SS_POWERDOWN_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL11__LC_BLOCK_L0s_FOR_POWERDOWN_CHANGE_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_EN_MASK 0x00800000L
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_RATE_REQD_MASK 0x03000000L
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_MODE_MASK 0x04000000L
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_DONE_MASK 0x08000000L
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_TLS_ADVERTISED_MASK 0x30000000L
+#define BIFP6_PCIE_LC_CNTL11__LC_LSLD_CURRENT_RATE_MASK 0xC0000000L
+//BIFP6_PCIE_LC_CNTL12
+#define BIFP6_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE__SHIFT 0x0
+#define BIFP6_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN__SHIFT 0x1
+#define BIFP6_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0__SHIFT 0x2
+#define BIFP6_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES__SHIFT 0x3
+#define BIFP6_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT__SHIFT 0x4
+#define BIFP6_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE__SHIFT 0x5
+#define BIFP6_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE__SHIFT 0x6
+#define BIFP6_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE__SHIFT 0x7
+#define BIFP6_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY__SHIFT 0x8
+#define BIFP6_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1__SHIFT 0x9
+#define BIFP6_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN__SHIFT 0xa
+#define BIFP6_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED__SHIFT 0xb
+#define BIFP6_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1__SHIFT 0xc
+#define BIFP6_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN__SHIFT 0xd
+#define BIFP6_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK__SHIFT 0xe
+#define BIFP6_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1__SHIFT 0xf
+#define BIFP6_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES__SHIFT 0x10
+#define BIFP6_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON__SHIFT 0x11
+#define BIFP6_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG__SHIFT 0x12
+#define BIFP6_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS__SHIFT 0x13
+#define BIFP6_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS__SHIFT 0x14
+#define BIFP6_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1__SHIFT 0x15
+#define BIFP6_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP__SHIFT 0x16
+#define BIFP6_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK__SHIFT 0x17
+#define BIFP6_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING__SHIFT 0x1f
+#define BIFP6_PCIE_LC_CNTL12__LC_CHECK_EC_GEN3_LOOPBACK_ACTIVE_MASK 0x00000001L
+#define BIFP6_PCIE_LC_CNTL12__LC_DELAY_POLL_COMP_SPD_CHG_AFTER_TXMARGIN_MASK 0x00000002L
+#define BIFP6_PCIE_LC_CNTL12__LC_WAIT_FOR_NONPAD_LINK_NUM_LANE0_MASK 0x00000004L
+#define BIFP6_PCIE_LC_CNTL12__LC_SKIP_LOCALPRESET_OFF_LANES_MASK 0x00000008L
+#define BIFP6_PCIE_LC_CNTL12__LC_RESET_SKP_SELECT_16GT_ON_TRAINING_BIT_MASK 0x00000010L
+#define BIFP6_PCIE_LC_CNTL12__LC_CLR_LINK_LANE_NUM_ON_NO_TSX_LANE_MASK 0x00000020L
+#define BIFP6_PCIE_LC_CNTL12__LC_FORCE_L1_PG_EXIT_ON_REG_WRITE_MASK 0x00000040L
+#define BIFP6_PCIE_LC_CNTL12__LC_EXTEND_EIEOS_MODE_MASK 0x00000080L
+#define BIFP6_PCIE_LC_CNTL12__LC_RXEQEVAL_WAIT_FOR_RXSTANDBY_MASK 0x00000100L
+#define BIFP6_PCIE_LC_CNTL12__LC_DEASSERT_REFCLKREQ_IN_NON_SS_L1_MASK 0x00000200L
+#define BIFP6_PCIE_LC_CNTL12__LC_ALT_RX_EQ_IN_PROGRESS_EN_MASK 0x00000400L
+#define BIFP6_PCIE_LC_CNTL12__LC_ALLOW_DLLPS_OTHER_SIDE_REMOVE_SPEED_MASK 0x00000800L
+#define BIFP6_PCIE_LC_CNTL12__LC_QUICK_L1_1_ABORT_IN_L1_MASK 0x00001000L
+#define BIFP6_PCIE_LC_CNTL12__LC_DYN_LANES_L1_SS_POWERDOWN_MASK 0x00002000L
+#define BIFP6_PCIE_LC_CNTL12__LC_CLKGATE_WAIT_FOR_REFCLKACK_MASK 0x00004000L
+#define BIFP6_PCIE_LC_CNTL12__LC_QUICK_L1_2_ABORT_IN_L1_MASK 0x00008000L
+#define BIFP6_PCIE_LC_CNTL12__LC_DETECT_PD_WAIT_FOR_REFCLKACK_OFF_LANES_MASK 0x00010000L
+#define BIFP6_PCIE_LC_CNTL12__LC_DETECT_PD_HOLDTRAINING_WAIT_FOR_LANES_ON_MASK 0x00020000L
+#define BIFP6_PCIE_LC_CNTL12__LC_DELAY_CLEAR_LANE_OFF_AFTER_LINKDIS_SPD_CHG_MASK 0x00040000L
+#define BIFP6_PCIE_LC_CNTL12__LC_ENSURE_TURN_OFF_DONE_LINKDIS_MASK 0x00080000L
+#define BIFP6_PCIE_LC_CNTL12__LC_CONFIG_WAIT_FOR_EIEOS_MASK 0x00100000L
+#define BIFP6_PCIE_LC_CNTL12__LC_HOLD_TLP_TO_XMIT_PULSE_IN_L1_MASK 0x00200000L
+#define BIFP6_PCIE_LC_CNTL12__LC_BLOCK_NEAREND_L1_2_WAKEUP_MASK 0x00400000L
+#define BIFP6_PCIE_LC_CNTL12__LC_RECOVERY_WAIT_FOR_ASPM_NAK_MASK 0x00800000L
+#define BIFP6_PCIE_LC_CNTL12__LC_REFCLKREQ_IN_HOLD_TRAINING_MASK 0x80000000L
+//BIFP6_PCIE_LC_SAVE_RESTORE_1
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN__SHIFT 0x0
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION__SHIFT 0x1
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX__SHIFT 0x2
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE__SHIFT 0xa
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE__SHIFT 0xb
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN__SHIFT 0xc
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN__SHIFT 0xd
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS__SHIFT 0xe
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO__SHIFT 0x10
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_EN_MASK 0x00000001L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DIRECTION_MASK 0x00000002L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_INDEX_MASK 0x000003FCL
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_ACKNOWLEDGE_MASK 0x00000400L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DONE_MASK 0x00000800L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_FAST_RESTORE_EN_MASK 0x00001000L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_BYPASS_P2C_EN_MASK 0x00002000L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_SPEEDS_MASK 0x0000C000L
+#define BIFP6_PCIE_LC_SAVE_RESTORE_1__LC_SAVE_RESTORE_DATA_LO_MASK 0xFFFF0000L
+//BIFP6_PCIE_LC_SAVE_RESTORE_2
+#define BIFP6_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI__SHIFT 0x0
+#define BIFP6_PCIE_LC_SAVE_RESTORE_2__LC_SAVE_RESTORE_DATA_HI_MASK 0xFFFFFFFFL
+//BIFP6_PCIE_LC_SAVE_RESTORE_3
+#define BIFP6_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN__SHIFT 0x0
+#define BIFP6_PCIE_LC_SAVE_RESTORE_3__LC_SAVE_RESTORE_FORCE_NEAR_END_EN_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_pciedir
+//PCIE_RESERVED
+#define PCIE_RESERVED__RESERVED__SHIFT 0x0
+#define PCIE_RESERVED__RESERVED_MASK 0xFFFFFFFFL
+//PCIE_SCRATCH
+#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//PCIE_RX_NUM_NAK
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT 0x0
+#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK 0xFFFFFFFFL
+//PCIE_RX_NUM_NAK_GENERATED
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT 0x0
+#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK 0xFFFFFFFFL
+//PCIE_CNTL
+#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT 0x1
+#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT 0x9
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT 0xa
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT 0xf
+#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT 0x10
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT 0x11
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT 0x12
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT 0x13
+#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT 0x14
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT 0x15
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT 0x16
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT 0x17
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT 0x1f
+#define PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK 0x0000000EL
+#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK 0x00000200L
+#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK 0x00001C00L
+#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK 0x00008000L
+#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK 0x00010000L
+#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK 0x00020000L
+#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK 0x00040000L
+#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK 0x00080000L
+#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK 0x00100000L
+#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK 0x00200000L
+#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK 0x00400000L
+#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK 0x00800000L
+#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK 0x80000000L
+//PCIE_CONFIG_CNTL
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT 0x0
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x8
+#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x9
+#define PCIE_CONFIG_CNTL__CI_10BIT_TAG_EN_OVERRIDE__SHIFT 0xb
+#define PCIE_CONFIG_CNTL__CI_SWUS_10BIT_TAG_EN_OVERRIDE__SHIFT 0xd
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT 0x10
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x11
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x14
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x15
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT 0x18
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1b
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT 0x1c
+#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x1e
+#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK 0x0000000FL
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK 0x00000100L
+#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK 0x00000600L
+#define PCIE_CONFIG_CNTL__CI_10BIT_TAG_EN_OVERRIDE_MASK 0x00001800L
+#define PCIE_CONFIG_CNTL__CI_SWUS_10BIT_TAG_EN_OVERRIDE_MASK 0x00006000L
+#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK 0x00010000L
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK 0x000E0000L
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK 0x00100000L
+#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK 0x00E00000L
+#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK 0x01000000L
+#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK 0x08000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK 0x30000000L
+#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK 0xC0000000L
+//PCIE_TX_TRACKING_ADDR_LO
+#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT 0x2
+#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK 0xFFFFFFFCL
+//PCIE_TX_TRACKING_ADDR_HI
+#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT 0x0
+#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK 0xFFFFFFFFL
+//PCIE_TX_TRACKING_CTRL_STATUS
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT 0x0
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT 0x1
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT 0x8
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT 0xf
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK 0x00000001L
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK 0x0000000EL
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK 0x00007F00L
+#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK 0x00008000L
+//PCIE_TX_CTRL_4
+#define PCIE_TX_CTRL_4__TX_ARB_VC_ROUND_ROBIN_EN__SHIFT 0x0
+#define PCIE_TX_CTRL_4__TX_ARB_VC0_LIMIT__SHIFT 0x1
+#define PCIE_TX_CTRL_4__TX_ARB_VC1_LIMIT__SHIFT 0x6
+#define PCIE_TX_CTRL_4__TX_ARB_VC_ROUND_ROBIN_EN_MASK 0x00000001L
+#define PCIE_TX_CTRL_4__TX_ARB_VC0_LIMIT_MASK 0x0000003EL
+#define PCIE_TX_CTRL_4__TX_ARB_VC1_LIMIT_MASK 0x000007C0L
+//PCIE_MST_CTRL_1
+#define PCIE_MST_CTRL_1__MST_PDAT_CREDITS_ADVT__SHIFT 0x0
+#define PCIE_MST_CTRL_1__MST_PDAT_CREDITS_OVERRIDE_EN__SHIFT 0x8
+#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_PENDING_RESET_DIS__SHIFT 0x9
+#define PCIE_MST_CTRL_1__CI_MSTSDP_ORIG_DISC_FIX_DIS__SHIFT 0xa
+#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_OVERRIDE_EN__SHIFT 0xf
+#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_ADVT__SHIFT 0x10
+#define PCIE_MST_CTRL_1__MST_IDLE_HYSTERESIS__SHIFT 0x18
+#define PCIE_MST_CTRL_1__MST_PDAT_CREDITS_ADVT_MASK 0x000000FFL
+#define PCIE_MST_CTRL_1__MST_PDAT_CREDITS_OVERRIDE_EN_MASK 0x00000100L
+#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_PENDING_RESET_DIS_MASK 0x00000200L
+#define PCIE_MST_CTRL_1__CI_MSTSDP_ORIG_DISC_FIX_DIS_MASK 0x00000400L
+#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_OVERRIDE_EN_MASK 0x00008000L
+#define PCIE_MST_CTRL_1__MST_PHDR_CREDITS_ADVT_MASK 0x00FF0000L
+#define PCIE_MST_CTRL_1__MST_IDLE_HYSTERESIS_MASK 0xFF000000L
+//PCIE_COMMON_AER_MASK
+#define PCIE_COMMON_AER_MASK__PRIV_SURP_DIS_VEC__SHIFT 0x0
+#define PCIE_COMMON_AER_MASK__PRIV_SURP_DIS_VEC_MASK 0x000000FFL
+//PCIE_CNTL2
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT 0x0
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT 0x1
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT 0x6
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT 0xb
+#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT 0xc
+#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT 0xd
+#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT 0xe
+#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT 0x10
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT 0x11
+#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT 0x12
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT 0x13
+#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT 0x14
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT 0x15
+#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT 0x16
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT 0x17
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT 0x18
+#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT 0x1d
+#define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT 0x1e
+#define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT 0x1f
+#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK 0x00000001L
+#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK 0x0000003EL
+#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK 0x000007C0L
+#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK 0x00000800L
+#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK 0x00001000L
+#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK 0x00002000L
+#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK 0x00004000L
+#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK 0x00020000L
+#define PCIE_CNTL2__MST_MEM_LS_EN_MASK 0x00040000L
+#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK 0x00080000L
+#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK 0x00100000L
+#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK 0x00200000L
+#define PCIE_CNTL2__MST_MEM_SD_EN_MASK 0x00400000L
+#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK 0x00800000L
+#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK 0x1F000000L
+#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK 0x20000000L
+#define PCIE_CNTL2__MST_MEM_DS_EN_MASK 0x40000000L
+#define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK 0x80000000L
+//PCIE_RX_CNTL2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT 0x1
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT 0x2
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT 0x3
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT 0x4
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT 0x5
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT 0x8
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT 0x9
+#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT 0xc
+#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT 0xd
+#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT 0xe
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT 0x10
+#define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define PCIE_RX_CNTL2__RX_PD_OVERFLOW_FIX_DISABLE__SHIFT 0x1f
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK 0x00000002L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK 0x00000004L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK 0x00000008L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK 0x00000010L
+#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK 0x00000020L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK 0x00000100L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK 0x00000E00L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK 0x00001000L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK 0x00002000L
+#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK 0x00004000L
+#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK 0x03FF0000L
+#define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+#define PCIE_RX_CNTL2__RX_PD_OVERFLOW_FIX_DISABLE_MASK 0x80000000L
+//PCIE_TX_F0_ATTR_CNTL
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK 0x00000003L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK 0x0000000CL
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK 0x00000030L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK 0x000000C0L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK 0x00000300L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK 0x00000C00L
+#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK 0x00003000L
+//PCIE_TX_SWUS_ATTR_CNTL
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT 0x0
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT 0x2
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT 0x4
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT 0x6
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT 0x8
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT 0xa
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT 0xc
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK 0x00000003L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK 0x0000000CL
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK 0x00000030L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK 0x000000C0L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK 0x00000300L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK 0x00000C00L
+#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK 0x00003000L
+//PCIE_CI_CNTL
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT 0x2
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT 0x4
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT 0x6
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT 0x8
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT 0x9
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT 0xa
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT 0xb
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT 0xc
+#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT 0x10
+#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS__SHIFT 0x11
+#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS__SHIFT 0x12
+#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS__SHIFT 0x13
+#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS__SHIFT 0x14
+#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG__SHIFT 0x15
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT 0x16
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT 0x17
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT 0x18
+#define PCIE_CI_CNTL__CI_MSTSPLIT_DIS__SHIFT 0x19
+#define PCIE_CI_CNTL__CI_MSTSPLIT_REQ_CHAIN_DIS__SHIFT 0x1a
+#define PCIE_CI_CNTL__TX_MWR_SPLIT_QW_PKT_SAFE_MODE__SHIFT 0x1b
+#define PCIE_CI_CNTL__CI_MST_TAG_BORROWING_DIS__SHIFT 0x1c
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN__SHIFT 0x1d
+#define PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN__SHIFT 0x1e
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN__SHIFT 0x1f
+#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK 0x00000004L
+#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK 0x00000010L
+#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK 0x000000C0L
+#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK 0x00000100L
+#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK 0x00000200L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK 0x00000400L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK 0x00000800L
+#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK 0x00001000L
+#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK 0x00010000L
+#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS_MASK 0x00020000L
+#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS_MASK 0x00040000L
+#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS_MASK 0x00080000L
+#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS_MASK 0x00100000L
+#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG_MASK 0x00200000L
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK 0x00400000L
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK 0x00800000L
+#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK 0x01000000L
+#define PCIE_CI_CNTL__CI_MSTSPLIT_DIS_MASK 0x02000000L
+#define PCIE_CI_CNTL__CI_MSTSPLIT_REQ_CHAIN_DIS_MASK 0x04000000L
+#define PCIE_CI_CNTL__TX_MWR_SPLIT_QW_PKT_SAFE_MODE_MASK 0x08000000L
+#define PCIE_CI_CNTL__CI_MST_TAG_BORROWING_DIS_MASK 0x10000000L
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_SC_IN_LINK_DOWN_EN_MASK 0x20000000L
+#define PCIE_CI_CNTL__SLV_ARB_LINKWIDTH_WEIGHTED_RROBIN_EN_MASK 0x40000000L
+#define PCIE_CI_CNTL__RX_RCB_RC_CTO_IGNORE_ERR_IN_LINK_DOWN_EN_MASK 0x80000000L
+//PCIE_BUS_CNTL
+#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT 0x6
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT 0xc
+#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK 0x00000040L
+#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK 0x00001000L
+//PCIE_LC_STATE6
+#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT 0x0
+#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT 0x8
+#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT 0x10
+#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT 0x18
+#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK 0x0000003FL
+#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK 0x00003F00L
+#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK 0x003F0000L
+#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK 0x3F000000L
+//PCIE_LC_STATE7
+#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT 0x0
+#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT 0x8
+#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT 0x10
+#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT 0x18
+#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK 0x0000003FL
+#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK 0x00003F00L
+#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK 0x003F0000L
+#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK 0x3F000000L
+//PCIE_LC_STATE8
+#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT 0x0
+#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT 0x8
+#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT 0x10
+#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT 0x18
+#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK 0x0000003FL
+#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK 0x00003F00L
+#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK 0x003F0000L
+#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK 0x3F000000L
+//PCIE_LC_STATE9
+#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT 0x0
+#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT 0x8
+#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT 0x10
+#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT 0x18
+#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK 0x0000003FL
+#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK 0x00003F00L
+#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK 0x003F0000L
+#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK 0x3F000000L
+//PCIE_LC_STATE10
+#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT 0x0
+#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT 0x8
+#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT 0x10
+#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT 0x18
+#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK 0x0000003FL
+#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK 0x00003F00L
+#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK 0x003F0000L
+#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK 0x3F000000L
+//PCIE_LC_STATE11
+#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT 0x0
+#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT 0x8
+#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT 0x10
+#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT 0x18
+#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK 0x0000003FL
+#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK 0x00003F00L
+#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK 0x003F0000L
+#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK 0x3F000000L
+//PCIE_LC_STATUS1
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT 0x0
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT 0x1
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT 0x2
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT 0x5
+#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK 0x00000001L
+#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK 0x00000002L
+#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK 0x0000001CL
+#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L
+//PCIE_LC_STATUS2
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT 0x0
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT 0x10
+#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK 0x0000FFFFL
+#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK 0xFFFF0000L
+//PCIE_TX_CNTL3
+#define PCIE_TX_CNTL3__TX_REGNUM_FROM_ADDR_CFGWR_IOWR_DIS__SHIFT 0x0
+#define PCIE_TX_CNTL3__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE__SHIFT 0x1
+#define PCIE_TX_CNTL3__TX_STOP_TLP2_IN_REPLAY_DIS__SHIFT 0x4
+#define PCIE_TX_CNTL3__TX_PDAT_CREDIT_RELEASE_FIX_DIS__SHIFT 0x5
+#define PCIE_TX_CNTL3__TX_ARB_P_AFTER_NP_EN__SHIFT 0x6
+#define PCIE_TX_CNTL3__TX_RBUF_DELAY_2HDR_MWR_EN__SHIFT 0x7
+#define PCIE_TX_CNTL3__TX_RBUF_DELAY_MWR_SIZE__SHIFT 0x8
+#define PCIE_TX_CNTL3__TX_ENCMSG_HDR_FROM_SDP_REQ_EN__SHIFT 0x13
+#define PCIE_TX_CNTL3__TX_DROP_REQ_TARGETING_BAD_PORT_EN__SHIFT 0x14
+#define PCIE_TX_CNTL3__MCA_CLKGATE_DIS__SHIFT 0x15
+#define PCIE_TX_CNTL3__TX_PMFSM_OLD_MODE__SHIFT 0x16
+#define PCIE_TX_CNTL3__TX_MPDAT_EVICT_TAIL_FIX_DIS__SHIFT 0x17
+#define PCIE_TX_CNTL3__TX_CHK_FC_FOR_L1_DIS__SHIFT 0x18
+#define PCIE_TX_CNTL3__TX_8B_CPL_AND_WRITE_EN__SHIFT 0x19
+#define PCIE_TX_CNTL3__TX_B2B_ACK_FIX_DIS__SHIFT 0x1a
+#define PCIE_TX_CNTL3__TXDLLP_B2B_DIS__SHIFT 0x1b
+#define PCIE_TX_CNTL3__TXDL_TLP_AFTER_DLLP_EN__SHIFT 0x1c
+#define PCIE_TX_CNTL3__TXDL_STP_SDP_AT_DW3_EN__SHIFT 0x1d
+#define PCIE_TX_CNTL3__TX_SILENT_DROP_P_IN_L1SS_DIS__SHIFT 0x1e
+#define PCIE_TX_CNTL3__TX_SILENT_DROP_NP_IN_L1SS_DIS__SHIFT 0x1f
+#define PCIE_TX_CNTL3__TX_REGNUM_FROM_ADDR_CFGWR_IOWR_DIS_MASK 0x00000001L
+#define PCIE_TX_CNTL3__CI_SLV_CPL_ALLOC_OVERSUBSCRIBE_MODE_MASK 0x0000000EL
+#define PCIE_TX_CNTL3__TX_STOP_TLP2_IN_REPLAY_DIS_MASK 0x00000010L
+#define PCIE_TX_CNTL3__TX_PDAT_CREDIT_RELEASE_FIX_DIS_MASK 0x00000020L
+#define PCIE_TX_CNTL3__TX_ARB_P_AFTER_NP_EN_MASK 0x00000040L
+#define PCIE_TX_CNTL3__TX_RBUF_DELAY_2HDR_MWR_EN_MASK 0x00000080L
+#define PCIE_TX_CNTL3__TX_RBUF_DELAY_MWR_SIZE_MASK 0x0000FF00L
+#define PCIE_TX_CNTL3__TX_ENCMSG_HDR_FROM_SDP_REQ_EN_MASK 0x00080000L
+#define PCIE_TX_CNTL3__TX_DROP_REQ_TARGETING_BAD_PORT_EN_MASK 0x00100000L
+#define PCIE_TX_CNTL3__MCA_CLKGATE_DIS_MASK 0x00200000L
+#define PCIE_TX_CNTL3__TX_PMFSM_OLD_MODE_MASK 0x00400000L
+#define PCIE_TX_CNTL3__TX_MPDAT_EVICT_TAIL_FIX_DIS_MASK 0x00800000L
+#define PCIE_TX_CNTL3__TX_CHK_FC_FOR_L1_DIS_MASK 0x01000000L
+#define PCIE_TX_CNTL3__TX_8B_CPL_AND_WRITE_EN_MASK 0x02000000L
+#define PCIE_TX_CNTL3__TX_B2B_ACK_FIX_DIS_MASK 0x04000000L
+#define PCIE_TX_CNTL3__TXDLLP_B2B_DIS_MASK 0x08000000L
+#define PCIE_TX_CNTL3__TXDL_TLP_AFTER_DLLP_EN_MASK 0x10000000L
+#define PCIE_TX_CNTL3__TXDL_STP_SDP_AT_DW3_EN_MASK 0x20000000L
+#define PCIE_TX_CNTL3__TX_SILENT_DROP_P_IN_L1SS_DIS_MASK 0x40000000L
+#define PCIE_TX_CNTL3__TX_SILENT_DROP_NP_IN_L1SS_DIS_MASK 0x80000000L
+//PCIE_TX_STATUS
+#define PCIE_TX_STATUS__TX_MST_MEM_READY__SHIFT 0x0
+#define PCIE_TX_STATUS__CI_MST_REQ_IDLE__SHIFT 0x1
+#define PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD__SHIFT 0x2
+#define PCIE_TX_STATUS__CI_MST_WRRSP_IDLE__SHIFT 0x3
+#define PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE__SHIFT 0x4
+#define PCIE_TX_STATUS__CI_MST_TX_IDLE__SHIFT 0x5
+#define PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE__SHIFT 0x6
+#define PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE__SHIFT 0x7
+#define PCIE_TX_STATUS__TX_P_HDR_EMPTY__SHIFT 0x8
+#define PCIE_TX_STATUS__TX_NP_HDR_EMPTY__SHIFT 0x9
+#define PCIE_TX_STATUS__TX_P_DAT_EMPTY__SHIFT 0xa
+#define PCIE_TX_STATUS__TX_NP_DAT_EMPTY__SHIFT 0xb
+#define PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS__SHIFT 0xc
+#define PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS__SHIFT 0xd
+#define PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS__SHIFT 0xe
+#define PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS__SHIFT 0xf
+#define PCIE_TX_STATUS__TX_MST_MEM_READY_MASK 0x00000001L
+#define PCIE_TX_STATUS__CI_MST_REQ_IDLE_MASK 0x00000002L
+#define PCIE_TX_STATUS__CI_NO_PENDING_MST_MRD_MASK 0x00000004L
+#define PCIE_TX_STATUS__CI_MST_WRRSP_IDLE_MASK 0x00000008L
+#define PCIE_TX_STATUS__CI_SLV_RDRSP_IDLE_MASK 0x00000010L
+#define PCIE_TX_STATUS__CI_MST_TX_IDLE_MASK 0x00000020L
+#define PCIE_TX_STATUS__CI_SLV_CLKREQ_IDLE_MASK 0x00000040L
+#define PCIE_TX_STATUS__CI_MST_CLKREQ_IDLE_MASK 0x00000080L
+#define PCIE_TX_STATUS__TX_P_HDR_EMPTY_MASK 0x00000100L
+#define PCIE_TX_STATUS__TX_NP_HDR_EMPTY_MASK 0x00000200L
+#define PCIE_TX_STATUS__TX_P_DAT_EMPTY_MASK 0x00000400L
+#define PCIE_TX_STATUS__TX_NP_DAT_EMPTY_MASK 0x00000800L
+#define PCIE_TX_STATUS__CI_P_HDR_NO_FREE_CREDITS_MASK 0x00001000L
+#define PCIE_TX_STATUS__CI_NP_HDR_NO_FREE_CREDITS_MASK 0x00002000L
+#define PCIE_TX_STATUS__CI_P_DAT_NO_FREE_CREDITS_MASK 0x00004000L
+#define PCIE_TX_STATUS__CI_NP_DAT_NO_FREE_CREDITS_MASK 0x00008000L
+//PCIE_WPR_CNTL
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT 0x0
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT 0x1
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT 0x2
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT 0x3
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT 0x4
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT 0x5
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT 0x6
+#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK 0x00000001L
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK 0x00000002L
+#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK 0x00000004L
+#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK 0x00000008L
+#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK 0x00000010L
+#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK 0x00000020L
+#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK 0x00000040L
+//PCIE_RX_LAST_TLP0
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT 0x0
+#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK 0xFFFFFFFFL
+//PCIE_RX_LAST_TLP1
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT 0x0
+#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK 0xFFFFFFFFL
+//PCIE_RX_LAST_TLP2
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT 0x0
+#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK 0xFFFFFFFFL
+//PCIE_RX_LAST_TLP3
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT 0x0
+#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT 0x0
+#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP1
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT 0x0
+#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP2
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT 0x0
+#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK 0xFFFFFFFFL
+//PCIE_TX_LAST_TLP3
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT 0x0
+#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK 0xFFFFFFFFL
+//PCIE_I2C_REG_ADDR_EXPAND
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT 0x0
+#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK 0x0001FFFFL
+//PCIE_I2C_REG_DATA
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT 0x0
+#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK 0xFFFFFFFFL
+//PCIE_CFG_CNTL
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+//PCIE_LC_PM_CNTL
+#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT 0x0
+#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT 0x4
+#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT 0x8
+#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT 0xc
+#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT 0x10
+#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT 0x14
+#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT 0x18
+#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT 0x1c
+#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK 0x0000000FL
+#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK 0x000000F0L
+#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK 0x00000F00L
+#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK 0x0000F000L
+#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK 0x000F0000L
+#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK 0x00F00000L
+#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK 0x0F000000L
+#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK 0xF0000000L
+//PCIE_LC_PORT_ORDER_CNTL
+#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN__SHIFT 0x0
+#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN_MASK 0x00000001L
+//PCIE_P_CNTL
+#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT 0x0
+#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT 0x1
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT 0x4
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT 0x5
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT 0x6
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT 0x7
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT 0x8
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT 0xc
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT 0xd
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT 0xe
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT 0x10
+#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT 0x11
+#define PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT__SHIFT 0x12
+#define PCIE_P_CNTL__MASTER_PLL_LANE_NUM__SHIFT 0x13
+#define PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN__SHIFT 0x17
+#define PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL__SHIFT 0x18
+#define PCIE_P_CNTL__P_PWRDN_EN_MASK 0x00000001L
+#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK 0x00000002L
+#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK 0x00000010L
+#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK 0x00000020L
+#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK 0x00000040L
+#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK 0x00000080L
+#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK 0x00000100L
+#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK 0x00001000L
+#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK 0x00002000L
+#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK 0x0000C000L
+#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK 0x00010000L
+#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK 0x00020000L
+#define PCIE_P_CNTL__LC_PCLK_USE_OLD_CLOCK_CIRCUIT_MASK 0x00040000L
+#define PCIE_P_CNTL__MASTER_PLL_LANE_NUM_MASK 0x00780000L
+#define PCIE_P_CNTL__MASTER_PLL_LANE_REFCLKREQ_EN_MASK 0x00800000L
+#define PCIE_P_CNTL__REFCLKREQ_WAIT_FOR_MASTER_PLL_MASK 0x01000000L
+//PCIE_P_BUF_STATUS
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT 0x0
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT 0x10
+#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK 0x0000FFFFL
+#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK 0xFFFF0000L
+//PCIE_P_DECODER_STATUS
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT 0x0
+#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK 0x0000FFFFL
+//PCIE_P_MISC_STATUS
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT 0x0
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT 0x10
+#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK 0x000000FFL
+#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK 0xFFFF0000L
+//PCIE_P_RCV_L0S_FTS_DET
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT 0x0
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT 0x8
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK 0x000000FFL
+#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK 0x0000FF00L
+//PCIE_TX_CCIX_CNTL0
+#define PCIE_TX_CCIX_CNTL0__TXCCIX_SDP_ENABLE__SHIFT 0x0
+#define PCIE_TX_CCIX_CNTL0__TXCCIX_L1_ON_SDP_DISCONNECT_EN__SHIFT 0x1
+#define PCIE_TX_CCIX_CNTL0__CCIX_SYNCFLOOD_DIS__SHIFT 0x2
+#define PCIE_TX_CCIX_CNTL0__TXCCIX_FLUSH_DIS__SHIFT 0x3
+#define PCIE_TX_CCIX_CNTL0__TXCCIX_SDP_ENABLE_MASK 0x00000001L
+#define PCIE_TX_CCIX_CNTL0__TXCCIX_L1_ON_SDP_DISCONNECT_EN_MASK 0x00000002L
+#define PCIE_TX_CCIX_CNTL0__CCIX_SYNCFLOOD_DIS_MASK 0x00000004L
+#define PCIE_TX_CCIX_CNTL0__TXCCIX_FLUSH_DIS_MASK 0x00000008L
+//PCIE_TX_CCIX_CNTL1
+#define PCIE_TX_CCIX_CNTL1__TXCCIX_VENDOR_ID__SHIFT 0x0
+#define PCIE_TX_CCIX_CNTL1__TXCCIX_VENDOR_ID_MASK 0x0000FFFFL
+//PCIE_TX_CCIX_PORT_MAP
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_SDP_PORT_NUM_INSERT_EN__SHIFT 0x0
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_SDP_PORT_NUM_INSERT_SEL__SHIFT 0x1
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_MODE_EN__SHIFT 0x4
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_PORT_NUMBER__SHIFT 0x5
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_FIRST_CCIX_PORT_NUM__SHIFT 0x8
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_ADDR_SEL__SHIFT 0xa
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_ADDR_REMOVE0__SHIFT 0xe
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_ADDR_REMOVE1__SHIFT 0xf
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_SDP_PORT_NUM_INSERT_EN_MASK 0x00000001L
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_SDP_PORT_NUM_INSERT_SEL_MASK 0x0000000EL
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_MODE_EN_MASK 0x00000010L
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_PORT_NUMBER_MASK 0x000000E0L
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_FIRST_CCIX_PORT_NUM_MASK 0x00000300L
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_ADDR_SEL_MASK 0x00003C00L
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_ADDR_REMOVE0_MASK 0x00004000L
+#define PCIE_TX_CCIX_PORT_MAP__CCIX_INTERLEAVED_ADDR_REMOVE1_MASK 0x00008000L
+//PCIE_TX_CCIX_ERR_CTL
+#define PCIE_TX_CCIX_ERR_CTL__RX_CCIX_WRRSP_NONDATAERR_MODE__SHIFT 0x0
+#define PCIE_TX_CCIX_ERR_CTL__RX_CCIX_RDRSP_NONDATAERR_MODE__SHIFT 0x2
+#define PCIE_TX_CCIX_ERR_CTL__RX_CCIX_RDRSP_DATAERR_MODE__SHIFT 0x5
+#define PCIE_TX_CCIX_ERR_CTL__TXCCIX_MASK_POISON_EN__SHIFT 0x8
+#define PCIE_TX_CCIX_ERR_CTL__RX_CCIX_WRRSP_NONDATAERR_MODE_MASK 0x00000003L
+#define PCIE_TX_CCIX_ERR_CTL__RX_CCIX_RDRSP_NONDATAERR_MODE_MASK 0x0000001CL
+#define PCIE_TX_CCIX_ERR_CTL__RX_CCIX_RDRSP_DATAERR_MODE_MASK 0x000000E0L
+#define PCIE_TX_CCIX_ERR_CTL__TXCCIX_MASK_POISON_EN_MASK 0x00000100L
+//PCIE_RX_CCIX_CTL0
+#define PCIE_RX_CCIX_CTL0__RXCCIX_CTO_VALUE__SHIFT 0x0
+#define PCIE_RX_CCIX_CTL0__RXCCIX_CTO_STATUS__SHIFT 0x3
+#define PCIE_RX_CCIX_CTL0__TXCCIX_REQMUX_MODE__SHIFT 0xe
+#define PCIE_RX_CCIX_CTL0__TXCCIX_REQ_MUXTIME_LIMIT__SHIFT 0x10
+#define PCIE_RX_CCIX_CTL0__RXCCIX_CTO_VALUE_MASK 0x00000007L
+#define PCIE_RX_CCIX_CTL0__RXCCIX_CTO_STATUS_MASK 0x00000038L
+#define PCIE_RX_CCIX_CTL0__TXCCIX_REQMUX_MODE_MASK 0x00004000L
+#define PCIE_RX_CCIX_CTL0__TXCCIX_REQ_MUXTIME_LIMIT_MASK 0x00FF0000L
+//PCIE_RX_AD
+#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT 0x0
+#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT 0x1
+#define PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT 0x2
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT 0x3
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT 0x4
+#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT 0x5
+#define PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT 0x8
+#define PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT 0x9
+#define PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT 0xa
+#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT 0xb
+#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT 0xc
+#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT 0xd
+#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT 0xe
+#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT 0xf
+#define PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN__SHIFT 0x10
+#define PCIE_RX_AD__RX_RC_UR_POIS_ATOP__SHIFT 0x11
+#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK 0x00000001L
+#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK 0x00000002L
+#define PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK 0x00000004L
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK 0x00000008L
+#define PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK 0x00000010L
+#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK 0x00000020L
+#define PCIE_RX_AD__RX_RC_DROP_VDM0_MASK 0x00000100L
+#define PCIE_RX_AD__RX_RC_UR_VDM0_MASK 0x00000200L
+#define PCIE_RX_AD__RX_RC_DROP_VDM1_MASK 0x00000400L
+#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK 0x00000800L
+#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK 0x00001000L
+#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK 0x00002000L
+#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK 0x00004000L
+#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK 0x00008000L
+#define PCIE_RX_AD__RX_SB_DROP_LTAR_VDM_EN_MASK 0x00010000L
+#define PCIE_RX_AD__RX_RC_UR_POIS_ATOP_MASK 0x00020000L
+//PCIE_SDP_CTRL
+#define PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT 0x0
+#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT 0x4
+#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT 0x5
+#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE__SHIFT 0x6
+#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS__SHIFT 0x7
+#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS__SHIFT 0x8
+#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT 0x9
+#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT 0xa
+#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT 0xb
+#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT 0xc
+#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN__SHIFT 0xd
+#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL__SHIFT 0xe
+#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT 0xf
+#define PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN__SHIFT 0x10
+#define PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN__SHIFT 0x11
+#define PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN__SHIFT 0x12
+#define PCIE_SDP_CTRL__TX_ENCMSG_USE_SDP_EP_DIS__SHIFT 0x13
+#define PCIE_SDP_CTRL__TX_IGNORE_POISON_BIT_EN__SHIFT 0x14
+#define PCIE_SDP_CTRL__TX_RBUF_WRITE_2HDR_DIS__SHIFT 0x15
+#define PCIE_SDP_CTRL__TX_RBUF_READ_2HDR_DIS__SHIFT 0x16
+#define PCIE_SDP_CTRL__TX_RBUF_END_TLP2_DIS__SHIFT 0x17
+#define PCIE_SDP_CTRL__TX_MULTICYCLE_DLLP_DIS__SHIFT 0x18
+#define PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE__SHIFT 0x19
+#define PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER__SHIFT 0x1a
+#define PCIE_SDP_CTRL__CI_SDP_RECONFIG_EN__SHIFT 0x1d
+#define PCIE_SDP_CTRL__TX_ENCMSG_REQID_FROM_REQSTREAMID_EN__SHIFT 0x1e
+#define PCIE_SDP_CTRL__SDP_UNIT_ID_MASK 0x0000000FL
+#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK 0x00000010L
+#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK 0x00000020L
+#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE_MASK 0x00000040L
+#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS_MASK 0x00000080L
+#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS_MASK 0x00000100L
+#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK 0x00000200L
+#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK 0x00000400L
+#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK 0x00000800L
+#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK 0x00001000L
+#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN_MASK 0x00002000L
+#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL_MASK 0x00004000L
+#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK 0x00008000L
+#define PCIE_SDP_CTRL__EARLY_HW_WAKE_UP_EN_MASK 0x00010000L
+#define PCIE_SDP_CTRL__SLV_SDP_DISCONNECT_WHEN_IN_L1_EN_MASK 0x00020000L
+#define PCIE_SDP_CTRL__BLOCK_SLV_SDP_DISCONNECT_WHEN_EARLY_HW_WAKE_UP_EN_MASK 0x00040000L
+#define PCIE_SDP_CTRL__TX_ENCMSG_USE_SDP_EP_DIS_MASK 0x00080000L
+#define PCIE_SDP_CTRL__TX_IGNORE_POISON_BIT_EN_MASK 0x00100000L
+#define PCIE_SDP_CTRL__TX_RBUF_WRITE_2HDR_DIS_MASK 0x00200000L
+#define PCIE_SDP_CTRL__TX_RBUF_READ_2HDR_DIS_MASK 0x00400000L
+#define PCIE_SDP_CTRL__TX_RBUF_END_TLP2_DIS_MASK 0x00800000L
+#define PCIE_SDP_CTRL__TX_MULTICYCLE_DLLP_DIS_MASK 0x01000000L
+#define PCIE_SDP_CTRL__CI_VIRTUAL_WIRE_MODE_MASK 0x02000000L
+#define PCIE_SDP_CTRL__SDP_UNIT_ID_LOWER_MASK 0x1C000000L
+#define PCIE_SDP_CTRL__CI_SDP_RECONFIG_EN_MASK 0x20000000L
+#define PCIE_SDP_CTRL__TX_ENCMSG_REQID_FROM_REQSTREAMID_EN_MASK 0x40000000L
+//NBIO_CLKREQb_MAP_CNTL
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_0_MAP__SHIFT 0x0
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_1_MAP__SHIFT 0x4
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_2_MAP__SHIFT 0x8
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_3_MAP__SHIFT 0xc
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_4_MAP__SHIFT 0x10
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_5_MAP__SHIFT 0x14
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_6_MAP__SHIFT 0x18
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_CNTL_MASK__SHIFT 0x1c
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_0_MAP_MASK 0x0000000FL
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_1_MAP_MASK 0x000000F0L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_2_MAP_MASK 0x00000F00L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_3_MAP_MASK 0x0000F000L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_4_MAP_MASK 0x000F0000L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_5_MAP_MASK 0x00F00000L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_6_MAP_MASK 0x0F000000L
+#define NBIO_CLKREQb_MAP_CNTL__PCIE_CLKREQB_CNTL_MASK_MASK 0x10000000L
+//PCIE_SDP_SWUS_SLV_ATTR_CTRL
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT 0x0
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT 0x2
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT 0x4
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT 0x6
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT 0x8
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT 0xa
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT 0xc
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT 0xe
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT 0x10
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK 0x00000003L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK 0x0000000CL
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK 0x00000030L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK 0x000000C0L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK 0x00000300L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK 0x00000C00L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK 0x00003000L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK 0x0000C000L
+#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK 0x00030000L
+//PCIE_SDP_RC_SLV_ATTR_CTRL
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMWR__SHIFT 0x0
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMRD__SHIFT 0x2
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_ATOMIC__SHIFT 0x4
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMWR__SHIFT 0x6
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMRD__SHIFT 0x8
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_ATOMIC__SHIFT 0xa
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMWR__SHIFT 0xc
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMRD__SHIFT 0xe
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_ATOMIC__SHIFT 0x10
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMWR_MASK 0x00000003L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_MEMRD_MASK 0x0000000CL
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_RO_OVERRIDE_ATOMIC_MASK 0x00000030L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMWR_MASK 0x000000C0L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_MEMRD_MASK 0x00000300L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_SNR_OVERRIDE_ATOMIC_MASK 0x00000C00L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMWR_MASK 0x00003000L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_MEMRD_MASK 0x0000C000L
+#define PCIE_SDP_RC_SLV_ATTR_CTRL__CI_RC_SLV_IDO_OVERRIDE_ATOMIC_MASK 0x00030000L
+//PCIE_PERF_COUNT_CNTL
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT 0x0
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT 0x1
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT 0x2
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_SCLK_STATUS__SHIFT 0x1f
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK 0x00000001L
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK 0x00000002L
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK 0x00000004L
+#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_SCLK_STATUS_MASK 0x80000000L
+//PCIE_PERF_CNTL_TXCLK1
+#define PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK1__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK1__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK1__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK1__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK1__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK1__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK1
+#define PCIE_PERF_COUNT0_TXCLK1__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK1__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK1
+#define PCIE_PERF_COUNT1_TXCLK1__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK1__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK2
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK2
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK2
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK3
+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK3__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK3__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK3__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK3
+#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK3__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK3
+#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK3__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_TXCLK4
+#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_TXCLK4__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_TXCLK4__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_TXCLK4__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_TXCLK4
+#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_TXCLK4__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_TXCLK4
+#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_TXCLK4__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_SCLK1
+#define PCIE_PERF_CNTL_SCLK1__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SCLK1__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SCLK1__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SCLK1__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_SCLK1__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_SCLK1__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_SCLK1__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_SCLK1__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_SCLK1
+#define PCIE_PERF_COUNT0_SCLK1__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_SCLK1__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_SCLK1
+#define PCIE_PERF_COUNT1_SCLK1__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SCLK1__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_SCLK2
+#define PCIE_PERF_CNTL_SCLK2__EVENT0_SEL__SHIFT 0x0
+#define PCIE_PERF_CNTL_SCLK2__EVENT1_SEL__SHIFT 0x8
+#define PCIE_PERF_CNTL_SCLK2__COUNTER0_UPPER__SHIFT 0x10
+#define PCIE_PERF_CNTL_SCLK2__COUNTER1_UPPER__SHIFT 0x18
+#define PCIE_PERF_CNTL_SCLK2__EVENT0_SEL_MASK 0x000000FFL
+#define PCIE_PERF_CNTL_SCLK2__EVENT1_SEL_MASK 0x0000FF00L
+#define PCIE_PERF_CNTL_SCLK2__COUNTER0_UPPER_MASK 0x00FF0000L
+#define PCIE_PERF_CNTL_SCLK2__COUNTER1_UPPER_MASK 0xFF000000L
+//PCIE_PERF_COUNT0_SCLK2
+#define PCIE_PERF_COUNT0_SCLK2__COUNTER0__SHIFT 0x0
+#define PCIE_PERF_COUNT0_SCLK2__COUNTER0_MASK 0xFFFFFFFFL
+//PCIE_PERF_COUNT1_SCLK2
+#define PCIE_PERF_COUNT1_SCLK2__COUNTER1__SHIFT 0x0
+#define PCIE_PERF_COUNT1_SCLK2__COUNTER1_MASK 0xFFFFFFFFL
+//PCIE_PERF_CNTL_EVENT_LC_PORT_SEL
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK1_MASK 0x0000000FL
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK1_MASK 0x000000F0L
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK 0x00000F00L
+#define PCIE_PERF_CNTL_EVENT_LC_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK 0x0000F000L
+//PCIE_PERF_CNTL_EVENT_CI_PORT_SEL
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3__SHIFT 0x0
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3__SHIFT 0x4
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4__SHIFT 0x8
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4__SHIFT 0xc
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK1__SHIFT 0x10
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK1__SHIFT 0x14
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK2__SHIFT 0x18
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK2__SHIFT 0x1c
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK3_MASK 0x0000000FL
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK3_MASK 0x000000F0L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_TXCLK4_MASK 0x00000F00L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_TXCLK4_MASK 0x0000F000L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK1_MASK 0x000F0000L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK1_MASK 0x00F00000L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF0_PORT_SEL_SCLK2_MASK 0x0F000000L
+#define PCIE_PERF_CNTL_EVENT_CI_PORT_SEL__PERF1_PORT_SEL_SCLK2_MASK 0xF0000000L
+//PCIE_STRAP_F0
+#define PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN__SHIFT 0x1
+#define PCIE_STRAP_F0__STRAP_F0_MSI_EN__SHIFT 0x2
+#define PCIE_STRAP_F0__STRAP_F0_VC_EN__SHIFT 0x3
+#define PCIE_STRAP_F0__STRAP_F0_DSN_EN__SHIFT 0x4
+#define PCIE_STRAP_F0__STRAP_F0_AER_EN__SHIFT 0x5
+#define PCIE_STRAP_F0__STRAP_F0_ACS_EN__SHIFT 0x6
+#define PCIE_STRAP_F0__STRAP_F0_BAR_EN__SHIFT 0x7
+#define PCIE_STRAP_F0__STRAP_F0_PWR_EN__SHIFT 0x8
+#define PCIE_STRAP_F0__STRAP_F0_DPA_EN__SHIFT 0x9
+#define PCIE_STRAP_F0__STRAP_F0_ATS_EN__SHIFT 0xa
+#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN__SHIFT 0xb
+#define PCIE_STRAP_F0__STRAP_F0_PASID_EN__SHIFT 0xc
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN__SHIFT 0xd
+#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL__SHIFT 0x10
+#define PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN__SHIFT 0x12
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN__SHIFT 0x13
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN__SHIFT 0x14
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP__SHIFT 0x18
+#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP__SHIFT 0x1b
+#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1c
+#define PCIE_STRAP_F0__STRAP_SWUS_ARI_EN__SHIFT 0x1d
+#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN__SHIFT 0x1e
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN__SHIFT 0x1f
+#define PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define PCIE_STRAP_F0__STRAP_F0_LEGACY_DEVICE_TYPE_EN_MASK 0x00000002L
+#define PCIE_STRAP_F0__STRAP_F0_MSI_EN_MASK 0x00000004L
+#define PCIE_STRAP_F0__STRAP_F0_VC_EN_MASK 0x00000008L
+#define PCIE_STRAP_F0__STRAP_F0_DSN_EN_MASK 0x00000010L
+#define PCIE_STRAP_F0__STRAP_F0_AER_EN_MASK 0x00000020L
+#define PCIE_STRAP_F0__STRAP_F0_ACS_EN_MASK 0x00000040L
+#define PCIE_STRAP_F0__STRAP_F0_BAR_EN_MASK 0x00000080L
+#define PCIE_STRAP_F0__STRAP_F0_PWR_EN_MASK 0x00000100L
+#define PCIE_STRAP_F0__STRAP_F0_DPA_EN_MASK 0x00000200L
+#define PCIE_STRAP_F0__STRAP_F0_ATS_EN_MASK 0x00000400L
+#define PCIE_STRAP_F0__STRAP_F0_PAGE_REQ_EN_MASK 0x00000800L
+#define PCIE_STRAP_F0__STRAP_F0_PASID_EN_MASK 0x00001000L
+#define PCIE_STRAP_F0__STRAP_F0_ECRC_CHECK_EN_MASK 0x00002000L
+#define PCIE_STRAP_F0__STRAP_F0_CPL_ABORT_ERR_EN_MASK 0x00008000L
+#define PCIE_STRAP_F0__STRAP_F0_POISONED_ADVISORY_NONFATAL_MASK 0x00010000L
+#define PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_EN_MASK 0x00040000L
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_64BIT_EN_MASK 0x00080000L
+#define PCIE_STRAP_F0__STRAP_F0_ATOMIC_ROUTING_EN_MASK 0x00100000L
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+#define PCIE_STRAP_F0__STRAP_F0_VFn_MSI_MULTI_CAP_MASK 0x07000000L
+#define PCIE_STRAP_F0__STRAP_F0_MSI_PERVECTOR_MASK_CAP_MASK 0x08000000L
+#define PCIE_STRAP_F0__STRAP_F0_NO_RO_ENABLED_P2P_PASSING_MASK 0x10000000L
+#define PCIE_STRAP_F0__STRAP_SWUS_ARI_EN_MASK 0x20000000L
+#define PCIE_STRAP_F0__STRAP_F0_SRIOV_EN_MASK 0x40000000L
+#define PCIE_STRAP_F0__STRAP_F0_MSI_MAP_EN_MASK 0x80000000L
+//PCIE_STRAP_NTB
+#define PCIE_STRAP_NTB__STRAP_NTB_MSI_EN__SHIFT 0x2
+#define PCIE_STRAP_NTB__STRAP_NTB_VC_EN__SHIFT 0x3
+#define PCIE_STRAP_NTB__STRAP_NTB_DSN_EN__SHIFT 0x4
+#define PCIE_STRAP_NTB__STRAP_NTB_AER_EN__SHIFT 0x5
+#define PCIE_STRAP_NTB__STRAP_NTB_ECRC_CHECK_EN__SHIFT 0xd
+#define PCIE_STRAP_NTB__STRAP_NTB_CPL_ABORT_ERR_EN__SHIFT 0xf
+#define PCIE_STRAP_NTB__STRAP_NTB_ATOMIC_EN__SHIFT 0x12
+#define PCIE_STRAP_NTB__STRAP_NTB_ATOMIC_64BIT_EN__SHIFT 0x13
+#define PCIE_STRAP_NTB__STRAP_NTB_ATOMIC_ROUTING_EN__SHIFT 0x14
+#define PCIE_STRAP_NTB__STRAP_NTB_LTR_SUPPORTED__SHIFT 0x15
+#define PCIE_STRAP_NTB__STRAP_NTB_OBFF_SUPPORTED__SHIFT 0x16
+#define PCIE_STRAP_NTB__STRAP_NTB_MSI_EN_MASK 0x00000004L
+#define PCIE_STRAP_NTB__STRAP_NTB_VC_EN_MASK 0x00000008L
+#define PCIE_STRAP_NTB__STRAP_NTB_DSN_EN_MASK 0x00000010L
+#define PCIE_STRAP_NTB__STRAP_NTB_AER_EN_MASK 0x00000020L
+#define PCIE_STRAP_NTB__STRAP_NTB_ECRC_CHECK_EN_MASK 0x00002000L
+#define PCIE_STRAP_NTB__STRAP_NTB_CPL_ABORT_ERR_EN_MASK 0x00008000L
+#define PCIE_STRAP_NTB__STRAP_NTB_ATOMIC_EN_MASK 0x00040000L
+#define PCIE_STRAP_NTB__STRAP_NTB_ATOMIC_64BIT_EN_MASK 0x00080000L
+#define PCIE_STRAP_NTB__STRAP_NTB_ATOMIC_ROUTING_EN_MASK 0x00100000L
+#define PCIE_STRAP_NTB__STRAP_NTB_LTR_SUPPORTED_MASK 0x00200000L
+#define PCIE_STRAP_NTB__STRAP_NTB_OBFF_SUPPORTED_MASK 0x00C00000L
+//PCIE_STRAP_MISC
+#define PCIE_STRAP_MISC__STRAP_DLF_EN__SHIFT 0x0
+#define PCIE_STRAP_MISC__STRAP_16GT_EN__SHIFT 0x1
+#define PCIE_STRAP_MISC__STRAP_MARGINING_EN__SHIFT 0x2
+#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN__SHIFT 0x4
+#define PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER__SHIFT 0x6
+#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT__SHIFT 0x1a
+#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL__SHIFT 0x1c
+#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define PCIE_STRAP_MISC__STRAP_DLF_EN_MASK 0x00000001L
+#define PCIE_STRAP_MISC__STRAP_16GT_EN_MASK 0x00000002L
+#define PCIE_STRAP_MISC__STRAP_MARGINING_EN_MASK 0x00000004L
+#define PCIE_STRAP_MISC__STRAP_TL_ALT_BUF_EN_MASK 0x00000010L
+#define PCIE_STRAP_MISC__STRAP_BYPASS_SCRAMBLER_MASK 0x00000040L
+#define PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define PCIE_STRAP_MISC__STRAP_EXT_VC_COUNT_MASK 0x04000000L
+#define PCIE_STRAP_MISC__STRAP_REVERSE_ALL_MASK 0x10000000L
+#define PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//PCIE_STRAP_MISC2
+#define PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN__SHIFT 0x0
+#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE__SHIFT 0x1
+#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE__SHIFT 0x3
+#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE__SHIFT 0x5
+#define PCIE_STRAP_MISC2__STRAP_F0_CTO_LOG_CAPABLE__SHIFT 0x6
+#define PCIE_STRAP_MISC2__STRAP_LINK_BW_NOTIFICATION_CAP_EN_MASK 0x00000001L
+#define PCIE_STRAP_MISC2__STRAP_GEN2_COMPLIANCE_MASK 0x00000002L
+#define PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+#define PCIE_STRAP_MISC2__STRAP_GEN3_COMPLIANCE_MASK 0x00000008L
+#define PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+#define PCIE_STRAP_MISC2__STRAP_GEN4_COMPLIANCE_MASK 0x00000020L
+#define PCIE_STRAP_MISC2__STRAP_F0_CTO_LOG_CAPABLE_MASK 0x00000040L
+//PCIE_STRAP_PI
+#define PCIE_STRAP_PI__STRAP_QUICKSIM_START__SHIFT 0x0
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN__SHIFT 0x1c
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE__SHIFT 0x1d
+#define PCIE_STRAP_PI__STRAP_QUICKSIM_START_MASK 0x00000001L
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_PATTERN_MASK 0x10000000L
+#define PCIE_STRAP_PI__STRAP_TEST_TOGGLE_MODE_MASK 0x20000000L
+//PCIE_STRAP_I2C_BD
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR__SHIFT 0x0
+#define PCIE_STRAP_I2C_BD__STRAP_BIF_I2C_SLV_ADR_MASK 0x0000007FL
+//PCIE_PRBS_CLR
+#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT 0x0
+#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT 0x18
+#define PCIE_PRBS_CLR__PRBS_CLR_MASK 0x0000FFFFL
+#define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK 0x01000000L
+//PCIE_PRBS_STATUS1
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT 0x0
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT 0x10
+#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK 0x0000FFFFL
+#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK 0xFFFF0000L
+//PCIE_PRBS_STATUS2
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT 0x0
+#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK 0x0000FFFFL
+//PCIE_PRBS_FREERUN
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT 0x0
+#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK 0x0000FFFFL
+//PCIE_PRBS_MISC
+#define PCIE_PRBS_MISC__PRBS_EN__SHIFT 0x0
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT 0x1
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT 0x4
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT 0x5
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT 0x6
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT 0x8
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT 0xe
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT 0x10
+#define PCIE_PRBS_MISC__PRBS_EN_MASK 0x00000001L
+#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK 0x0000000EL
+#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK 0x00000010L
+#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK 0x00000020L
+#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK 0x000000C0L
+#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK 0x00001F00L
+#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK 0x0000C000L
+#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK 0xFFFF0000L
+//PCIE_PRBS_USER_PATTERN
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT 0x0
+#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK 0x3FFFFFFFL
+//PCIE_PRBS_LO_BITCNT
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK 0xFFFFFFFFL
+//PCIE_PRBS_HI_BITCNT
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT 0x0
+#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK 0x000000FFL
+//PCIE_PRBS_ERRCNT_0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_1
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_2
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_3
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_4
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_5
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_6
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_7
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_8
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_9
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_10
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_11
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_12
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_13
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_14
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK 0xFFFFFFFFL
+//PCIE_PRBS_ERRCNT_15
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT 0x0
+#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK 0xFFFFFFFFL
+//SWRST_COMMAND_STATUS
+#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT 0x0
+#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT 0x1
+#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT 0x10
+#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT 0x11
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET__SHIFT 0x18
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY__SHIFT 0x19
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB__SHIFT 0x1a
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET__SHIFT 0x1b
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY__SHIFT 0x1c
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET__SHIFT 0x1d
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE__SHIFT 0x1e
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN__SHIFT 0x1f
+#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK 0x00000001L
+#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK 0x00000002L
+#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK 0x00010000L
+#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK 0x00020000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_MASK 0x01000000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY_MASK 0x02000000L
+#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB_MASK 0x04000000L
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_MASK 0x08000000L
+#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY_MASK 0x10000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET_MASK 0x20000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE_MASK 0x40000000L
+#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN_MASK 0x80000000L
+//SWRST_GENERAL_CONTROL
+#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT 0x0
+#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT 0x1
+#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT 0x2
+#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT 0x8
+#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT 0x9
+#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT 0xa
+#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT 0xc
+#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD__SHIFT 0x11
+#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT 0x18
+#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET__SHIFT 0x19
+#define SWRST_GENERAL_CONTROL__WAIT_FOR_SDP_CREDITS__SHIFT 0x1a
+#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK 0x00000001L
+#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK 0x00000002L
+#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK 0x0000001CL
+#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK 0x00000100L
+#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK 0x00000200L
+#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK 0x00000400L
+#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK 0x00001000L
+#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD_MASK 0x00020000L
+#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK 0x01000000L
+#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET_MASK 0x02000000L
+#define SWRST_GENERAL_CONTROL__WAIT_FOR_SDP_CREDITS_MASK 0x04000000L
+//SWRST_COMMAND_0
+#define SWRST_COMMAND_0__PORT0_COR_RESET__SHIFT 0x0
+#define SWRST_COMMAND_0__PORT0_CFG_RESET__SHIFT 0x8
+#define SWRST_COMMAND_0__PORT1_CFG_RESET__SHIFT 0x9
+#define SWRST_COMMAND_0__PORT2_CFG_RESET__SHIFT 0xa
+#define SWRST_COMMAND_0__PORT3_CFG_RESET__SHIFT 0xb
+#define SWRST_COMMAND_0__PORT4_CFG_RESET__SHIFT 0xc
+#define SWRST_COMMAND_0__PORT5_CFG_RESET__SHIFT 0xd
+#define SWRST_COMMAND_0__PORT6_CFG_RESET__SHIFT 0xe
+#define SWRST_COMMAND_0__PORT7_CFG_RESET__SHIFT 0xf
+#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT 0x18
+#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT 0x19
+#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT 0x1a
+#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT 0x1b
+#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT 0x1c
+#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT 0x1d
+#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT 0x1e
+#define SWRST_COMMAND_0__BIF0_SDP_CREDIT_RESET__SHIFT 0x1f
+#define SWRST_COMMAND_0__PORT0_COR_RESET_MASK 0x00000001L
+#define SWRST_COMMAND_0__PORT0_CFG_RESET_MASK 0x00000100L
+#define SWRST_COMMAND_0__PORT1_CFG_RESET_MASK 0x00000200L
+#define SWRST_COMMAND_0__PORT2_CFG_RESET_MASK 0x00000400L
+#define SWRST_COMMAND_0__PORT3_CFG_RESET_MASK 0x00000800L
+#define SWRST_COMMAND_0__PORT4_CFG_RESET_MASK 0x00001000L
+#define SWRST_COMMAND_0__PORT5_CFG_RESET_MASK 0x00002000L
+#define SWRST_COMMAND_0__PORT6_CFG_RESET_MASK 0x00004000L
+#define SWRST_COMMAND_0__PORT7_CFG_RESET_MASK 0x00008000L
+#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK 0x01000000L
+#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK 0x02000000L
+#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK 0x04000000L
+#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK 0x08000000L
+#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK 0x10000000L
+#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK 0x20000000L
+#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK 0x40000000L
+#define SWRST_COMMAND_0__BIF0_SDP_CREDIT_RESET_MASK 0x80000000L
+//SWRST_COMMAND_1
+#define SWRST_COMMAND_1__RESETPCS0__SHIFT 0x0
+#define SWRST_COMMAND_1__RESETPCS1__SHIFT 0x1
+#define SWRST_COMMAND_1__RESETPCS2__SHIFT 0x2
+#define SWRST_COMMAND_1__RESETPCS3__SHIFT 0x3
+#define SWRST_COMMAND_1__RESETPCS4__SHIFT 0x4
+#define SWRST_COMMAND_1__RESETPCS5__SHIFT 0x5
+#define SWRST_COMMAND_1__RESETPCS6__SHIFT 0x6
+#define SWRST_COMMAND_1__RESETPCS7__SHIFT 0x7
+#define SWRST_COMMAND_1__RESETPCS8__SHIFT 0x8
+#define SWRST_COMMAND_1__RESETPCS9__SHIFT 0x9
+#define SWRST_COMMAND_1__RESETPCS10__SHIFT 0xa
+#define SWRST_COMMAND_1__RESETPCS11__SHIFT 0xb
+#define SWRST_COMMAND_1__RESETPCS12__SHIFT 0xc
+#define SWRST_COMMAND_1__RESETPCS13__SHIFT 0xd
+#define SWRST_COMMAND_1__RESETPCS14__SHIFT 0xe
+#define SWRST_COMMAND_1__RESETPCS15__SHIFT 0xf
+#define SWRST_COMMAND_1__SWITCHCLK__SHIFT 0x15
+#define SWRST_COMMAND_1__RESETPCFG__SHIFT 0x19
+#define SWRST_COMMAND_1__RESETLNCT__SHIFT 0x1a
+#define SWRST_COMMAND_1__RESETMNTR__SHIFT 0x1b
+#define SWRST_COMMAND_1__RESETHLTR__SHIFT 0x1c
+#define SWRST_COMMAND_1__RESETCPM__SHIFT 0x1d
+#define SWRST_COMMAND_1__RESETPHY0__SHIFT 0x1e
+#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT 0x1f
+#define SWRST_COMMAND_1__RESETPCS0_MASK 0x00000001L
+#define SWRST_COMMAND_1__RESETPCS1_MASK 0x00000002L
+#define SWRST_COMMAND_1__RESETPCS2_MASK 0x00000004L
+#define SWRST_COMMAND_1__RESETPCS3_MASK 0x00000008L
+#define SWRST_COMMAND_1__RESETPCS4_MASK 0x00000010L
+#define SWRST_COMMAND_1__RESETPCS5_MASK 0x00000020L
+#define SWRST_COMMAND_1__RESETPCS6_MASK 0x00000040L
+#define SWRST_COMMAND_1__RESETPCS7_MASK 0x00000080L
+#define SWRST_COMMAND_1__RESETPCS8_MASK 0x00000100L
+#define SWRST_COMMAND_1__RESETPCS9_MASK 0x00000200L
+#define SWRST_COMMAND_1__RESETPCS10_MASK 0x00000400L
+#define SWRST_COMMAND_1__RESETPCS11_MASK 0x00000800L
+#define SWRST_COMMAND_1__RESETPCS12_MASK 0x00001000L
+#define SWRST_COMMAND_1__RESETPCS13_MASK 0x00002000L
+#define SWRST_COMMAND_1__RESETPCS14_MASK 0x00004000L
+#define SWRST_COMMAND_1__RESETPCS15_MASK 0x00008000L
+#define SWRST_COMMAND_1__SWITCHCLK_MASK 0x00200000L
+#define SWRST_COMMAND_1__RESETPCFG_MASK 0x02000000L
+#define SWRST_COMMAND_1__RESETLNCT_MASK 0x04000000L
+#define SWRST_COMMAND_1__RESETMNTR_MASK 0x08000000L
+#define SWRST_COMMAND_1__RESETHLTR_MASK 0x10000000L
+#define SWRST_COMMAND_1__RESETCPM_MASK 0x20000000L
+#define SWRST_COMMAND_1__RESETPHY0_MASK 0x40000000L
+#define SWRST_COMMAND_1__TOGGLESTRAP_MASK 0x80000000L
+//SWRST_CONTROL_0
+#define SWRST_CONTROL_0__PORT0_COR_RCEN__SHIFT 0x0
+#define SWRST_CONTROL_0__PORT0_CFG_RCEN__SHIFT 0x8
+#define SWRST_CONTROL_0__PORT1_CFG_RCEN__SHIFT 0x9
+#define SWRST_CONTROL_0__PORT2_CFG_RCEN__SHIFT 0xa
+#define SWRST_CONTROL_0__PORT3_CFG_RCEN__SHIFT 0xb
+#define SWRST_CONTROL_0__PORT4_CFG_RCEN__SHIFT 0xc
+#define SWRST_CONTROL_0__PORT5_CFG_RCEN__SHIFT 0xd
+#define SWRST_CONTROL_0__PORT6_CFG_RCEN__SHIFT 0xe
+#define SWRST_CONTROL_0__PORT7_CFG_RCEN__SHIFT 0xf
+#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT 0x18
+#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT 0x19
+#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT 0x1a
+#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT 0x1b
+#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT 0x1c
+#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT 0x1d
+#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT 0x1e
+#define SWRST_CONTROL_0__BIF0_SDP_CREDIT_RESETRCEN__SHIFT 0x1f
+#define SWRST_CONTROL_0__PORT0_COR_RCEN_MASK 0x00000001L
+#define SWRST_CONTROL_0__PORT0_CFG_RCEN_MASK 0x00000100L
+#define SWRST_CONTROL_0__PORT1_CFG_RCEN_MASK 0x00000200L
+#define SWRST_CONTROL_0__PORT2_CFG_RCEN_MASK 0x00000400L
+#define SWRST_CONTROL_0__PORT3_CFG_RCEN_MASK 0x00000800L
+#define SWRST_CONTROL_0__PORT4_CFG_RCEN_MASK 0x00001000L
+#define SWRST_CONTROL_0__PORT5_CFG_RCEN_MASK 0x00002000L
+#define SWRST_CONTROL_0__PORT6_CFG_RCEN_MASK 0x00004000L
+#define SWRST_CONTROL_0__PORT7_CFG_RCEN_MASK 0x00008000L
+#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK 0x01000000L
+#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK 0x02000000L
+#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK 0x04000000L
+#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK 0x08000000L
+#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK 0x10000000L
+#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK 0x20000000L
+#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK 0x40000000L
+#define SWRST_CONTROL_0__BIF0_SDP_CREDIT_RESETRCEN_MASK 0x80000000L
+//SWRST_CONTROL_1
+#define SWRST_CONTROL_1__PCSRESET0_RCEN__SHIFT 0x0
+#define SWRST_CONTROL_1__PCSRESET1_RCEN__SHIFT 0x1
+#define SWRST_CONTROL_1__PCSRESET2_RCEN__SHIFT 0x2
+#define SWRST_CONTROL_1__PCSRESET3_RCEN__SHIFT 0x3
+#define SWRST_CONTROL_1__PCSRESET4_RCEN__SHIFT 0x4
+#define SWRST_CONTROL_1__PCSRESET5_RCEN__SHIFT 0x5
+#define SWRST_CONTROL_1__PCSRESET6_RCEN__SHIFT 0x6
+#define SWRST_CONTROL_1__PCSRESET7_RCEN__SHIFT 0x7
+#define SWRST_CONTROL_1__PCSRESET8_RCEN__SHIFT 0x8
+#define SWRST_CONTROL_1__PCSRESET9_RCEN__SHIFT 0x9
+#define SWRST_CONTROL_1__PCSRESET10_RCEN__SHIFT 0xa
+#define SWRST_CONTROL_1__PCSRESET11_RCEN__SHIFT 0xb
+#define SWRST_CONTROL_1__PCSRESET12_RCEN__SHIFT 0xc
+#define SWRST_CONTROL_1__PCSRESET13_RCEN__SHIFT 0xd
+#define SWRST_CONTROL_1__PCSRESET14_RCEN__SHIFT 0xe
+#define SWRST_CONTROL_1__PCSRESET15_RCEN__SHIFT 0xf
+#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT 0x15
+#define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT 0x19
+#define SWRST_CONTROL_1__RESETLNCT_RCEN__SHIFT 0x1a
+#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT 0x1b
+#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT 0x1c
+#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT 0x1d
+#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT 0x1e
+#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT 0x1f
+#define SWRST_CONTROL_1__PCSRESET0_RCEN_MASK 0x00000001L
+#define SWRST_CONTROL_1__PCSRESET1_RCEN_MASK 0x00000002L
+#define SWRST_CONTROL_1__PCSRESET2_RCEN_MASK 0x00000004L
+#define SWRST_CONTROL_1__PCSRESET3_RCEN_MASK 0x00000008L
+#define SWRST_CONTROL_1__PCSRESET4_RCEN_MASK 0x00000010L
+#define SWRST_CONTROL_1__PCSRESET5_RCEN_MASK 0x00000020L
+#define SWRST_CONTROL_1__PCSRESET6_RCEN_MASK 0x00000040L
+#define SWRST_CONTROL_1__PCSRESET7_RCEN_MASK 0x00000080L
+#define SWRST_CONTROL_1__PCSRESET8_RCEN_MASK 0x00000100L
+#define SWRST_CONTROL_1__PCSRESET9_RCEN_MASK 0x00000200L
+#define SWRST_CONTROL_1__PCSRESET10_RCEN_MASK 0x00000400L
+#define SWRST_CONTROL_1__PCSRESET11_RCEN_MASK 0x00000800L
+#define SWRST_CONTROL_1__PCSRESET12_RCEN_MASK 0x00001000L
+#define SWRST_CONTROL_1__PCSRESET13_RCEN_MASK 0x00002000L
+#define SWRST_CONTROL_1__PCSRESET14_RCEN_MASK 0x00004000L
+#define SWRST_CONTROL_1__PCSRESET15_RCEN_MASK 0x00008000L
+#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK 0x00200000L
+#define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK 0x02000000L
+#define SWRST_CONTROL_1__RESETLNCT_RCEN_MASK 0x04000000L
+#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK 0x08000000L
+#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK 0x10000000L
+#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK 0x20000000L
+#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK 0x40000000L
+#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK 0x80000000L
+//SWRST_CONTROL_2
+#define SWRST_CONTROL_2__PORT0_COR_ATEN__SHIFT 0x0
+#define SWRST_CONTROL_2__PORT0_CFG_ATEN__SHIFT 0x8
+#define SWRST_CONTROL_2__PORT1_CFG_ATEN__SHIFT 0x9
+#define SWRST_CONTROL_2__PORT2_CFG_ATEN__SHIFT 0xa
+#define SWRST_CONTROL_2__PORT3_CFG_ATEN__SHIFT 0xb
+#define SWRST_CONTROL_2__PORT4_CFG_ATEN__SHIFT 0xc
+#define SWRST_CONTROL_2__PORT5_CFG_ATEN__SHIFT 0xd
+#define SWRST_CONTROL_2__PORT6_CFG_ATEN__SHIFT 0xe
+#define SWRST_CONTROL_2__PORT7_CFG_ATEN__SHIFT 0xf
+#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT 0x18
+#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT 0x19
+#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT 0x1a
+#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT 0x1b
+#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT 0x1c
+#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT 0x1d
+#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT 0x1e
+#define SWRST_CONTROL_2__BIF0_SDP_CREDIT_RESETATEN__SHIFT 0x1f
+#define SWRST_CONTROL_2__PORT0_COR_ATEN_MASK 0x00000001L
+#define SWRST_CONTROL_2__PORT0_CFG_ATEN_MASK 0x00000100L
+#define SWRST_CONTROL_2__PORT1_CFG_ATEN_MASK 0x00000200L
+#define SWRST_CONTROL_2__PORT2_CFG_ATEN_MASK 0x00000400L
+#define SWRST_CONTROL_2__PORT3_CFG_ATEN_MASK 0x00000800L
+#define SWRST_CONTROL_2__PORT4_CFG_ATEN_MASK 0x00001000L
+#define SWRST_CONTROL_2__PORT5_CFG_ATEN_MASK 0x00002000L
+#define SWRST_CONTROL_2__PORT6_CFG_ATEN_MASK 0x00004000L
+#define SWRST_CONTROL_2__PORT7_CFG_ATEN_MASK 0x00008000L
+#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK 0x01000000L
+#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK 0x02000000L
+#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK 0x04000000L
+#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK 0x08000000L
+#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK 0x10000000L
+#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK 0x20000000L
+#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK 0x40000000L
+#define SWRST_CONTROL_2__BIF0_SDP_CREDIT_RESETATEN_MASK 0x80000000L
+//SWRST_CONTROL_3
+#define SWRST_CONTROL_3__PCSRESET0_ATEN__SHIFT 0x0
+#define SWRST_CONTROL_3__PCSRESET1_ATEN__SHIFT 0x1
+#define SWRST_CONTROL_3__PCSRESET2_ATEN__SHIFT 0x2
+#define SWRST_CONTROL_3__PCSRESET3_ATEN__SHIFT 0x3
+#define SWRST_CONTROL_3__PCSRESET4_ATEN__SHIFT 0x4
+#define SWRST_CONTROL_3__PCSRESET5_ATEN__SHIFT 0x5
+#define SWRST_CONTROL_3__PCSRESET6_ATEN__SHIFT 0x6
+#define SWRST_CONTROL_3__PCSRESET7_ATEN__SHIFT 0x7
+#define SWRST_CONTROL_3__PCSRESET8_ATEN__SHIFT 0x8
+#define SWRST_CONTROL_3__PCSRESET9_ATEN__SHIFT 0x9
+#define SWRST_CONTROL_3__PCSRESET10_ATEN__SHIFT 0xa
+#define SWRST_CONTROL_3__PCSRESET11_ATEN__SHIFT 0xb
+#define SWRST_CONTROL_3__PCSRESET12_ATEN__SHIFT 0xc
+#define SWRST_CONTROL_3__PCSRESET13_ATEN__SHIFT 0xd
+#define SWRST_CONTROL_3__PCSRESET14_ATEN__SHIFT 0xe
+#define SWRST_CONTROL_3__PCSRESET15_ATEN__SHIFT 0xf
+#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT 0x15
+#define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT 0x19
+#define SWRST_CONTROL_3__RESETLNCT_ATEN__SHIFT 0x1a
+#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT 0x1b
+#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT 0x1c
+#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT 0x1d
+#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT 0x1e
+#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT 0x1f
+#define SWRST_CONTROL_3__PCSRESET0_ATEN_MASK 0x00000001L
+#define SWRST_CONTROL_3__PCSRESET1_ATEN_MASK 0x00000002L
+#define SWRST_CONTROL_3__PCSRESET2_ATEN_MASK 0x00000004L
+#define SWRST_CONTROL_3__PCSRESET3_ATEN_MASK 0x00000008L
+#define SWRST_CONTROL_3__PCSRESET4_ATEN_MASK 0x00000010L
+#define SWRST_CONTROL_3__PCSRESET5_ATEN_MASK 0x00000020L
+#define SWRST_CONTROL_3__PCSRESET6_ATEN_MASK 0x00000040L
+#define SWRST_CONTROL_3__PCSRESET7_ATEN_MASK 0x00000080L
+#define SWRST_CONTROL_3__PCSRESET8_ATEN_MASK 0x00000100L
+#define SWRST_CONTROL_3__PCSRESET9_ATEN_MASK 0x00000200L
+#define SWRST_CONTROL_3__PCSRESET10_ATEN_MASK 0x00000400L
+#define SWRST_CONTROL_3__PCSRESET11_ATEN_MASK 0x00000800L
+#define SWRST_CONTROL_3__PCSRESET12_ATEN_MASK 0x00001000L
+#define SWRST_CONTROL_3__PCSRESET13_ATEN_MASK 0x00002000L
+#define SWRST_CONTROL_3__PCSRESET14_ATEN_MASK 0x00004000L
+#define SWRST_CONTROL_3__PCSRESET15_ATEN_MASK 0x00008000L
+#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK 0x00200000L
+#define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK 0x02000000L
+#define SWRST_CONTROL_3__RESETLNCT_ATEN_MASK 0x04000000L
+#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK 0x08000000L
+#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK 0x10000000L
+#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK 0x20000000L
+#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK 0x40000000L
+#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK 0x80000000L
+//SWRST_CONTROL_4
+#define SWRST_CONTROL_4__PORT0_COR_WREN__SHIFT 0x0
+#define SWRST_CONTROL_4__PORT0_CFG_WREN__SHIFT 0x8
+#define SWRST_CONTROL_4__PORT1_CFG_WREN__SHIFT 0x9
+#define SWRST_CONTROL_4__PORT2_CFG_WREN__SHIFT 0xa
+#define SWRST_CONTROL_4__PORT3_CFG_WREN__SHIFT 0xb
+#define SWRST_CONTROL_4__PORT4_CFG_WREN__SHIFT 0xc
+#define SWRST_CONTROL_4__PORT5_CFG_WREN__SHIFT 0xd
+#define SWRST_CONTROL_4__PORT6_CFG_WREN__SHIFT 0xe
+#define SWRST_CONTROL_4__PORT7_CFG_WREN__SHIFT 0xf
+#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT 0x18
+#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT 0x19
+#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT 0x1a
+#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT 0x1b
+#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT 0x1c
+#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT 0x1d
+#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT 0x1e
+#define SWRST_CONTROL_4__BIF0_SDP_CREDIT_WRRESETEN__SHIFT 0x1f
+#define SWRST_CONTROL_4__PORT0_COR_WREN_MASK 0x00000001L
+#define SWRST_CONTROL_4__PORT0_CFG_WREN_MASK 0x00000100L
+#define SWRST_CONTROL_4__PORT1_CFG_WREN_MASK 0x00000200L
+#define SWRST_CONTROL_4__PORT2_CFG_WREN_MASK 0x00000400L
+#define SWRST_CONTROL_4__PORT3_CFG_WREN_MASK 0x00000800L
+#define SWRST_CONTROL_4__PORT4_CFG_WREN_MASK 0x00001000L
+#define SWRST_CONTROL_4__PORT5_CFG_WREN_MASK 0x00002000L
+#define SWRST_CONTROL_4__PORT6_CFG_WREN_MASK 0x00004000L
+#define SWRST_CONTROL_4__PORT7_CFG_WREN_MASK 0x00008000L
+#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK 0x01000000L
+#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK 0x02000000L
+#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK 0x04000000L
+#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK 0x08000000L
+#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK 0x10000000L
+#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK 0x20000000L
+#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK 0x40000000L
+#define SWRST_CONTROL_4__BIF0_SDP_CREDIT_WRRESETEN_MASK 0x80000000L
+//SWRST_CONTROL_5
+#define SWRST_CONTROL_5__PCSRESET0_WREN__SHIFT 0x0
+#define SWRST_CONTROL_5__PCSRESET1_WREN__SHIFT 0x1
+#define SWRST_CONTROL_5__PCSRESET2_WREN__SHIFT 0x2
+#define SWRST_CONTROL_5__PCSRESET3_WREN__SHIFT 0x3
+#define SWRST_CONTROL_5__PCSRESET4_WREN__SHIFT 0x4
+#define SWRST_CONTROL_5__PCSRESET5_WREN__SHIFT 0x5
+#define SWRST_CONTROL_5__PCSRESET6_WREN__SHIFT 0x6
+#define SWRST_CONTROL_5__PCSRESET7_WREN__SHIFT 0x7
+#define SWRST_CONTROL_5__PCSRESET8_WREN__SHIFT 0x8
+#define SWRST_CONTROL_5__PCSRESET9_WREN__SHIFT 0x9
+#define SWRST_CONTROL_5__PCSRESET10_WREN__SHIFT 0xa
+#define SWRST_CONTROL_5__PCSRESET11_WREN__SHIFT 0xb
+#define SWRST_CONTROL_5__PCSRESET12_WREN__SHIFT 0xc
+#define SWRST_CONTROL_5__PCSRESET13_WREN__SHIFT 0xd
+#define SWRST_CONTROL_5__PCSRESET14_WREN__SHIFT 0xe
+#define SWRST_CONTROL_5__PCSRESET15_WREN__SHIFT 0xf
+#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT 0x15
+#define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT 0x19
+#define SWRST_CONTROL_5__WRRESETLNCT_EN__SHIFT 0x1a
+#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT 0x1b
+#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT 0x1c
+#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT 0x1d
+#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT 0x1e
+#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT 0x1f
+#define SWRST_CONTROL_5__PCSRESET0_WREN_MASK 0x00000001L
+#define SWRST_CONTROL_5__PCSRESET1_WREN_MASK 0x00000002L
+#define SWRST_CONTROL_5__PCSRESET2_WREN_MASK 0x00000004L
+#define SWRST_CONTROL_5__PCSRESET3_WREN_MASK 0x00000008L
+#define SWRST_CONTROL_5__PCSRESET4_WREN_MASK 0x00000010L
+#define SWRST_CONTROL_5__PCSRESET5_WREN_MASK 0x00000020L
+#define SWRST_CONTROL_5__PCSRESET6_WREN_MASK 0x00000040L
+#define SWRST_CONTROL_5__PCSRESET7_WREN_MASK 0x00000080L
+#define SWRST_CONTROL_5__PCSRESET8_WREN_MASK 0x00000100L
+#define SWRST_CONTROL_5__PCSRESET9_WREN_MASK 0x00000200L
+#define SWRST_CONTROL_5__PCSRESET10_WREN_MASK 0x00000400L
+#define SWRST_CONTROL_5__PCSRESET11_WREN_MASK 0x00000800L
+#define SWRST_CONTROL_5__PCSRESET12_WREN_MASK 0x00001000L
+#define SWRST_CONTROL_5__PCSRESET13_WREN_MASK 0x00002000L
+#define SWRST_CONTROL_5__PCSRESET14_WREN_MASK 0x00004000L
+#define SWRST_CONTROL_5__PCSRESET15_WREN_MASK 0x00008000L
+#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK 0x00200000L
+#define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK 0x02000000L
+#define SWRST_CONTROL_5__WRRESETLNCT_EN_MASK 0x04000000L
+#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK 0x08000000L
+#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK 0x10000000L
+#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK 0x20000000L
+#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK 0x40000000L
+#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK 0x80000000L
+//SWRST_CONTROL_6
+#define SWRST_CONTROL_6__HOLD_TRAINING_A__SHIFT 0x0
+#define SWRST_CONTROL_6__HOLD_TRAINING_B__SHIFT 0x1
+#define SWRST_CONTROL_6__HOLD_TRAINING_C__SHIFT 0x2
+#define SWRST_CONTROL_6__HOLD_TRAINING_D__SHIFT 0x3
+#define SWRST_CONTROL_6__HOLD_TRAINING_E__SHIFT 0x4
+#define SWRST_CONTROL_6__HOLD_TRAINING_F__SHIFT 0x5
+#define SWRST_CONTROL_6__HOLD_TRAINING_G__SHIFT 0x6
+#define SWRST_CONTROL_6__HOLD_TRAINING_H__SHIFT 0x7
+#define SWRST_CONTROL_6__HOLD_TRAINING_I__SHIFT 0x8
+#define SWRST_CONTROL_6__HOLD_TRAINING_J__SHIFT 0x9
+#define SWRST_CONTROL_6__HOLD_TRAINING_K__SHIFT 0xa
+#define SWRST_CONTROL_6__HOLD_TRAINING_A_MASK 0x00000001L
+#define SWRST_CONTROL_6__HOLD_TRAINING_B_MASK 0x00000002L
+#define SWRST_CONTROL_6__HOLD_TRAINING_C_MASK 0x00000004L
+#define SWRST_CONTROL_6__HOLD_TRAINING_D_MASK 0x00000008L
+#define SWRST_CONTROL_6__HOLD_TRAINING_E_MASK 0x00000010L
+#define SWRST_CONTROL_6__HOLD_TRAINING_F_MASK 0x00000020L
+#define SWRST_CONTROL_6__HOLD_TRAINING_G_MASK 0x00000040L
+#define SWRST_CONTROL_6__HOLD_TRAINING_H_MASK 0x00000080L
+#define SWRST_CONTROL_6__HOLD_TRAINING_I_MASK 0x00000100L
+#define SWRST_CONTROL_6__HOLD_TRAINING_J_MASK 0x00000200L
+#define SWRST_CONTROL_6__HOLD_TRAINING_K_MASK 0x00000400L
+//SWRST_EP_COMMAND_0
+#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT 0x0
+#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT 0x8
+#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT 0x9
+#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT 0xa
+#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK 0x00000001L
+#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK 0x00000100L
+#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK 0x00000200L
+#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK 0x00000400L
+//SWRST_EP_CONTROL_0
+#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT 0x0
+#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT 0x8
+#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT 0x9
+#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT 0xa
+#define SWRST_EP_CONTROL_0__EP_PORT_IGNORE_CHIP_MODE__SHIFT 0x16
+#define SWRST_EP_CONTROL_0__EP_PORT_CONTROL__SHIFT 0x17
+#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK 0x00000001L
+#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK 0x00000100L
+#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK 0x00000200L
+#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK 0x00000400L
+#define SWRST_EP_CONTROL_0__EP_PORT_IGNORE_CHIP_MODE_MASK 0x00400000L
+#define SWRST_EP_CONTROL_0__EP_PORT_CONTROL_MASK 0xFF800000L
+//CPM_CONTROL
+#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT 0x0
+#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT 0x1
+#define CPM_CONTROL__L1_PWR_GATE_ENABLE__SHIFT 0x2
+#define CPM_CONTROL__L1_1_PWR_GATE_ENABLE__SHIFT 0x3
+#define CPM_CONTROL__L1_2_PWR_GATE_ENABLE__SHIFT 0x4
+#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT 0x5
+#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT 0x6
+#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT 0x7
+#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT 0x8
+#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT 0x9
+#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT 0xb
+#define CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE__SHIFT 0xd
+#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT 0xe
+#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT 0xf
+#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT 0x10
+#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT 0x11
+#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT 0x12
+#define CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG__SHIFT 0x15
+#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT 0x16
+#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT 0x17
+#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE__SHIFT 0x18
+#define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1__SHIFT 0x19
+#define CPM_CONTROL__PG_EARLY_WAKE_ENABLE__SHIFT 0x1a
+#define CPM_CONTROL__PCIE_CORE_IDLE__SHIFT 0x1b
+#define CPM_CONTROL__PCIE_LINK_IDLE__SHIFT 0x1c
+#define CPM_CONTROL__PCIE_BUFFER_EMPTY__SHIFT 0x1d
+#define CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY__SHIFT 0x1e
+#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK 0x00000001L
+#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK 0x00000002L
+#define CPM_CONTROL__L1_PWR_GATE_ENABLE_MASK 0x00000004L
+#define CPM_CONTROL__L1_1_PWR_GATE_ENABLE_MASK 0x00000008L
+#define CPM_CONTROL__L1_2_PWR_GATE_ENABLE_MASK 0x00000010L
+#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK 0x00000020L
+#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK 0x00000040L
+#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK 0x00000080L
+#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK 0x00000100L
+#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK 0x00000600L
+#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK 0x00001800L
+#define CPM_CONTROL__REFCLKREQ_REFCLKACK_LOOPBACK_ENABLE_MASK 0x00002000L
+#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK 0x00004000L
+#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK 0x00008000L
+#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK 0x00010000L
+#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK 0x00020000L
+#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK 0x001C0000L
+#define CPM_CONTROL__IGNORE_REGS_IDLE_IN_PG_MASK 0x00200000L
+#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK 0x00400000L
+#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK 0x00800000L
+#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK 0x01000000L
+#define CPM_CONTROL__LCLK_GATE_ALLOW_IN_L1_MASK 0x02000000L
+#define CPM_CONTROL__PG_EARLY_WAKE_ENABLE_MASK 0x04000000L
+#define CPM_CONTROL__PCIE_CORE_IDLE_MASK 0x08000000L
+#define CPM_CONTROL__PCIE_LINK_IDLE_MASK 0x10000000L
+#define CPM_CONTROL__PCIE_BUFFER_EMPTY_MASK 0x20000000L
+#define CPM_CONTROL__REGS_IDLE_TO_PG_LATENCY_MASK 0xC0000000L
+//CPM_SPLIT_CONTROL
+#define CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE__SHIFT 0x0
+#define CPM_SPLIT_CONTROL__TXCLK_CCIX_DYN_GATE_ENABLE_MASK 0x00000001L
+//CPM_CONTROL_EXT
+#define CPM_CONTROL_EXT__PWRDOWN_EI_MASK_DISABLE__SHIFT 0x0
+#define CPM_CONTROL_EXT__DELAY_HOLD_TRAINING_ENABLE__SHIFT 0x1
+#define CPM_CONTROL_EXT__LCLK_DS_MODE__SHIFT 0x2
+#define CPM_CONTROL_EXT__LCLK_DS_ENABLE__SHIFT 0x3
+#define CPM_CONTROL_EXT__PG_STATE__SHIFT 0x4
+#define CPM_CONTROL_EXT__PWRDOWN_EI_MASK_DISABLE_MASK 0x00000001L
+#define CPM_CONTROL_EXT__DELAY_HOLD_TRAINING_ENABLE_MASK 0x00000002L
+#define CPM_CONTROL_EXT__LCLK_DS_MODE_MASK 0x00000004L
+#define CPM_CONTROL_EXT__LCLK_DS_ENABLE_MASK 0x00000008L
+#define CPM_CONTROL_EXT__PG_STATE_MASK 0x00000070L
+//SMN_APERTURE_ID_A
+#define SMN_APERTURE_ID_A__PCS_APERTURE_ID__SHIFT 0xc
+#define SMN_APERTURE_ID_A__PCS_APERTURE_ID_MASK 0x00FFF000L
+//SMN_APERTURE_ID_B
+#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID__SHIFT 0x0
+#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID__SHIFT 0xc
+#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID_MASK 0x00000FFFL
+#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID_MASK 0x00FFF000L
+//LNCNT_CONTROL
+#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN__SHIFT 0x0
+#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN__SHIFT 0x1
+#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN__SHIFT 0x2
+#define LNCNT_CONTROL__CFG_LNC_OVRD_EN__SHIFT 0x3
+#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL__SHIFT 0x4
+#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN_MASK 0x00000001L
+#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN_MASK 0x00000002L
+#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN_MASK 0x00000004L
+#define LNCNT_CONTROL__CFG_LNC_OVRD_EN_MASK 0x00000008L
+#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL_MASK 0x00000010L
+//LNCNT_QUAN_THRD
+#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD__SHIFT 0x0
+#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD__SHIFT 0x4
+#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD_MASK 0x00000007L
+#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD_MASK 0x00000070L
+//LNCNT_WEIGHT
+#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT__SHIFT 0x0
+#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT__SHIFT 0x10
+#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT_MASK 0x0000FFFFL
+#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT_MASK 0xFFFF0000L
+//PCIE_PGMST_CNTL
+#define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS__SHIFT 0x0
+#define PCIE_PGMST_CNTL__CFG_PG_EN__SHIFT 0x8
+#define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL__SHIFT 0xe
+#define PCIE_PGMST_CNTL__PG_EXIT_TIMER__SHIFT 0x10
+#define PCIE_PGMST_CNTL__CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define PCIE_PGMST_CNTL__CFG_PG_EN_MASK 0x00000100L
+#define PCIE_PGMST_CNTL__CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define PCIE_PGMST_CNTL__CFG_FW_PG_EXIT_CNTL_MASK 0x0000C000L
+#define PCIE_PGMST_CNTL__PG_EXIT_TIMER_MASK 0x00FF0000L
+//PCIE_PGSLV_CNTL
+#define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS__SHIFT 0x0
+#define PCIE_PGSLV_CNTL__CFG_IDLE_HYSTERESIS_MASK 0x0000001FL
+//LC_CPM_CONTROL_0
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE__SHIFT 0x0
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE__SHIFT 0x1
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE__SHIFT 0x2
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE__SHIFT 0x3
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE__SHIFT 0x4
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE__SHIFT 0x5
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE__SHIFT 0x6
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE__SHIFT 0x7
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE__SHIFT 0x8
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE__SHIFT 0x9
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE__SHIFT 0xa
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE__SHIFT 0xb
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE__SHIFT 0xc
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE__SHIFT 0xd
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE__SHIFT 0xe
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE__SHIFT 0xf
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE__SHIFT 0x10
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE__SHIFT 0x11
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE__SHIFT 0x12
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE__SHIFT 0x13
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE__SHIFT 0x14
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE__SHIFT 0x15
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE__SHIFT 0x16
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE__SHIFT 0x17
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE__SHIFT 0x18
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE__SHIFT 0x19
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE__SHIFT 0x1a
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE__SHIFT 0x1b
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE__SHIFT 0x1c
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE__SHIFT 0x1d
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE__SHIFT 0x1e
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE__SHIFT 0x1f
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_A_GATE_ENABLE_MASK 0x00000001L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_B_GATE_ENABLE_MASK 0x00000002L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_C_GATE_ENABLE_MASK 0x00000004L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_D_GATE_ENABLE_MASK 0x00000008L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_E_GATE_ENABLE_MASK 0x00000010L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_F_GATE_ENABLE_MASK 0x00000020L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_G_GATE_ENABLE_MASK 0x00000040L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_H_GATE_ENABLE_MASK 0x00000080L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_I_GATE_ENABLE_MASK 0x00000100L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_J_GATE_ENABLE_MASK 0x00000200L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_K_GATE_ENABLE_MASK 0x00000400L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_L_GATE_ENABLE_MASK 0x00000800L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_M_GATE_ENABLE_MASK 0x00001000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_N_GATE_ENABLE_MASK 0x00002000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_O_GATE_ENABLE_MASK 0x00004000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_PORT_P_GATE_ENABLE_MASK 0x00008000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_A_GATE_ENABLE_MASK 0x00010000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_B_GATE_ENABLE_MASK 0x00020000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_C_GATE_ENABLE_MASK 0x00040000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_D_GATE_ENABLE_MASK 0x00080000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_E_GATE_ENABLE_MASK 0x00100000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_F_GATE_ENABLE_MASK 0x00200000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_G_GATE_ENABLE_MASK 0x00400000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_H_GATE_ENABLE_MASK 0x00800000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_I_GATE_ENABLE_MASK 0x01000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_J_GATE_ENABLE_MASK 0x02000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_K_GATE_ENABLE_MASK 0x04000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_L_GATE_ENABLE_MASK 0x08000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_M_GATE_ENABLE_MASK 0x10000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_N_GATE_ENABLE_MASK 0x20000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_O_GATE_ENABLE_MASK 0x40000000L
+#define LC_CPM_CONTROL_0__TXCLK_DYN_TR_PORT_P_GATE_ENABLE_MASK 0x80000000L
+//LC_CPM_CONTROL_1
+#define LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY__SHIFT 0x0
+#define LC_CPM_CONTROL_1__TXCLK_PI_CLK_EN_ALL_LANES_GATE_ENABLE__SHIFT 0xf
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE__SHIFT 0x10
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE__SHIFT 0x11
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE__SHIFT 0x12
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE__SHIFT 0x13
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE__SHIFT 0x14
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE__SHIFT 0x15
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE__SHIFT 0x16
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE__SHIFT 0x17
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE__SHIFT 0x18
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE__SHIFT 0x19
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE__SHIFT 0x1a
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE__SHIFT 0x1b
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE__SHIFT 0x1c
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE__SHIFT 0x1d
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE__SHIFT 0x1e
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE__SHIFT 0x1f
+#define LC_CPM_CONTROL_1__TXCLK_DYN_PORT_GATE_LATENCY_MASK 0x00000007L
+#define LC_CPM_CONTROL_1__TXCLK_PI_CLK_EN_ALL_LANES_GATE_ENABLE_MASK 0x00008000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_A_GATE_ENABLE_MASK 0x00010000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_B_GATE_ENABLE_MASK 0x00020000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_C_GATE_ENABLE_MASK 0x00040000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_D_GATE_ENABLE_MASK 0x00080000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_E_GATE_ENABLE_MASK 0x00100000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_F_GATE_ENABLE_MASK 0x00200000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_G_GATE_ENABLE_MASK 0x00400000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_H_GATE_ENABLE_MASK 0x00800000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_I_GATE_ENABLE_MASK 0x01000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_J_GATE_ENABLE_MASK 0x02000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_K_GATE_ENABLE_MASK 0x04000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_L_GATE_ENABLE_MASK 0x08000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_M_GATE_ENABLE_MASK 0x10000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_N_GATE_ENABLE_MASK 0x20000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_O_GATE_ENABLE_MASK 0x40000000L
+#define LC_CPM_CONTROL_1__TXCLK_RXP_CLK_EN_PORT_P_GATE_ENABLE_MASK 0x80000000L
+//PCIE_RXMARGIN_CONTROL_CAPABILITIES
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED__SHIFT 0x0
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE__SHIFT 0x1
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING__SHIFT 0x2
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD__SHIFT 0x3
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER__SHIFT 0x4
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_VOLTAGESUPPORTED_MASK 0x00000001L
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDUPDOWNVOLTAGE_MASK 0x00000002L
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDLEFTRIGHTTIMING_MASK 0x00000004L
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_SAMPLEREPORTINGMETHOD_MASK 0x00000008L
+#define PCIE_RXMARGIN_CONTROL_CAPABILITIES__M_INDERRORSAMPLER_MASK 0x00000010L
+//PCIE_RXMARGIN_1_SETTINGS
+#define PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS__SHIFT 0x0
+#define PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS__SHIFT 0x7
+#define PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET__SHIFT 0xd
+#define PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET__SHIFT 0x14
+#define PCIE_RXMARGIN_1_SETTINGS__M_NUMVOLTAGESTEPS_MASK 0x0000007FL
+#define PCIE_RXMARGIN_1_SETTINGS__M_NUMTIMINGSTEPS_MASK 0x00001F80L
+#define PCIE_RXMARGIN_1_SETTINGS__M_MAXTIMINGOFFSET_MASK 0x000FE000L
+#define PCIE_RXMARGIN_1_SETTINGS__M_MAXVOLTAGEOFFSET_MASK 0x07F00000L
+//PCIE_RXMARGIN_2_SETTINGS
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE__SHIFT 0x0
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING__SHIFT 0x6
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT__SHIFT 0xc
+#define PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES__SHIFT 0x13
+#define PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT__SHIFT 0x18
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATEVOLTAGE_MASK 0x0000003FL
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLINGRATETIMING_MASK 0x00000FC0L
+#define PCIE_RXMARGIN_2_SETTINGS__M_SAMPLECOUNT_MASK 0x0007F000L
+#define PCIE_RXMARGIN_2_SETTINGS__M_MAXLANES_MASK 0x00F80000L
+#define PCIE_RXMARGIN_2_SETTINGS__M_ERROR_COUNT_LIMIT_MASK 0x3F000000L
+//PCIE_PRESENCE_DETECT_SELECT
+#define PCIE_PRESENCE_DETECT_SELECT__HPGI_BLOCK_DL_ACTIVE_INT__SHIFT 0x0
+#define PCIE_PRESENCE_DETECT_SELECT__HPGI_DL_ACTIVE_STATE_PRIVATE__SHIFT 0x8
+#define PCIE_PRESENCE_DETECT_SELECT__DL_ACTIVE_INT_STATUS__SHIFT 0x10
+#define PCIE_PRESENCE_DETECT_SELECT__PRESENCE_DETECT_SELECT__SHIFT 0x18
+#define PCIE_PRESENCE_DETECT_SELECT__HPGI_BLOCK_DL_ACTIVE_INT_MASK 0x000000FFL
+#define PCIE_PRESENCE_DETECT_SELECT__HPGI_DL_ACTIVE_STATE_PRIVATE_MASK 0x0000FF00L
+#define PCIE_PRESENCE_DETECT_SELECT__DL_ACTIVE_INT_STATUS_MASK 0x00FF0000L
+#define PCIE_PRESENCE_DETECT_SELECT__PRESENCE_DETECT_SELECT_MASK 0x01000000L
+
+
+// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
+
+
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow0_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow1_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow2_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow3_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow4_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow5_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_PCIE0shadow6_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_fastreg_fastreg_cfgdec
+//FASTREG_APERTURE
+#define FASTREG_APERTURE__FASTREG_APERTURE_ID__SHIFT 0x0
+#define FASTREG_APERTURE__FASTREG_NODE_ID__SHIFT 0x10
+#define FASTREG_APERTURE__FASTREG_TRAN_POSTED__SHIFT 0x1f
+#define FASTREG_APERTURE__FASTREG_APERTURE_ID_MASK 0x00000FFFL
+#define FASTREG_APERTURE__FASTREG_NODE_ID_MASK 0x000F0000L
+#define FASTREG_APERTURE__FASTREG_TRAN_POSTED_MASK 0x80000000L
+
+
+// addressBlock: nbio_iohub_nb_NBIF1shadow0_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_NBIF1shadow1_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_NBIF1shadow2_pcieshadow_cfgdecp
+
+
+// addressBlock: nbio_iohub_nb_misc_misc_cfgdec
+//NBIO_LCLK_DS_MASK
+#define NBIO_LCLK_DS_MASK__LCLK_DS_MASK__SHIFT 0x0
+#define NBIO_LCLK_DS_MASK__LCLK_DS_MASK_MASK 0xFFFFFFFFL
+//SB_LOCATION
+#define SB_LOCATION__SBlocated_Port__SHIFT 0x0
+#define SB_LOCATION__SBlocated_Core__SHIFT 0x10
+#define SB_LOCATION__SBlocated_Port_MASK 0x0000FFFFL
+#define SB_LOCATION__SBlocated_Core_MASK 0xFFFF0000L
+//SW_US_LOCATION
+#define SW_US_LOCATION__SW_USlocated_Port__SHIFT 0x0
+#define SW_US_LOCATION__SW_USlocated_Core__SHIFT 0x10
+#define SW_US_LOCATION__SW_USlocated_Port_MASK 0x0000FFFFL
+#define SW_US_LOCATION__SW_USlocated_Core_MASK 0xFFFF0000L
+//SW_NMI_CNTL
+#define SW_NMI_CNTL__SW_NMI_Status__SHIFT 0x0
+#define SW_NMI_CNTL__SW_NMI_Status_MASK 0xFFFFFFFFL
+//SW_SMI_CNTL
+#define SW_SMI_CNTL__SW_SMI_Status__SHIFT 0x0
+#define SW_SMI_CNTL__SW_SMI_Status_MASK 0xFFFFFFFFL
+//SW_SCI_CNTL
+#define SW_SCI_CNTL__SW_SCI_Status__SHIFT 0x0
+#define SW_SCI_CNTL__SW_SCI_Status_MASK 0xFFFFFFFFL
+//APML_SW_STATUS
+#define APML_SW_STATUS__APML_NMI_STATUS__SHIFT 0x0
+#define APML_SW_STATUS__APML_NMI_STATUS_MASK 0x00000001L
+//SW_GIC_SPI_CNTL
+#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector__SHIFT 0x0
+#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector__SHIFT 0x8
+#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector__SHIFT 0x10
+#define SW_GIC_SPI_CNTL__SW_NMI_GIC_SPI_Vector_MASK 0x000000FFL
+#define SW_GIC_SPI_CNTL__SW_SMI_GIC_SPI_Vector_MASK 0x0000FF00L
+#define SW_GIC_SPI_CNTL__SW_SCI_GIC_SPI_Vector_MASK 0x00FF0000L
+//SW_SYNCFLOOD_CNTL
+#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE__SHIFT 0x0
+#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML__SHIFT 0x1
+#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_PRIVATE_MASK 0x00000001L
+#define SW_SYNCFLOOD_CNTL__SW_SYNCFLOOD_APML_MASK 0x00000002L
+//CAM_CONTROL
+#define CAM_CONTROL__CAM_En__SHIFT 0x0
+#define CAM_CONTROL__Op__SHIFT 0x1
+#define CAM_CONTROL__AccessType__SHIFT 0x2
+#define CAM_CONTROL__DataMatchEn__SHIFT 0x3
+#define CAM_CONTROL__VC__SHIFT 0x4
+#define CAM_CONTROL__CrossTrigger__SHIFT 0x8
+#define CAM_CONTROL__CAM_En_MASK 0x00000001L
+#define CAM_CONTROL__Op_MASK 0x00000002L
+#define CAM_CONTROL__AccessType_MASK 0x00000004L
+#define CAM_CONTROL__DataMatchEn_MASK 0x00000008L
+#define CAM_CONTROL__VC_MASK 0x00000070L
+#define CAM_CONTROL__CrossTrigger_MASK 0x00000F00L
+//CAM_TARGET_INDEX_ADDR_BOTTOM
+#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom__SHIFT 0x0
+#define CAM_TARGET_INDEX_ADDR_BOTTOM__IndexAddrBottom_MASK 0xFFFFFFFFL
+//CAM_TARGET_INDEX_ADDR_TOP
+#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop__SHIFT 0x0
+#define CAM_TARGET_INDEX_ADDR_TOP__IndexAddrTop_MASK 0xFFFFFFFFL
+//CAM_TARGET_INDEX_DATA
+#define CAM_TARGET_INDEX_DATA__IndexData__SHIFT 0x0
+#define CAM_TARGET_INDEX_DATA__IndexData_MASK 0xFFFFFFFFL
+//CAM_TARGET_INDEX_DATA_MASK
+#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask__SHIFT 0x0
+#define CAM_TARGET_INDEX_DATA_MASK__IndexDataMask_MASK 0xFFFFFFFFL
+//CAM_TARGET_DATA_ADDR_BOTTOM
+#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom__SHIFT 0x0
+#define CAM_TARGET_DATA_ADDR_BOTTOM__DataAddrBottom_MASK 0xFFFFFFFFL
+//CAM_TARGET_DATA_ADDR_TOP
+#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop__SHIFT 0x0
+#define CAM_TARGET_DATA_ADDR_TOP__DataAddrTop_MASK 0xFFFFFFFFL
+//CAM_TARGET_DATA
+#define CAM_TARGET_DATA__Data__SHIFT 0x0
+#define CAM_TARGET_DATA__Data_MASK 0xFFFFFFFFL
+//CAM_TARGET_DATA_MASK
+#define CAM_TARGET_DATA_MASK__DataMask__SHIFT 0x0
+#define CAM_TARGET_DATA_MASK__DataMask_MASK 0xFFFFFFFFL
+//P_DMA_DROPPED_LOG_LOWER
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0__SHIFT 0x0
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1__SHIFT 0x1
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2__SHIFT 0x2
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3__SHIFT 0x3
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4__SHIFT 0x4
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5__SHIFT 0x5
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6__SHIFT 0x6
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7__SHIFT 0x7
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8__SHIFT 0x8
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9__SHIFT 0x9
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10__SHIFT 0xa
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11__SHIFT 0xb
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12__SHIFT 0xc
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13__SHIFT 0xd
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14__SHIFT 0xe
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15__SHIFT 0xf
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16__SHIFT 0x10
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17__SHIFT 0x11
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18__SHIFT 0x12
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19__SHIFT 0x13
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20__SHIFT 0x14
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21__SHIFT 0x15
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22__SHIFT 0x16
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23__SHIFT 0x17
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24__SHIFT 0x18
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25__SHIFT 0x19
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26__SHIFT 0x1a
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27__SHIFT 0x1b
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28__SHIFT 0x1c
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29__SHIFT 0x1d
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30__SHIFT 0x1e
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31__SHIFT 0x1f
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_0_MASK 0x00000001L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_1_MASK 0x00000002L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_2_MASK 0x00000004L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_3_MASK 0x00000008L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_4_MASK 0x00000010L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_5_MASK 0x00000020L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_6_MASK 0x00000040L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_7_MASK 0x00000080L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_8_MASK 0x00000100L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_9_MASK 0x00000200L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_10_MASK 0x00000400L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_11_MASK 0x00000800L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_12_MASK 0x00001000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_13_MASK 0x00002000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_14_MASK 0x00004000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_15_MASK 0x00008000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_16_MASK 0x00010000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_17_MASK 0x00020000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_18_MASK 0x00040000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_19_MASK 0x00080000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_20_MASK 0x00100000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_21_MASK 0x00200000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_22_MASK 0x00400000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_23_MASK 0x00800000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_24_MASK 0x01000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_25_MASK 0x02000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_26_MASK 0x04000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_27_MASK 0x08000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_28_MASK 0x10000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_29_MASK 0x20000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_30_MASK 0x40000000L
+#define P_DMA_DROPPED_LOG_LOWER__P_DMA_DROPPED_LOG_LOWER_31_MASK 0x80000000L
+//P_DMA_DROPPED_LOG_UPPER
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0__SHIFT 0x0
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1__SHIFT 0x1
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2__SHIFT 0x2
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3__SHIFT 0x3
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4__SHIFT 0x4
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5__SHIFT 0x5
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6__SHIFT 0x6
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7__SHIFT 0x7
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8__SHIFT 0x8
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9__SHIFT 0x9
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10__SHIFT 0xa
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11__SHIFT 0xb
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12__SHIFT 0xc
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13__SHIFT 0xd
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14__SHIFT 0xe
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15__SHIFT 0xf
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16__SHIFT 0x10
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17__SHIFT 0x11
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18__SHIFT 0x12
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19__SHIFT 0x13
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20__SHIFT 0x14
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21__SHIFT 0x15
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22__SHIFT 0x16
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23__SHIFT 0x17
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24__SHIFT 0x18
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25__SHIFT 0x19
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26__SHIFT 0x1a
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27__SHIFT 0x1b
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28__SHIFT 0x1c
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29__SHIFT 0x1d
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30__SHIFT 0x1e
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31__SHIFT 0x1f
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_0_MASK 0x00000001L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_1_MASK 0x00000002L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_2_MASK 0x00000004L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_3_MASK 0x00000008L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_4_MASK 0x00000010L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_5_MASK 0x00000020L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_6_MASK 0x00000040L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_7_MASK 0x00000080L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_8_MASK 0x00000100L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_9_MASK 0x00000200L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_10_MASK 0x00000400L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_11_MASK 0x00000800L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_12_MASK 0x00001000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_13_MASK 0x00002000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_14_MASK 0x00004000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_15_MASK 0x00008000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_16_MASK 0x00010000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_17_MASK 0x00020000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_18_MASK 0x00040000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_19_MASK 0x00080000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_20_MASK 0x00100000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_21_MASK 0x00200000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_22_MASK 0x00400000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_23_MASK 0x00800000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_24_MASK 0x01000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_25_MASK 0x02000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_26_MASK 0x04000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_27_MASK 0x08000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_28_MASK 0x10000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_29_MASK 0x20000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_30_MASK 0x40000000L
+#define P_DMA_DROPPED_LOG_UPPER__P_DMA_DROPPED_LOG_UPPER_31_MASK 0x80000000L
+//NP_DMA_DROPPED_LOG_LOWER
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0__SHIFT 0x0
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1__SHIFT 0x1
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2__SHIFT 0x2
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3__SHIFT 0x3
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4__SHIFT 0x4
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5__SHIFT 0x5
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6__SHIFT 0x6
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7__SHIFT 0x7
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8__SHIFT 0x8
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9__SHIFT 0x9
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10__SHIFT 0xa
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11__SHIFT 0xb
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12__SHIFT 0xc
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13__SHIFT 0xd
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14__SHIFT 0xe
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15__SHIFT 0xf
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16__SHIFT 0x10
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17__SHIFT 0x11
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18__SHIFT 0x12
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19__SHIFT 0x13
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20__SHIFT 0x14
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21__SHIFT 0x15
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22__SHIFT 0x16
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23__SHIFT 0x17
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24__SHIFT 0x18
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25__SHIFT 0x19
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26__SHIFT 0x1a
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27__SHIFT 0x1b
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28__SHIFT 0x1c
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29__SHIFT 0x1d
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30__SHIFT 0x1e
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31__SHIFT 0x1f
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_0_MASK 0x00000001L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_1_MASK 0x00000002L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_2_MASK 0x00000004L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_3_MASK 0x00000008L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_4_MASK 0x00000010L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_5_MASK 0x00000020L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_6_MASK 0x00000040L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_7_MASK 0x00000080L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_8_MASK 0x00000100L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_9_MASK 0x00000200L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_10_MASK 0x00000400L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_11_MASK 0x00000800L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_12_MASK 0x00001000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_13_MASK 0x00002000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_14_MASK 0x00004000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_15_MASK 0x00008000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_16_MASK 0x00010000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_17_MASK 0x00020000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_18_MASK 0x00040000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_19_MASK 0x00080000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_20_MASK 0x00100000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_21_MASK 0x00200000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_22_MASK 0x00400000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_23_MASK 0x00800000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_24_MASK 0x01000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_25_MASK 0x02000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_26_MASK 0x04000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_27_MASK 0x08000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_28_MASK 0x10000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_29_MASK 0x20000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_30_MASK 0x40000000L
+#define NP_DMA_DROPPED_LOG_LOWER__NP_DMA_DROPPED_LOG_LOWER_31_MASK 0x80000000L
+//NP_DMA_DROPPED_LOG_UPPER
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0__SHIFT 0x0
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1__SHIFT 0x1
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2__SHIFT 0x2
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3__SHIFT 0x3
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4__SHIFT 0x4
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5__SHIFT 0x5
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6__SHIFT 0x6
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7__SHIFT 0x7
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8__SHIFT 0x8
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9__SHIFT 0x9
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10__SHIFT 0xa
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11__SHIFT 0xb
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12__SHIFT 0xc
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13__SHIFT 0xd
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14__SHIFT 0xe
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15__SHIFT 0xf
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16__SHIFT 0x10
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17__SHIFT 0x11
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18__SHIFT 0x12
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19__SHIFT 0x13
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20__SHIFT 0x14
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21__SHIFT 0x15
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22__SHIFT 0x16
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23__SHIFT 0x17
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24__SHIFT 0x18
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25__SHIFT 0x19
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26__SHIFT 0x1a
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27__SHIFT 0x1b
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28__SHIFT 0x1c
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29__SHIFT 0x1d
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30__SHIFT 0x1e
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31__SHIFT 0x1f
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_0_MASK 0x00000001L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_1_MASK 0x00000002L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_2_MASK 0x00000004L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_3_MASK 0x00000008L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_4_MASK 0x00000010L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_5_MASK 0x00000020L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_6_MASK 0x00000040L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_7_MASK 0x00000080L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_8_MASK 0x00000100L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_9_MASK 0x00000200L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_10_MASK 0x00000400L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_11_MASK 0x00000800L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_12_MASK 0x00001000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_13_MASK 0x00002000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_14_MASK 0x00004000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_15_MASK 0x00008000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_16_MASK 0x00010000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_17_MASK 0x00020000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_18_MASK 0x00040000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_19_MASK 0x00080000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_20_MASK 0x00100000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_21_MASK 0x00200000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_22_MASK 0x00400000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_23_MASK 0x00800000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_24_MASK 0x01000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_25_MASK 0x02000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_26_MASK 0x04000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_27_MASK 0x08000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_28_MASK 0x10000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_29_MASK 0x20000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_30_MASK 0x40000000L
+#define NP_DMA_DROPPED_LOG_UPPER__NP_DMA_DROPPED_LOG_UPPER_31_MASK 0x80000000L
+//PCIE_VDM_NODE0_CTRL4
+#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE__SHIFT 0x0
+#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT__SHIFT 0x8
+#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT__SHIFT 0x1f
+#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_BASE_MASK 0x000000FFL
+#define PCIE_VDM_NODE0_CTRL4__BUS_RANGE_LIMIT_MASK 0x0000FF00L
+#define PCIE_VDM_NODE0_CTRL4__NODE0_PRESENT_MASK 0x80000000L
+//PCIE_VDM_CNTL2
+#define PCIE_VDM_CNTL2__VdmP2pMode__SHIFT 0x0
+#define PCIE_VDM_CNTL2__MCTPMasterValid__SHIFT 0xf
+#define PCIE_VDM_CNTL2__MCTPMasterID__SHIFT 0x10
+#define PCIE_VDM_CNTL2__VdmP2pMode_MASK 0x00000003L
+#define PCIE_VDM_CNTL2__MCTPMasterValid_MASK 0x00008000L
+#define PCIE_VDM_CNTL2__MCTPMasterID_MASK 0xFFFF0000L
+//PCIE_VDM_CNTL3
+#define PCIE_VDM_CNTL3__APMTPMasterValid__SHIFT 0xf
+#define PCIE_VDM_CNTL3__APMTPMasterID__SHIFT 0x10
+#define PCIE_VDM_CNTL3__APMTPMasterValid_MASK 0x00008000L
+#define PCIE_VDM_CNTL3__APMTPMasterID_MASK 0xFFFF0000L
+//STALL_CONTROL_XBARPORT0_0
+#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT0_0__StallVC0ReqEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT0_0__StallVC1ReqEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT0_0__StallVC2ReqEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT0_0__StallVC3ReqEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT0_0__StallVC4ReqEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT0_0__StallVC5ReqEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT0_0__StallVC7ReqEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT0_1
+#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT0_1__StallVC5RspEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT0_1__StallVC0RspEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT0_1__StallVC1RspEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT0_1__StallVC2RspEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT0_1__StallVC3RspEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT0_1__StallVC4RspEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT0_1__StallVC5RspEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT0_1__StallVC7RspEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT1_0
+#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT1_0__StallVC0ReqEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT1_0__StallVC1ReqEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT1_0__StallVC2ReqEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT1_0__StallVC3ReqEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT1_0__StallVC4ReqEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT1_0__StallVC5ReqEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT1_0__StallVC7ReqEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT1_1
+#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT1_1__StallVC5RspEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT1_1__StallVC0RspEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT1_1__StallVC1RspEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT1_1__StallVC2RspEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT1_1__StallVC3RspEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT1_1__StallVC4RspEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT1_1__StallVC5RspEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT1_1__StallVC7RspEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT2_0
+#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT2_0__StallVC0ReqEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT2_0__StallVC1ReqEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT2_0__StallVC2ReqEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT2_0__StallVC3ReqEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT2_0__StallVC4ReqEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT2_0__StallVC5ReqEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT2_0__StallVC7ReqEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT2_1
+#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT2_1__StallVC5RspEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT2_1__StallVC0RspEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT2_1__StallVC1RspEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT2_1__StallVC2RspEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT2_1__StallVC3RspEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT2_1__StallVC4RspEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT2_1__StallVC5RspEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT2_1__StallVC7RspEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT3_0
+#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT3_0__StallVC0ReqEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT3_0__StallVC1ReqEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT3_0__StallVC2ReqEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT3_0__StallVC3ReqEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT3_0__StallVC4ReqEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT3_0__StallVC5ReqEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT3_0__StallVC7ReqEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT3_1
+#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT3_1__StallVC5RspEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT3_1__StallVC0RspEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT3_1__StallVC1RspEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT3_1__StallVC2RspEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT3_1__StallVC3RspEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT3_1__StallVC4RspEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT3_1__StallVC5RspEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT3_1__StallVC7RspEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT4_0
+#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT4_0__StallVC0ReqEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT4_0__StallVC1ReqEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT4_0__StallVC2ReqEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT4_0__StallVC3ReqEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT4_0__StallVC4ReqEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT4_0__StallVC5ReqEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT4_0__StallVC7ReqEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT4_1
+#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT4_1__StallVC5RspEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT4_1__StallVC0RspEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT4_1__StallVC1RspEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT4_1__StallVC2RspEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT4_1__StallVC3RspEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT4_1__StallVC4RspEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT4_1__StallVC5RspEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT4_1__StallVC7RspEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT5_0
+#define STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT5_0__StallVC0ReqEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT5_0__StallVC1ReqEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT5_0__StallVC2ReqEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT5_0__StallVC3ReqEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT5_0__StallVC4ReqEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT5_0__StallVC5ReqEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT5_0__StallVC7ReqEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT5_1
+#define STALL_CONTROL_XBARPORT5_1__StallVC0RspEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT5_1__StallVC1RspEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT5_1__StallVC2RspEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT5_1__StallVC3RspEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT5_1__StallVC4RspEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT5_1__StallVC5RspEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT5_1__StallVC7RspEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT5_1__StallVC0RspEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT5_1__StallVC1RspEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT5_1__StallVC2RspEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT5_1__StallVC3RspEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT5_1__StallVC4RspEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT5_1__StallVC5RspEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT5_1__StallVC7RspEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT6_0
+#define STALL_CONTROL_XBARPORT6_0__StallVC0ReqEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT6_0__StallVC1ReqEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT6_0__StallVC2ReqEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT6_0__StallVC3ReqEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT6_0__StallVC4ReqEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT6_0__StallVC5ReqEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT6_0__StallVC7ReqEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT6_0__StallVC0ReqEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT6_0__StallVC1ReqEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT6_0__StallVC2ReqEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT6_0__StallVC3ReqEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT6_0__StallVC4ReqEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT6_0__StallVC5ReqEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT6_0__StallVC7ReqEn_MASK 0x30000000L
+//STALL_CONTROL_XBARPORT6_1
+#define STALL_CONTROL_XBARPORT6_1__StallVC0RspEn__SHIFT 0x0
+#define STALL_CONTROL_XBARPORT6_1__StallVC1RspEn__SHIFT 0x4
+#define STALL_CONTROL_XBARPORT6_1__StallVC2RspEn__SHIFT 0x8
+#define STALL_CONTROL_XBARPORT6_1__StallVC3RspEn__SHIFT 0xc
+#define STALL_CONTROL_XBARPORT6_1__StallVC4RspEn__SHIFT 0x10
+#define STALL_CONTROL_XBARPORT6_1__StallVC5RspEn__SHIFT 0x14
+#define STALL_CONTROL_XBARPORT6_1__StallVC7RspEn__SHIFT 0x1c
+#define STALL_CONTROL_XBARPORT6_1__StallVC0RspEn_MASK 0x00000003L
+#define STALL_CONTROL_XBARPORT6_1__StallVC1RspEn_MASK 0x00000030L
+#define STALL_CONTROL_XBARPORT6_1__StallVC2RspEn_MASK 0x00000300L
+#define STALL_CONTROL_XBARPORT6_1__StallVC3RspEn_MASK 0x00003000L
+#define STALL_CONTROL_XBARPORT6_1__StallVC4RspEn_MASK 0x00030000L
+#define STALL_CONTROL_XBARPORT6_1__StallVC5RspEn_MASK 0x00300000L
+#define STALL_CONTROL_XBARPORT6_1__StallVC7RspEn_MASK 0x30000000L
+//FASTREG_BASE_ADDR_LO
+#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN__SHIFT 0x0
+#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK__SHIFT 0x1
+#define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO__SHIFT 0x14
+#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_EN_MASK 0x00000001L
+#define FASTREG_BASE_ADDR_LO__FASTREG_MMIO_LOCK_MASK 0x00000002L
+#define FASTREG_BASE_ADDR_LO__FASTREG_BASE_ADDR_LO_MASK 0xFFF00000L
+//FASTREG_BASE_ADDR_HI
+#define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI__SHIFT 0x0
+#define FASTREG_BASE_ADDR_HI__FASTREG_BASE_ADDR_HI_MASK 0x0000FFFFL
+//FASTREGCNTL_BASE_ADDR_LO
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN__SHIFT 0x0
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK__SHIFT 0x1
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO__SHIFT 0xc
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_EN_MASK 0x00000001L
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_MMIO_LOCK_MASK 0x00000002L
+#define FASTREGCNTL_BASE_ADDR_LO__FASTREGCNTL_BASE_ADDR_LO_MASK 0xFFFFF000L
+//FASTREGCNTL_BASE_ADDR_HI
+#define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI__SHIFT 0x0
+#define FASTREGCNTL_BASE_ADDR_HI__FASTREGCNTL_BASE_ADDR_HI_MASK 0x0000FFFFL
+//SCRATCH_4
+#define SCRATCH_4__SCRATCH_4__SHIFT 0x0
+#define SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL
+//SCRATCH_5
+#define SCRATCH_5__SCRATCH_5__SHIFT 0x0
+#define SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL
+//TRAP_STATUS
+#define TRAP_STATUS__TrapReqValid__SHIFT 0x0
+#define TRAP_STATUS__TrapNumber__SHIFT 0x8
+#define TRAP_STATUS__TrapReqValid_MASK 0x00000001L
+#define TRAP_STATUS__TrapNumber_MASK 0x00000F00L
+//TRAP_REQUEST0
+#define TRAP_REQUEST0__TrapReqAddrLo__SHIFT 0x2
+#define TRAP_REQUEST0__TrapReqAddrLo_MASK 0xFFFFFFFCL
+//TRAP_REQUEST1
+#define TRAP_REQUEST1__TrapReqAddrHi__SHIFT 0x0
+#define TRAP_REQUEST1__TrapReqAddrHi_MASK 0xFFFFFFFFL
+//TRAP_REQUEST2
+#define TRAP_REQUEST2__TrapReqCmd__SHIFT 0x0
+#define TRAP_REQUEST2__TrapAttr__SHIFT 0x8
+#define TRAP_REQUEST2__TrapReqLen__SHIFT 0x10
+#define TRAP_REQUEST2__TrapReqCmd_MASK 0x0000003FL
+#define TRAP_REQUEST2__TrapAttr_MASK 0x0000FF00L
+#define TRAP_REQUEST2__TrapReqLen_MASK 0x003F0000L
+//TRAP_REQUEST3
+#define TRAP_REQUEST3__TrapReqVC__SHIFT 0x0
+#define TRAP_REQUEST3__TrapReqBlockLevel__SHIFT 0x4
+#define TRAP_REQUEST3__TrapReqChain__SHIFT 0x6
+#define TRAP_REQUEST3__TrapReqIO__SHIFT 0x7
+#define TRAP_REQUEST3__TrapReqPassPW__SHIFT 0x8
+#define TRAP_REQUEST3__TrapReqRspPassPW__SHIFT 0x9
+#define TRAP_REQUEST3__TrapReqUnitID__SHIFT 0x10
+#define TRAP_REQUEST3__TrapReqVC_MASK 0x00000007L
+#define TRAP_REQUEST3__TrapReqBlockLevel_MASK 0x00000030L
+#define TRAP_REQUEST3__TrapReqChain_MASK 0x00000040L
+#define TRAP_REQUEST3__TrapReqIO_MASK 0x00000080L
+#define TRAP_REQUEST3__TrapReqPassPW_MASK 0x00000100L
+#define TRAP_REQUEST3__TrapReqRspPassPW_MASK 0x00000200L
+#define TRAP_REQUEST3__TrapReqUnitID_MASK 0x003F0000L
+//TRAP_REQUEST4
+#define TRAP_REQUEST4__TrapReqSecLevel__SHIFT 0x0
+#define TRAP_REQUEST4__TrapReqSecLevel_MASK 0x0000000FL
+//TRAP_REQUEST5
+#define TRAP_REQUEST5__TrapReqDataVC__SHIFT 0x0
+#define TRAP_REQUEST5__TrapReqDataErr__SHIFT 0x4
+#define TRAP_REQUEST5__TrapReqDataParity__SHIFT 0x8
+#define TRAP_REQUEST5__TrapReqDataVC_MASK 0x00000007L
+#define TRAP_REQUEST5__TrapReqDataErr_MASK 0x00000010L
+#define TRAP_REQUEST5__TrapReqDataParity_MASK 0x0000FF00L
+//TRAP_REQUEST_DATASTRB0
+#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0__SHIFT 0x0
+#define TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATASTRB1
+#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1__SHIFT 0x0
+#define TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA0
+#define TRAP_REQUEST_DATA0__TrapReqData0__SHIFT 0x0
+#define TRAP_REQUEST_DATA0__TrapReqData0_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA1
+#define TRAP_REQUEST_DATA1__TrapReqData1__SHIFT 0x0
+#define TRAP_REQUEST_DATA1__TrapReqData1_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA2
+#define TRAP_REQUEST_DATA2__TrapReqData2__SHIFT 0x0
+#define TRAP_REQUEST_DATA2__TrapReqData2_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA3
+#define TRAP_REQUEST_DATA3__TrapReqData3__SHIFT 0x0
+#define TRAP_REQUEST_DATA3__TrapReqData3_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA4
+#define TRAP_REQUEST_DATA4__TrapReqData4__SHIFT 0x0
+#define TRAP_REQUEST_DATA4__TrapReqData4_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA5
+#define TRAP_REQUEST_DATA5__TrapReqData5__SHIFT 0x0
+#define TRAP_REQUEST_DATA5__TrapReqData5_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA6
+#define TRAP_REQUEST_DATA6__TrapReqData6__SHIFT 0x0
+#define TRAP_REQUEST_DATA6__TrapReqData6_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA7
+#define TRAP_REQUEST_DATA7__TrapReqData7__SHIFT 0x0
+#define TRAP_REQUEST_DATA7__TrapReqData7_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA8
+#define TRAP_REQUEST_DATA8__TrapReqData8__SHIFT 0x0
+#define TRAP_REQUEST_DATA8__TrapReqData8_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA9
+#define TRAP_REQUEST_DATA9__TrapReqData9__SHIFT 0x0
+#define TRAP_REQUEST_DATA9__TrapReqData9_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA10
+#define TRAP_REQUEST_DATA10__TrapReqData10__SHIFT 0x0
+#define TRAP_REQUEST_DATA10__TrapReqData10_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA11
+#define TRAP_REQUEST_DATA11__TrapReqData11__SHIFT 0x0
+#define TRAP_REQUEST_DATA11__TrapReqData11_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA12
+#define TRAP_REQUEST_DATA12__TrapReqData12__SHIFT 0x0
+#define TRAP_REQUEST_DATA12__TrapReqData12_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA13
+#define TRAP_REQUEST_DATA13__TrapReqData13__SHIFT 0x0
+#define TRAP_REQUEST_DATA13__TrapReqData13_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA14
+#define TRAP_REQUEST_DATA14__TrapReqData14__SHIFT 0x0
+#define TRAP_REQUEST_DATA14__TrapReqData14_MASK 0xFFFFFFFFL
+//TRAP_REQUEST_DATA15
+#define TRAP_REQUEST_DATA15__TrapReqData15__SHIFT 0x0
+#define TRAP_REQUEST_DATA15__TrapReqData15_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_CONTROL
+#define TRAP_RESPONSE_CONTROL__TrapRspTrigger__SHIFT 0x0
+#define TRAP_RESPONSE_CONTROL__TrapRspReqPassthru__SHIFT 0x1
+#define TRAP_RESPONSE_CONTROL__TrapRspTrigger_MASK 0x00000001L
+#define TRAP_RESPONSE_CONTROL__TrapRspReqPassthru_MASK 0x00000002L
+//TRAP_RESPONSE0
+#define TRAP_RESPONSE0__TrapRspPassPW__SHIFT 0x0
+#define TRAP_RESPONSE0__TrapRspStatus__SHIFT 0x4
+#define TRAP_RESPONSE0__TrapRspDataStatus__SHIFT 0x10
+#define TRAP_RESPONSE0__TrapRspPassPW_MASK 0x00000001L
+#define TRAP_RESPONSE0__TrapRspStatus_MASK 0x000000F0L
+#define TRAP_RESPONSE0__TrapRspDataStatus_MASK 0x00FF0000L
+//TRAP_RESPONSE_DATA0
+#define TRAP_RESPONSE_DATA0__TrapRdRspData0__SHIFT 0x0
+#define TRAP_RESPONSE_DATA0__TrapRdRspData0_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA1
+#define TRAP_RESPONSE_DATA1__TrapRdRspData1__SHIFT 0x0
+#define TRAP_RESPONSE_DATA1__TrapRdRspData1_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA2
+#define TRAP_RESPONSE_DATA2__TrapRdRspData2__SHIFT 0x0
+#define TRAP_RESPONSE_DATA2__TrapRdRspData2_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA3
+#define TRAP_RESPONSE_DATA3__TrapRdRspData3__SHIFT 0x0
+#define TRAP_RESPONSE_DATA3__TrapRdRspData3_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA4
+#define TRAP_RESPONSE_DATA4__TrapRdRspData4__SHIFT 0x0
+#define TRAP_RESPONSE_DATA4__TrapRdRspData4_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA5
+#define TRAP_RESPONSE_DATA5__TrapRdRspData5__SHIFT 0x0
+#define TRAP_RESPONSE_DATA5__TrapRdRspData5_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA6
+#define TRAP_RESPONSE_DATA6__TrapRdRspData6__SHIFT 0x0
+#define TRAP_RESPONSE_DATA6__TrapRdRspData6_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA7
+#define TRAP_RESPONSE_DATA7__TrapRdRspData7__SHIFT 0x0
+#define TRAP_RESPONSE_DATA7__TrapRdRspData7_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA8
+#define TRAP_RESPONSE_DATA8__TrapRdRspData8__SHIFT 0x0
+#define TRAP_RESPONSE_DATA8__TrapRdRspData8_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA9
+#define TRAP_RESPONSE_DATA9__TrapRdRspData9__SHIFT 0x0
+#define TRAP_RESPONSE_DATA9__TrapRdRspData9_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA10
+#define TRAP_RESPONSE_DATA10__TrapRdRspData10__SHIFT 0x0
+#define TRAP_RESPONSE_DATA10__TrapRdRspData10_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA11
+#define TRAP_RESPONSE_DATA11__TrapRdRspData11__SHIFT 0x0
+#define TRAP_RESPONSE_DATA11__TrapRdRspData11_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA12
+#define TRAP_RESPONSE_DATA12__TrapRdRspData12__SHIFT 0x0
+#define TRAP_RESPONSE_DATA12__TrapRdRspData12_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA13
+#define TRAP_RESPONSE_DATA13__TrapRdRspData13__SHIFT 0x0
+#define TRAP_RESPONSE_DATA13__TrapRdRspData13_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA14
+#define TRAP_RESPONSE_DATA14__TrapRdRspData14__SHIFT 0x0
+#define TRAP_RESPONSE_DATA14__TrapRdRspData14_MASK 0xFFFFFFFFL
+//TRAP_RESPONSE_DATA15
+#define TRAP_RESPONSE_DATA15__TrapRdRspData15__SHIFT 0x0
+#define TRAP_RESPONSE_DATA15__TrapRdRspData15_MASK 0xFFFFFFFFL
+//TRAP0_CONTROL0
+#define TRAP0_CONTROL0__Trap0En__SHIFT 0x0
+#define TRAP0_CONTROL0__Trap0CrossTrigger__SHIFT 0x18
+#define TRAP0_CONTROL0__Trap0En_MASK 0x00000001L
+#define TRAP0_CONTROL0__Trap0CrossTrigger_MASK 0x0F000000L
+//TRAP0_ADDRESS_LO
+#define TRAP0_ADDRESS_LO__Trap0AddrLo__SHIFT 0x2
+#define TRAP0_ADDRESS_LO__Trap0AddrLo_MASK 0xFFFFFFFCL
+//TRAP0_ADDRESS_HI
+#define TRAP0_ADDRESS_HI__Trap0AddrHi__SHIFT 0x0
+#define TRAP0_ADDRESS_HI__Trap0AddrHi_MASK 0xFFFFFFFFL
+//TRAP0_COMMAND
+#define TRAP0_COMMAND__Trap0Cmd0__SHIFT 0x0
+#define TRAP0_COMMAND__Trap0Cmd1__SHIFT 0x8
+#define TRAP0_COMMAND__Trap0Cmd0_MASK 0x0000003FL
+#define TRAP0_COMMAND__Trap0Cmd1_MASK 0x00003F00L
+//TRAP0_ADDRESS_LO_MASK
+#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask__SHIFT 0x2
+#define TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP0_ADDRESS_HI_MASK
+#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask__SHIFT 0x0
+#define TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP0_COMMAND_MASK
+#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask__SHIFT 0x0
+#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask__SHIFT 0x8
+#define TRAP0_COMMAND_MASK__Trap0Cmd0Mask_MASK 0x0000003FL
+#define TRAP0_COMMAND_MASK__Trap0Cmd1Mask_MASK 0x00003F00L
+//TRAP1_CONTROL0
+#define TRAP1_CONTROL0__Trap1En__SHIFT 0x0
+#define TRAP1_CONTROL0__Trap1CrossTrigger__SHIFT 0x18
+#define TRAP1_CONTROL0__Trap1En_MASK 0x00000001L
+#define TRAP1_CONTROL0__Trap1CrossTrigger_MASK 0x0F000000L
+//TRAP1_ADDRESS_LO
+#define TRAP1_ADDRESS_LO__Trap1AddrLo__SHIFT 0x2
+#define TRAP1_ADDRESS_LO__Trap1AddrLo_MASK 0xFFFFFFFCL
+//TRAP1_ADDRESS_HI
+#define TRAP1_ADDRESS_HI__Trap1AddrHi__SHIFT 0x0
+#define TRAP1_ADDRESS_HI__Trap1AddrHi_MASK 0xFFFFFFFFL
+//TRAP1_COMMAND
+#define TRAP1_COMMAND__Trap1Cmd0__SHIFT 0x0
+#define TRAP1_COMMAND__Trap1Cmd1__SHIFT 0x8
+#define TRAP1_COMMAND__Trap1Cmd0_MASK 0x0000003FL
+#define TRAP1_COMMAND__Trap1Cmd1_MASK 0x00003F00L
+//TRAP1_ADDRESS_LO_MASK
+#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask__SHIFT 0x2
+#define TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP1_ADDRESS_HI_MASK
+#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask__SHIFT 0x0
+#define TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP1_COMMAND_MASK
+#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask__SHIFT 0x0
+#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask__SHIFT 0x8
+#define TRAP1_COMMAND_MASK__Trap1Cmd0Mask_MASK 0x0000003FL
+#define TRAP1_COMMAND_MASK__Trap1Cmd1Mask_MASK 0x00003F00L
+//TRAP2_CONTROL0
+#define TRAP2_CONTROL0__Trap2En__SHIFT 0x0
+#define TRAP2_CONTROL0__Trap2CrossTrigger__SHIFT 0x18
+#define TRAP2_CONTROL0__Trap2En_MASK 0x00000001L
+#define TRAP2_CONTROL0__Trap2CrossTrigger_MASK 0x0F000000L
+//TRAP2_ADDRESS_LO
+#define TRAP2_ADDRESS_LO__Trap2AddrLo__SHIFT 0x2
+#define TRAP2_ADDRESS_LO__Trap2AddrLo_MASK 0xFFFFFFFCL
+//TRAP2_ADDRESS_HI
+#define TRAP2_ADDRESS_HI__Trap2AddrHi__SHIFT 0x0
+#define TRAP2_ADDRESS_HI__Trap2AddrHi_MASK 0xFFFFFFFFL
+//TRAP2_COMMAND
+#define TRAP2_COMMAND__Trap2Cmd0__SHIFT 0x0
+#define TRAP2_COMMAND__Trap2Cmd1__SHIFT 0x8
+#define TRAP2_COMMAND__Trap2Cmd0_MASK 0x0000003FL
+#define TRAP2_COMMAND__Trap2Cmd1_MASK 0x00003F00L
+//TRAP2_ADDRESS_LO_MASK
+#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask__SHIFT 0x2
+#define TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP2_ADDRESS_HI_MASK
+#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask__SHIFT 0x0
+#define TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP2_COMMAND_MASK
+#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask__SHIFT 0x0
+#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask__SHIFT 0x8
+#define TRAP2_COMMAND_MASK__Trap2Cmd0Mask_MASK 0x0000003FL
+#define TRAP2_COMMAND_MASK__Trap2Cmd1Mask_MASK 0x00003F00L
+//TRAP3_CONTROL0
+#define TRAP3_CONTROL0__Trap3En__SHIFT 0x0
+#define TRAP3_CONTROL0__Trap3CrossTrigger__SHIFT 0x18
+#define TRAP3_CONTROL0__Trap3En_MASK 0x00000001L
+#define TRAP3_CONTROL0__Trap3CrossTrigger_MASK 0x0F000000L
+//TRAP3_ADDRESS_LO
+#define TRAP3_ADDRESS_LO__Trap3AddrLo__SHIFT 0x2
+#define TRAP3_ADDRESS_LO__Trap3AddrLo_MASK 0xFFFFFFFCL
+//TRAP3_ADDRESS_HI
+#define TRAP3_ADDRESS_HI__Trap3AddrHi__SHIFT 0x0
+#define TRAP3_ADDRESS_HI__Trap3AddrHi_MASK 0xFFFFFFFFL
+//TRAP3_COMMAND
+#define TRAP3_COMMAND__Trap3Cmd0__SHIFT 0x0
+#define TRAP3_COMMAND__Trap3Cmd1__SHIFT 0x8
+#define TRAP3_COMMAND__Trap3Cmd0_MASK 0x0000003FL
+#define TRAP3_COMMAND__Trap3Cmd1_MASK 0x00003F00L
+//TRAP3_ADDRESS_LO_MASK
+#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask__SHIFT 0x2
+#define TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP3_ADDRESS_HI_MASK
+#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask__SHIFT 0x0
+#define TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP3_COMMAND_MASK
+#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask__SHIFT 0x0
+#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask__SHIFT 0x8
+#define TRAP3_COMMAND_MASK__Trap3Cmd0Mask_MASK 0x0000003FL
+#define TRAP3_COMMAND_MASK__Trap3Cmd1Mask_MASK 0x00003F00L
+//TRAP4_CONTROL0
+#define TRAP4_CONTROL0__Trap4En__SHIFT 0x0
+#define TRAP4_CONTROL0__Trap4CrossTrigger__SHIFT 0x18
+#define TRAP4_CONTROL0__Trap4En_MASK 0x00000001L
+#define TRAP4_CONTROL0__Trap4CrossTrigger_MASK 0x0F000000L
+//TRAP4_ADDRESS_LO
+#define TRAP4_ADDRESS_LO__Trap4AddrLo__SHIFT 0x2
+#define TRAP4_ADDRESS_LO__Trap4AddrLo_MASK 0xFFFFFFFCL
+//TRAP4_ADDRESS_HI
+#define TRAP4_ADDRESS_HI__Trap4AddrHi__SHIFT 0x0
+#define TRAP4_ADDRESS_HI__Trap4AddrHi_MASK 0xFFFFFFFFL
+//TRAP4_COMMAND
+#define TRAP4_COMMAND__Trap4Cmd0__SHIFT 0x0
+#define TRAP4_COMMAND__Trap4Cmd1__SHIFT 0x8
+#define TRAP4_COMMAND__Trap4Cmd0_MASK 0x0000003FL
+#define TRAP4_COMMAND__Trap4Cmd1_MASK 0x00003F00L
+//TRAP4_ADDRESS_LO_MASK
+#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask__SHIFT 0x2
+#define TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP4_ADDRESS_HI_MASK
+#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask__SHIFT 0x0
+#define TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP4_COMMAND_MASK
+#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask__SHIFT 0x0
+#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask__SHIFT 0x8
+#define TRAP4_COMMAND_MASK__Trap4Cmd0Mask_MASK 0x0000003FL
+#define TRAP4_COMMAND_MASK__Trap4Cmd1Mask_MASK 0x00003F00L
+//TRAP5_CONTROL0
+#define TRAP5_CONTROL0__Trap5En__SHIFT 0x0
+#define TRAP5_CONTROL0__Trap5CrossTrigger__SHIFT 0x18
+#define TRAP5_CONTROL0__Trap5En_MASK 0x00000001L
+#define TRAP5_CONTROL0__Trap5CrossTrigger_MASK 0x0F000000L
+//TRAP5_ADDRESS_LO
+#define TRAP5_ADDRESS_LO__Trap5AddrLo__SHIFT 0x2
+#define TRAP5_ADDRESS_LO__Trap5AddrLo_MASK 0xFFFFFFFCL
+//TRAP5_ADDRESS_HI
+#define TRAP5_ADDRESS_HI__Trap5AddrHi__SHIFT 0x0
+#define TRAP5_ADDRESS_HI__Trap5AddrHi_MASK 0xFFFFFFFFL
+//TRAP5_COMMAND
+#define TRAP5_COMMAND__Trap5Cmd0__SHIFT 0x0
+#define TRAP5_COMMAND__Trap5Cmd1__SHIFT 0x8
+#define TRAP5_COMMAND__Trap5Cmd0_MASK 0x0000003FL
+#define TRAP5_COMMAND__Trap5Cmd1_MASK 0x00003F00L
+//TRAP5_ADDRESS_LO_MASK
+#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask__SHIFT 0x2
+#define TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP5_ADDRESS_HI_MASK
+#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask__SHIFT 0x0
+#define TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP5_COMMAND_MASK
+#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask__SHIFT 0x0
+#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask__SHIFT 0x8
+#define TRAP5_COMMAND_MASK__Trap5Cmd0Mask_MASK 0x0000003FL
+#define TRAP5_COMMAND_MASK__Trap5Cmd1Mask_MASK 0x00003F00L
+//TRAP6_CONTROL0
+#define TRAP6_CONTROL0__Trap6En__SHIFT 0x0
+#define TRAP6_CONTROL0__Trap6CrossTrigger__SHIFT 0x18
+#define TRAP6_CONTROL0__Trap6En_MASK 0x00000001L
+#define TRAP6_CONTROL0__Trap6CrossTrigger_MASK 0x0F000000L
+//TRAP6_ADDRESS_LO
+#define TRAP6_ADDRESS_LO__Trap6AddrLo__SHIFT 0x2
+#define TRAP6_ADDRESS_LO__Trap6AddrLo_MASK 0xFFFFFFFCL
+//TRAP6_ADDRESS_HI
+#define TRAP6_ADDRESS_HI__Trap6AddrHi__SHIFT 0x0
+#define TRAP6_ADDRESS_HI__Trap6AddrHi_MASK 0xFFFFFFFFL
+//TRAP6_COMMAND
+#define TRAP6_COMMAND__Trap6Cmd0__SHIFT 0x0
+#define TRAP6_COMMAND__Trap6Cmd1__SHIFT 0x8
+#define TRAP6_COMMAND__Trap6Cmd0_MASK 0x0000003FL
+#define TRAP6_COMMAND__Trap6Cmd1_MASK 0x00003F00L
+//TRAP6_ADDRESS_LO_MASK
+#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask__SHIFT 0x2
+#define TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP6_ADDRESS_HI_MASK
+#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask__SHIFT 0x0
+#define TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP6_COMMAND_MASK
+#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask__SHIFT 0x0
+#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask__SHIFT 0x8
+#define TRAP6_COMMAND_MASK__Trap6Cmd0Mask_MASK 0x0000003FL
+#define TRAP6_COMMAND_MASK__Trap6Cmd1Mask_MASK 0x00003F00L
+//TRAP7_CONTROL0
+#define TRAP7_CONTROL0__Trap7En__SHIFT 0x0
+#define TRAP7_CONTROL0__Trap7CrossTrigger__SHIFT 0x18
+#define TRAP7_CONTROL0__Trap7En_MASK 0x00000001L
+#define TRAP7_CONTROL0__Trap7CrossTrigger_MASK 0x0F000000L
+//TRAP7_ADDRESS_LO
+#define TRAP7_ADDRESS_LO__Trap7AddrLo__SHIFT 0x2
+#define TRAP7_ADDRESS_LO__Trap7AddrLo_MASK 0xFFFFFFFCL
+//TRAP7_ADDRESS_HI
+#define TRAP7_ADDRESS_HI__Trap7AddrHi__SHIFT 0x0
+#define TRAP7_ADDRESS_HI__Trap7AddrHi_MASK 0xFFFFFFFFL
+//TRAP7_COMMAND
+#define TRAP7_COMMAND__Trap7Cmd0__SHIFT 0x0
+#define TRAP7_COMMAND__Trap7Cmd1__SHIFT 0x8
+#define TRAP7_COMMAND__Trap7Cmd0_MASK 0x0000003FL
+#define TRAP7_COMMAND__Trap7Cmd1_MASK 0x00003F00L
+//TRAP7_ADDRESS_LO_MASK
+#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask__SHIFT 0x2
+#define TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP7_ADDRESS_HI_MASK
+#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask__SHIFT 0x0
+#define TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP7_COMMAND_MASK
+#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask__SHIFT 0x0
+#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask__SHIFT 0x8
+#define TRAP7_COMMAND_MASK__Trap7Cmd0Mask_MASK 0x0000003FL
+#define TRAP7_COMMAND_MASK__Trap7Cmd1Mask_MASK 0x00003F00L
+//TRAP8_CONTROL0
+#define TRAP8_CONTROL0__Trap8En__SHIFT 0x0
+#define TRAP8_CONTROL0__Trap8CrossTrigger__SHIFT 0x18
+#define TRAP8_CONTROL0__Trap8En_MASK 0x00000001L
+#define TRAP8_CONTROL0__Trap8CrossTrigger_MASK 0x0F000000L
+//TRAP8_ADDRESS_LO
+#define TRAP8_ADDRESS_LO__Trap8AddrLo__SHIFT 0x2
+#define TRAP8_ADDRESS_LO__Trap8AddrLo_MASK 0xFFFFFFFCL
+//TRAP8_ADDRESS_HI
+#define TRAP8_ADDRESS_HI__Trap8AddrHi__SHIFT 0x0
+#define TRAP8_ADDRESS_HI__Trap8AddrHi_MASK 0xFFFFFFFFL
+//TRAP8_COMMAND
+#define TRAP8_COMMAND__Trap8Cmd0__SHIFT 0x0
+#define TRAP8_COMMAND__Trap8Cmd1__SHIFT 0x8
+#define TRAP8_COMMAND__Trap8Cmd0_MASK 0x0000003FL
+#define TRAP8_COMMAND__Trap8Cmd1_MASK 0x00003F00L
+//TRAP8_ADDRESS_LO_MASK
+#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask__SHIFT 0x2
+#define TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP8_ADDRESS_HI_MASK
+#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask__SHIFT 0x0
+#define TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP8_COMMAND_MASK
+#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask__SHIFT 0x0
+#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask__SHIFT 0x8
+#define TRAP8_COMMAND_MASK__Trap8Cmd0Mask_MASK 0x0000003FL
+#define TRAP8_COMMAND_MASK__Trap8Cmd1Mask_MASK 0x00003F00L
+//TRAP9_CONTROL0
+#define TRAP9_CONTROL0__Trap9En__SHIFT 0x0
+#define TRAP9_CONTROL0__Trap9CrossTrigger__SHIFT 0x18
+#define TRAP9_CONTROL0__Trap9En_MASK 0x00000001L
+#define TRAP9_CONTROL0__Trap9CrossTrigger_MASK 0x0F000000L
+//TRAP9_ADDRESS_LO
+#define TRAP9_ADDRESS_LO__Trap9AddrLo__SHIFT 0x2
+#define TRAP9_ADDRESS_LO__Trap9AddrLo_MASK 0xFFFFFFFCL
+//TRAP9_ADDRESS_HI
+#define TRAP9_ADDRESS_HI__Trap9AddrHi__SHIFT 0x0
+#define TRAP9_ADDRESS_HI__Trap9AddrHi_MASK 0xFFFFFFFFL
+//TRAP9_COMMAND
+#define TRAP9_COMMAND__Trap9Cmd0__SHIFT 0x0
+#define TRAP9_COMMAND__Trap9Cmd1__SHIFT 0x8
+#define TRAP9_COMMAND__Trap9Cmd0_MASK 0x0000003FL
+#define TRAP9_COMMAND__Trap9Cmd1_MASK 0x00003F00L
+//TRAP9_ADDRESS_LO_MASK
+#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask__SHIFT 0x2
+#define TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP9_ADDRESS_HI_MASK
+#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask__SHIFT 0x0
+#define TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP9_COMMAND_MASK
+#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask__SHIFT 0x0
+#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask__SHIFT 0x8
+#define TRAP9_COMMAND_MASK__Trap9Cmd0Mask_MASK 0x0000003FL
+#define TRAP9_COMMAND_MASK__Trap9Cmd1Mask_MASK 0x00003F00L
+//TRAP10_CONTROL0
+#define TRAP10_CONTROL0__Trap10En__SHIFT 0x0
+#define TRAP10_CONTROL0__Trap10CrossTrigger__SHIFT 0x18
+#define TRAP10_CONTROL0__Trap10En_MASK 0x00000001L
+#define TRAP10_CONTROL0__Trap10CrossTrigger_MASK 0x0F000000L
+//TRAP10_ADDRESS_LO
+#define TRAP10_ADDRESS_LO__Trap10AddrLo__SHIFT 0x2
+#define TRAP10_ADDRESS_LO__Trap10AddrLo_MASK 0xFFFFFFFCL
+//TRAP10_ADDRESS_HI
+#define TRAP10_ADDRESS_HI__Trap10AddrHi__SHIFT 0x0
+#define TRAP10_ADDRESS_HI__Trap10AddrHi_MASK 0xFFFFFFFFL
+//TRAP10_COMMAND
+#define TRAP10_COMMAND__Trap10Cmd0__SHIFT 0x0
+#define TRAP10_COMMAND__Trap10Cmd1__SHIFT 0x8
+#define TRAP10_COMMAND__Trap10Cmd0_MASK 0x0000003FL
+#define TRAP10_COMMAND__Trap10Cmd1_MASK 0x00003F00L
+//TRAP10_ADDRESS_LO_MASK
+#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask__SHIFT 0x2
+#define TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP10_ADDRESS_HI_MASK
+#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask__SHIFT 0x0
+#define TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP10_COMMAND_MASK
+#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask__SHIFT 0x0
+#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask__SHIFT 0x8
+#define TRAP10_COMMAND_MASK__Trap10Cmd0Mask_MASK 0x0000003FL
+#define TRAP10_COMMAND_MASK__Trap10Cmd1Mask_MASK 0x00003F00L
+//TRAP11_CONTROL0
+#define TRAP11_CONTROL0__Trap11En__SHIFT 0x0
+#define TRAP11_CONTROL0__Trap11CrossTrigger__SHIFT 0x18
+#define TRAP11_CONTROL0__Trap11En_MASK 0x00000001L
+#define TRAP11_CONTROL0__Trap11CrossTrigger_MASK 0x0F000000L
+//TRAP11_ADDRESS_LO
+#define TRAP11_ADDRESS_LO__Trap11AddrLo__SHIFT 0x2
+#define TRAP11_ADDRESS_LO__Trap11AddrLo_MASK 0xFFFFFFFCL
+//TRAP11_ADDRESS_HI
+#define TRAP11_ADDRESS_HI__Trap11AddrHi__SHIFT 0x0
+#define TRAP11_ADDRESS_HI__Trap11AddrHi_MASK 0xFFFFFFFFL
+//TRAP11_COMMAND
+#define TRAP11_COMMAND__Trap11Cmd0__SHIFT 0x0
+#define TRAP11_COMMAND__Trap11Cmd1__SHIFT 0x8
+#define TRAP11_COMMAND__Trap11Cmd0_MASK 0x0000003FL
+#define TRAP11_COMMAND__Trap11Cmd1_MASK 0x00003F00L
+//TRAP11_ADDRESS_LO_MASK
+#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask__SHIFT 0x2
+#define TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP11_ADDRESS_HI_MASK
+#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask__SHIFT 0x0
+#define TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP11_COMMAND_MASK
+#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask__SHIFT 0x0
+#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask__SHIFT 0x8
+#define TRAP11_COMMAND_MASK__Trap11Cmd0Mask_MASK 0x0000003FL
+#define TRAP11_COMMAND_MASK__Trap11Cmd1Mask_MASK 0x00003F00L
+//TRAP12_CONTROL0
+#define TRAP12_CONTROL0__Trap12En__SHIFT 0x0
+#define TRAP12_CONTROL0__Trap12CrossTrigger__SHIFT 0x18
+#define TRAP12_CONTROL0__Trap12En_MASK 0x00000001L
+#define TRAP12_CONTROL0__Trap12CrossTrigger_MASK 0x0F000000L
+//TRAP12_ADDRESS_LO
+#define TRAP12_ADDRESS_LO__Trap12AddrLo__SHIFT 0x2
+#define TRAP12_ADDRESS_LO__Trap12AddrLo_MASK 0xFFFFFFFCL
+//TRAP12_ADDRESS_HI
+#define TRAP12_ADDRESS_HI__Trap12AddrHi__SHIFT 0x0
+#define TRAP12_ADDRESS_HI__Trap12AddrHi_MASK 0xFFFFFFFFL
+//TRAP12_COMMAND
+#define TRAP12_COMMAND__Trap12Cmd0__SHIFT 0x0
+#define TRAP12_COMMAND__Trap12Cmd1__SHIFT 0x8
+#define TRAP12_COMMAND__Trap12Cmd0_MASK 0x0000003FL
+#define TRAP12_COMMAND__Trap12Cmd1_MASK 0x00003F00L
+//TRAP12_ADDRESS_LO_MASK
+#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask__SHIFT 0x2
+#define TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP12_ADDRESS_HI_MASK
+#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask__SHIFT 0x0
+#define TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP12_COMMAND_MASK
+#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask__SHIFT 0x0
+#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask__SHIFT 0x8
+#define TRAP12_COMMAND_MASK__Trap12Cmd0Mask_MASK 0x0000003FL
+#define TRAP12_COMMAND_MASK__Trap12Cmd1Mask_MASK 0x00003F00L
+//TRAP13_CONTROL0
+#define TRAP13_CONTROL0__Trap13En__SHIFT 0x0
+#define TRAP13_CONTROL0__Trap13CrossTrigger__SHIFT 0x18
+#define TRAP13_CONTROL0__Trap13En_MASK 0x00000001L
+#define TRAP13_CONTROL0__Trap13CrossTrigger_MASK 0x0F000000L
+//TRAP13_ADDRESS_LO
+#define TRAP13_ADDRESS_LO__Trap13AddrLo__SHIFT 0x2
+#define TRAP13_ADDRESS_LO__Trap13AddrLo_MASK 0xFFFFFFFCL
+//TRAP13_ADDRESS_HI
+#define TRAP13_ADDRESS_HI__Trap13AddrHi__SHIFT 0x0
+#define TRAP13_ADDRESS_HI__Trap13AddrHi_MASK 0xFFFFFFFFL
+//TRAP13_COMMAND
+#define TRAP13_COMMAND__Trap13Cmd0__SHIFT 0x0
+#define TRAP13_COMMAND__Trap13Cmd1__SHIFT 0x8
+#define TRAP13_COMMAND__Trap13Cmd0_MASK 0x0000003FL
+#define TRAP13_COMMAND__Trap13Cmd1_MASK 0x00003F00L
+//TRAP13_ADDRESS_LO_MASK
+#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask__SHIFT 0x2
+#define TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP13_ADDRESS_HI_MASK
+#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask__SHIFT 0x0
+#define TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP13_COMMAND_MASK
+#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask__SHIFT 0x0
+#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask__SHIFT 0x8
+#define TRAP13_COMMAND_MASK__Trap13Cmd0Mask_MASK 0x0000003FL
+#define TRAP13_COMMAND_MASK__Trap13Cmd1Mask_MASK 0x00003F00L
+//TRAP14_CONTROL0
+#define TRAP14_CONTROL0__Trap14En__SHIFT 0x0
+#define TRAP14_CONTROL0__Trap14CrossTrigger__SHIFT 0x18
+#define TRAP14_CONTROL0__Trap14En_MASK 0x00000001L
+#define TRAP14_CONTROL0__Trap14CrossTrigger_MASK 0x0F000000L
+//TRAP14_ADDRESS_LO
+#define TRAP14_ADDRESS_LO__Trap14AddrLo__SHIFT 0x2
+#define TRAP14_ADDRESS_LO__Trap14AddrLo_MASK 0xFFFFFFFCL
+//TRAP14_ADDRESS_HI
+#define TRAP14_ADDRESS_HI__Trap14AddrHi__SHIFT 0x0
+#define TRAP14_ADDRESS_HI__Trap14AddrHi_MASK 0xFFFFFFFFL
+//TRAP14_COMMAND
+#define TRAP14_COMMAND__Trap14Cmd0__SHIFT 0x0
+#define TRAP14_COMMAND__Trap14Cmd1__SHIFT 0x8
+#define TRAP14_COMMAND__Trap14Cmd0_MASK 0x0000003FL
+#define TRAP14_COMMAND__Trap14Cmd1_MASK 0x00003F00L
+//TRAP14_ADDRESS_LO_MASK
+#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask__SHIFT 0x2
+#define TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP14_ADDRESS_HI_MASK
+#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask__SHIFT 0x0
+#define TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP14_COMMAND_MASK
+#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask__SHIFT 0x0
+#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask__SHIFT 0x8
+#define TRAP14_COMMAND_MASK__Trap14Cmd0Mask_MASK 0x0000003FL
+#define TRAP14_COMMAND_MASK__Trap14Cmd1Mask_MASK 0x00003F00L
+//TRAP15_CONTROL0
+#define TRAP15_CONTROL0__Trap15En__SHIFT 0x0
+#define TRAP15_CONTROL0__Trap15CrossTrigger__SHIFT 0x18
+#define TRAP15_CONTROL0__Trap15En_MASK 0x00000001L
+#define TRAP15_CONTROL0__Trap15CrossTrigger_MASK 0x0F000000L
+//TRAP15_ADDRESS_LO
+#define TRAP15_ADDRESS_LO__Trap15AddrLo__SHIFT 0x2
+#define TRAP15_ADDRESS_LO__Trap15AddrLo_MASK 0xFFFFFFFCL
+//TRAP15_ADDRESS_HI
+#define TRAP15_ADDRESS_HI__Trap15AddrHi__SHIFT 0x0
+#define TRAP15_ADDRESS_HI__Trap15AddrHi_MASK 0xFFFFFFFFL
+//TRAP15_COMMAND
+#define TRAP15_COMMAND__Trap15Cmd0__SHIFT 0x0
+#define TRAP15_COMMAND__Trap15Cmd1__SHIFT 0x8
+#define TRAP15_COMMAND__Trap15Cmd0_MASK 0x0000003FL
+#define TRAP15_COMMAND__Trap15Cmd1_MASK 0x00003F00L
+//TRAP15_ADDRESS_LO_MASK
+#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask__SHIFT 0x2
+#define TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask_MASK 0xFFFFFFFCL
+//TRAP15_ADDRESS_HI_MASK
+#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask__SHIFT 0x0
+#define TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask_MASK 0xFFFFFFFFL
+//TRAP15_COMMAND_MASK
+#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask__SHIFT 0x0
+#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask__SHIFT 0x8
+#define TRAP15_COMMAND_MASK__Trap15Cmd0Mask_MASK 0x0000003FL
+#define TRAP15_COMMAND_MASK__Trap15Cmd1Mask_MASK 0x00003F00L
+//SB_COMMAND
+#define SB_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define SB_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define SB_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define SB_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define SB_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define SB_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+//SB_SUB_BUS_NUMBER_LATENCY
+#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define SB_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define SB_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+//SB_IO_BASE_LIMIT
+#define SB_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define SB_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define SB_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define SB_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//SB_MEM_BASE_LIMIT
+#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define SB_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define SB_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//SB_PREF_BASE_LIMIT
+#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define SB_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define SB_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//SB_PREF_BASE_UPPER
+#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define SB_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//SB_PREF_LIMIT_UPPER
+#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define SB_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//SB_IO_BASE_LIMIT_HI
+#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define SB_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define SB_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//SB_IRQ_BRIDGE_CNTL
+#define SB_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define SB_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define SB_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define SB_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define SB_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define SB_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+//SB_EXT_BRIDGE_CNTL
+#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define SB_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//SB_PMI_STATUS_CNTL
+#define SB_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define SB_PMI_STATUS_CNTL__POWER_STATE_MASK 0x03L
+//SB_SLOT_CAP
+#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define SB_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define SB_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+//SB_ROOT_CNTL
+#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define SB_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//SB_DEVICE_CNTL2
+#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define SB_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+//MCA_SMN_INT_REQ_ADDR
+#define MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR__SHIFT 0x0
+#define MCA_SMN_INT_REQ_ADDR__SMN_INT_REQ_ADDR_MASK 0x000FFFFFL
+//MCA_SMN_INT_MCM_ADDR
+#define MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR__SHIFT 0x0
+#define MCA_SMN_INT_MCM_ADDR__SMN_INT_MCM_ADDR_MASK 0x0000000FL
+//MCA_SMN_INT_APERTUREID
+#define MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID__SHIFT 0x0
+#define MCA_SMN_INT_APERTUREID__SMN_INT_APERTUREID_MASK 0x00000FFFL
+//MCA_SMN_INT_CONTROL
+#define MCA_SMN_INT_CONTROL__MCACrossTrigger__SHIFT 0x0
+#define MCA_SMN_INT_CONTROL__MCACrossTrigger_MASK 0x0000000FL
+
+
+// addressBlock: nbio_iohub_mca_iohc_mca_map
+
+
+// addressBlock: nbio_iohub_nb_security_security_cfgdec
+
+
+// addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec
+//PARITY_CONTROL_0
+#define PARITY_CONTROL_0__ParityCorrThreshold__SHIFT 0x0
+#define PARITY_CONTROL_0__ParityUCPThreshold__SHIFT 0x10
+#define PARITY_CONTROL_0__ParityCorrThreshold_MASK 0x0000FFFFL
+#define PARITY_CONTROL_0__ParityUCPThreshold_MASK 0xFFFF0000L
+//PARITY_CONTROL_1
+#define PARITY_CONTROL_1__ParityErrGenGroupSel__SHIFT 0x0
+#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel__SHIFT 0x8
+#define PARITY_CONTROL_1__ParityErrGenIdSel__SHIFT 0xb
+#define PARITY_CONTROL_1__ParityErrGenCmd__SHIFT 0x10
+#define PARITY_CONTROL_1__ParityErrGenTrigger__SHIFT 0x1e
+#define PARITY_CONTROL_1__ParityErrGenInjectAllow__SHIFT 0x1f
+#define PARITY_CONTROL_1__ParityErrGenGroupSel_MASK 0x000000FFL
+#define PARITY_CONTROL_1__ParityErrGenGroupTypeSel_MASK 0x00000100L
+#define PARITY_CONTROL_1__ParityErrGenIdSel_MASK 0x0000F800L
+#define PARITY_CONTROL_1__ParityErrGenCmd_MASK 0x000F0000L
+#define PARITY_CONTROL_1__ParityErrGenTrigger_MASK 0x40000000L
+#define PARITY_CONTROL_1__ParityErrGenInjectAllow_MASK 0x80000000L
+//PARITY_SEVERITY_CONTROL_UNCORR_0
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0__SHIFT 0x0
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1__SHIFT 0x2
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2__SHIFT 0x4
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3__SHIFT 0x6
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4__SHIFT 0x8
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5__SHIFT 0xa
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6__SHIFT 0xc
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7__SHIFT 0xe
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp0_MASK 0x00000003L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp1_MASK 0x0000000CL
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp2_MASK 0x00000030L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp3_MASK 0x000000C0L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp4_MASK 0x00000300L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp5_MASK 0x00000C00L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp6_MASK 0x00003000L
+#define PARITY_SEVERITY_CONTROL_UNCORR_0__ParityErrSevUnCorrGrp7_MASK 0x0000C000L
+//PARITY_SEVERITY_CONTROL_CORR_0
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0__SHIFT 0x0
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1__SHIFT 0x2
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2__SHIFT 0x4
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3__SHIFT 0x6
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4__SHIFT 0x8
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5__SHIFT 0xa
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6__SHIFT 0xc
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7__SHIFT 0xe
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp0_MASK 0x00000003L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp1_MASK 0x0000000CL
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp2_MASK 0x00000030L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp3_MASK 0x000000C0L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp4_MASK 0x00000300L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp5_MASK 0x00000C00L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp6_MASK 0x00003000L
+#define PARITY_SEVERITY_CONTROL_CORR_0__ParityErrSevCorrGrp7_MASK 0x0000C000L
+//PARITY_SEVERITY_CONTROL_UCP_0
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0__SHIFT 0x0
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1__SHIFT 0x2
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2__SHIFT 0x4
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3__SHIFT 0x6
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4__SHIFT 0x8
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5__SHIFT 0xa
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6__SHIFT 0xc
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7__SHIFT 0xe
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp0_MASK 0x00000003L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp1_MASK 0x0000000CL
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp2_MASK 0x00000030L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp3_MASK 0x000000C0L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp4_MASK 0x00000300L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp5_MASK 0x00000C00L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp6_MASK 0x00003000L
+#define PARITY_SEVERITY_CONTROL_UCP_0__ParityErrSevUCPGrp7_MASK 0x0000C000L
+//RAS_GLOBAL_STATUS_LO
+#define RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT 0x0
+#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT 0x1
+#define RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT 0x2
+#define RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT 0x3
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT 0x6
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT 0x7
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT 0x8
+#define RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT 0x9
+#define RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT 0xa
+#define RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT 0xb
+#define RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT 0xc
+#define RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT 0xd
+#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT 0xe
+#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT 0xf
+#define RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK 0x00000001L
+#define RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK 0x00000002L
+#define RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK 0x00000004L
+#define RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK 0x00000008L
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK 0x00000040L
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK 0x00000080L
+#define RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK 0x00000100L
+#define RAS_GLOBAL_STATUS_LO__SW_SMI_MASK 0x00000200L
+#define RAS_GLOBAL_STATUS_LO__SW_SCI_MASK 0x00000400L
+#define RAS_GLOBAL_STATUS_LO__SW_NMI_MASK 0x00000800L
+#define RAS_GLOBAL_STATUS_LO__APML_NMI_MASK 0x00001000L
+#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK 0x00002000L
+#define RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK 0x00004000L
+#define RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK 0x00008000L
+//RAS_GLOBAL_STATUS_HI
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT 0x0
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr__SHIFT 0x1
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr__SHIFT 0x2
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr__SHIFT 0x3
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr__SHIFT 0x4
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr__SHIFT 0x5
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr__SHIFT 0x6
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr__SHIFT 0x7
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortBErr__SHIFT 0x8
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortCErr__SHIFT 0x9
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK 0x00000001L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortBErr_MASK 0x00000002L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortCErr_MASK 0x00000004L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortDErr_MASK 0x00000008L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortEErr_MASK 0x00000010L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortFErr_MASK 0x00000020L
+#define RAS_GLOBAL_STATUS_HI__PCIE0PortGErr_MASK 0x00000040L
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortAErr_MASK 0x00000080L
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortBErr_MASK 0x00000100L
+#define RAS_GLOBAL_STATUS_HI__NBIF1PortCErr_MASK 0x00000200L
+//PARITY_ERROR_STATUS_UNCORR_GRP0
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP1
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP2
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP3
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP4
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP5
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP5__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP6
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP6__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UNCORR_GRP7
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UNCORR_GRP7__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP0
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP0__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP1
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP1__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP2
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP2__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP3
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP3__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP4
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP4__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP5
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP5__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP6
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP6__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_CORR_GRP7
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_CORR_GRP7__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP0
+#define PARITY_COUNTER_CORR_GRP0__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP0__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP0__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP0__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP1
+#define PARITY_COUNTER_CORR_GRP1__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP1__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP1__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP1__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP2
+#define PARITY_COUNTER_CORR_GRP2__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP2__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP2__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP2__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP3
+#define PARITY_COUNTER_CORR_GRP3__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP3__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP3__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP3__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP4
+#define PARITY_COUNTER_CORR_GRP4__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP4__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP4__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP4__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP5
+#define PARITY_COUNTER_CORR_GRP5__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP5__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP5__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP5__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP6
+#define PARITY_COUNTER_CORR_GRP6__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP6__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP6__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP6__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_CORR_GRP7
+#define PARITY_COUNTER_CORR_GRP7__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_CORR_GRP7__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_CORR_GRP7__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_CORR_GRP7__ResetEn_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP0
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP0__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP1
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP1__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP2
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP2__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP3
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP3__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP4
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP4__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP5
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP5__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP6
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP6__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_ERROR_STATUS_UCP_GRP7
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id0__SHIFT 0x0
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id1__SHIFT 0x1
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id2__SHIFT 0x2
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id3__SHIFT 0x3
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id4__SHIFT 0x4
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id5__SHIFT 0x5
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id6__SHIFT 0x6
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id7__SHIFT 0x7
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id8__SHIFT 0x8
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id9__SHIFT 0x9
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id10__SHIFT 0xa
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id11__SHIFT 0xb
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id12__SHIFT 0xc
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id13__SHIFT 0xd
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id14__SHIFT 0xe
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id15__SHIFT 0xf
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id16__SHIFT 0x10
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id17__SHIFT 0x11
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id18__SHIFT 0x12
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id19__SHIFT 0x13
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id20__SHIFT 0x14
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id21__SHIFT 0x15
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id22__SHIFT 0x16
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id23__SHIFT 0x17
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id24__SHIFT 0x18
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id25__SHIFT 0x19
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id26__SHIFT 0x1a
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id27__SHIFT 0x1b
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id28__SHIFT 0x1c
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id29__SHIFT 0x1d
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id30__SHIFT 0x1e
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id31__SHIFT 0x1f
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id0_MASK 0x00000001L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id1_MASK 0x00000002L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id2_MASK 0x00000004L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id3_MASK 0x00000008L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id4_MASK 0x00000010L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id5_MASK 0x00000020L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id6_MASK 0x00000040L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id7_MASK 0x00000080L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id8_MASK 0x00000100L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id9_MASK 0x00000200L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id10_MASK 0x00000400L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id11_MASK 0x00000800L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id12_MASK 0x00001000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id13_MASK 0x00002000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id14_MASK 0x00004000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id15_MASK 0x00008000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id16_MASK 0x00010000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id17_MASK 0x00020000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id18_MASK 0x00040000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id19_MASK 0x00080000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id20_MASK 0x00100000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id21_MASK 0x00200000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id22_MASK 0x00400000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id23_MASK 0x00800000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id24_MASK 0x01000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id25_MASK 0x02000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id26_MASK 0x04000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id27_MASK 0x08000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id28_MASK 0x10000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id29_MASK 0x20000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id30_MASK 0x40000000L
+#define PARITY_ERROR_STATUS_UCP_GRP7__ParityErrDetected_Id31_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP0
+#define PARITY_COUNTER_UCP_GRP0__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP0__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP0__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP0__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP1
+#define PARITY_COUNTER_UCP_GRP1__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP1__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP1__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP1__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP2
+#define PARITY_COUNTER_UCP_GRP2__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP2__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP2__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP2__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP3
+#define PARITY_COUNTER_UCP_GRP3__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP3__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP3__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP3__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP4
+#define PARITY_COUNTER_UCP_GRP4__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP4__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP4__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP4__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP5
+#define PARITY_COUNTER_UCP_GRP5__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP5__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP5__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP5__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP6
+#define PARITY_COUNTER_UCP_GRP6__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP6__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP6__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP6__ResetEn_MASK 0x80000000L
+//PARITY_COUNTER_UCP_GRP7
+#define PARITY_COUNTER_UCP_GRP7__ThresholdCounter__SHIFT 0x0
+#define PARITY_COUNTER_UCP_GRP7__ResetEn__SHIFT 0x1f
+#define PARITY_COUNTER_UCP_GRP7__ThresholdCounter_MASK 0x0000FFFFL
+#define PARITY_COUNTER_UCP_GRP7__ResetEn_MASK 0x80000000L
+//MISC_SEVERITY_CONTROL
+#define MISC_SEVERITY_CONTROL__ErrEventErrSev__SHIFT 0x4
+#define MISC_SEVERITY_CONTROL__PcieParityErrSev__SHIFT 0x6
+#define MISC_SEVERITY_CONTROL__ErrEventErrSev_MASK 0x00000030L
+#define MISC_SEVERITY_CONTROL__PcieParityErrSev_MASK 0x000000C0L
+//MISC_RAS_CONTROL
+#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En__SHIFT 0x2
+#define MISC_RAS_CONTROL__InterruptOutputDis__SHIFT 0x9
+#define MISC_RAS_CONTROL__LinkDisOutputDis__SHIFT 0xa
+#define MISC_RAS_CONTROL__SyncFldOutputDis__SHIFT 0xb
+#define MISC_RAS_CONTROL__PCIe_NMI_En__SHIFT 0xc
+#define MISC_RAS_CONTROL__PCIe_SCI_En__SHIFT 0xd
+#define MISC_RAS_CONTROL__PCIe_SMI_En__SHIFT 0xe
+#define MISC_RAS_CONTROL__SW_SCI_En__SHIFT 0xf
+#define MISC_RAS_CONTROL__SW_SMI_En__SHIFT 0x10
+#define MISC_RAS_CONTROL__SW_NMI_En__SHIFT 0x11
+#define MISC_RAS_CONTROL__PIN_NMI_SyncFlood_En_MASK 0x00000004L
+#define MISC_RAS_CONTROL__InterruptOutputDis_MASK 0x00000200L
+#define MISC_RAS_CONTROL__LinkDisOutputDis_MASK 0x00000400L
+#define MISC_RAS_CONTROL__SyncFldOutputDis_MASK 0x00000800L
+#define MISC_RAS_CONTROL__PCIe_NMI_En_MASK 0x00001000L
+#define MISC_RAS_CONTROL__PCIe_SCI_En_MASK 0x00002000L
+#define MISC_RAS_CONTROL__PCIe_SMI_En_MASK 0x00004000L
+#define MISC_RAS_CONTROL__SW_SCI_En_MASK 0x00008000L
+#define MISC_RAS_CONTROL__SW_SMI_En_MASK 0x00010000L
+#define MISC_RAS_CONTROL__SW_NMI_En_MASK 0x00020000L
+//RAS_SCRATCH_0
+#define RAS_SCRATCH_0__SCRATCH_0__SHIFT 0x0
+#define RAS_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL
+//RAS_SCRATCH_1
+#define RAS_SCRATCH_1__SCRATCH_1__SHIFT 0x0
+#define RAS_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL
+//ErrEvent_ACTION_CONTROL
+#define ErrEvent_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define ErrEvent_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define ErrEvent_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define ErrEvent_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define ErrEvent_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define ErrEvent_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define ErrEvent_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define ErrEvent_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//ParitySerr_ACTION_CONTROL
+#define ParitySerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define ParitySerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define ParitySerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define ParitySerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define ParitySerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define ParitySerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define ParitySerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define ParitySerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//ParityFatal_ACTION_CONTROL
+#define ParityFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define ParityFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define ParityFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define ParityFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define ParityFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define ParityFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define ParityFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define ParityFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//ParityNonFatal_ACTION_CONTROL
+#define ParityNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define ParityNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define ParityNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define ParityNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define ParityNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define ParityNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define ParityNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define ParityNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//ParityCorr_ACTION_CONTROL
+#define ParityCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define ParityCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define ParityCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define ParityCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define ParityCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define ParityCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define ParityCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define ParityCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortASerr_ACTION_CONTROL
+#define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortASerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortASerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortASerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortASerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAIntFatal_ACTION_CONTROL
+#define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAIntNonFatal_ACTION_CONTROL
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAIntCorr_ACTION_CONTROL
+#define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAExtFatal_ACTION_CONTROL
+#define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAExtNonFatal_ACTION_CONTROL
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAExtCorr_ACTION_CONTROL
+#define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortAParityErr_ACTION_CONTROL
+#define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBSerr_ACTION_CONTROL
+#define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBIntFatal_ACTION_CONTROL
+#define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBIntNonFatal_ACTION_CONTROL
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBIntCorr_ACTION_CONTROL
+#define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBExtFatal_ACTION_CONTROL
+#define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBExtNonFatal_ACTION_CONTROL
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBExtCorr_ACTION_CONTROL
+#define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortBParityErr_ACTION_CONTROL
+#define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCSerr_ACTION_CONTROL
+#define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCIntFatal_ACTION_CONTROL
+#define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCIntNonFatal_ACTION_CONTROL
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCIntCorr_ACTION_CONTROL
+#define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCExtFatal_ACTION_CONTROL
+#define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCExtNonFatal_ACTION_CONTROL
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCExtCorr_ACTION_CONTROL
+#define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortCParityErr_ACTION_CONTROL
+#define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortCParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortCParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortCParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortCParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDSerr_ACTION_CONTROL
+#define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDIntFatal_ACTION_CONTROL
+#define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDIntNonFatal_ACTION_CONTROL
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDIntCorr_ACTION_CONTROL
+#define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDExtFatal_ACTION_CONTROL
+#define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDExtNonFatal_ACTION_CONTROL
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDExtCorr_ACTION_CONTROL
+#define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortDParityErr_ACTION_CONTROL
+#define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortDParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortDParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortDParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortDParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortESerr_ACTION_CONTROL
+#define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortESerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortESerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortESerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortESerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEIntFatal_ACTION_CONTROL
+#define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEIntNonFatal_ACTION_CONTROL
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEIntCorr_ACTION_CONTROL
+#define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEExtFatal_ACTION_CONTROL
+#define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEExtNonFatal_ACTION_CONTROL
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEExtCorr_ACTION_CONTROL
+#define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortEParityErr_ACTION_CONTROL
+#define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortEParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortEParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortEParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortEParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFSerr_ACTION_CONTROL
+#define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFIntFatal_ACTION_CONTROL
+#define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFIntNonFatal_ACTION_CONTROL
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFIntCorr_ACTION_CONTROL
+#define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFExtFatal_ACTION_CONTROL
+#define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFExtNonFatal_ACTION_CONTROL
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFExtCorr_ACTION_CONTROL
+#define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortFParityErr_ACTION_CONTROL
+#define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortFParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortFParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortFParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortFParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGSerr_ACTION_CONTROL
+#define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGIntFatal_ACTION_CONTROL
+#define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGIntNonFatal_ACTION_CONTROL
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGIntCorr_ACTION_CONTROL
+#define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGExtFatal_ACTION_CONTROL
+#define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGExtNonFatal_ACTION_CONTROL
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGExtCorr_ACTION_CONTROL
+#define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//PCIE0PortGParityErr_ACTION_CONTROL
+#define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define PCIE0PortGParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define PCIE0PortGParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define PCIE0PortGParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define PCIE0PortGParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortASerr_ACTION_CONTROL
+#define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortASerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortASerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortASerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortASerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAIntFatal_ACTION_CONTROL
+#define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAIntNonFatal_ACTION_CONTROL
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAIntCorr_ACTION_CONTROL
+#define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAExtFatal_ACTION_CONTROL
+#define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAExtNonFatal_ACTION_CONTROL
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAExtCorr_ACTION_CONTROL
+#define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortAParityErr_ACTION_CONTROL
+#define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortAParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortAParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortAParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortAParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBSerr_ACTION_CONTROL
+#define NBIF1PortBSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBIntFatal_ACTION_CONTROL
+#define NBIF1PortBIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBIntNonFatal_ACTION_CONTROL
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBIntCorr_ACTION_CONTROL
+#define NBIF1PortBIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBExtFatal_ACTION_CONTROL
+#define NBIF1PortBExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBExtNonFatal_ACTION_CONTROL
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBExtCorr_ACTION_CONTROL
+#define NBIF1PortBExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortBParityErr_ACTION_CONTROL
+#define NBIF1PortBParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortBParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortBParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortBParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortBParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortBParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortBParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortBParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortCSerr_ACTION_CONTROL
+#define NBIF1PortCSerr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortCSerr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortCSerr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortCSerr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortCSerr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortCSerr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortCSerr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortCSerr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortCIntFatal_ACTION_CONTROL
+#define NBIF1PortCIntFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortCIntFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortCIntFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortCIntFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortCIntFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortCIntFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortCIntFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortCIntFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortCIntNonFatal_ACTION_CONTROL
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortCIntNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortCIntCorr_ACTION_CONTROL
+#define NBIF1PortCIntCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortCIntCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortCIntCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortCIntCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortCIntCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortCIntCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortCIntCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortCIntCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortCExtFatal_ACTION_CONTROL
+#define NBIF1PortCExtFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortCExtFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortCExtFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortCExtFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortCExtFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortCExtFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortCExtFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortCExtFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortCExtNonFatal_ACTION_CONTROL
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortCExtNonFatal_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortCExtCorr_ACTION_CONTROL
+#define NBIF1PortCExtCorr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortCExtCorr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortCExtCorr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortCExtCorr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortCExtCorr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortCExtCorr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortCExtCorr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortCExtCorr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//NBIF1PortCParityErr_ACTION_CONTROL
+#define NBIF1PortCParityErr_ACTION_CONTROL__APML_ERR_En__SHIFT 0x0
+#define NBIF1PortCParityErr_ACTION_CONTROL__IntrGenSel__SHIFT 0x1
+#define NBIF1PortCParityErr_ACTION_CONTROL__LinkDis_En__SHIFT 0x3
+#define NBIF1PortCParityErr_ACTION_CONTROL__SyncFlood_En__SHIFT 0x4
+#define NBIF1PortCParityErr_ACTION_CONTROL__APML_ERR_En_MASK 0x00000001L
+#define NBIF1PortCParityErr_ACTION_CONTROL__IntrGenSel_MASK 0x00000006L
+#define NBIF1PortCParityErr_ACTION_CONTROL__LinkDis_En_MASK 0x00000008L
+#define NBIF1PortCParityErr_ACTION_CONTROL__SyncFlood_En_MASK 0x00000010L
+//SYNCFLOOD_STATUS
+#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl__SHIFT 0x0
+#define SYNCFLOOD_STATUS__SyncfloodFromAPML__SHIFT 0x1
+#define SYNCFLOOD_STATUS__SyncfloodFromPin__SHIFT 0x2
+#define SYNCFLOOD_STATUS__SyncfloodFromPrivate__SHIFT 0x4
+#define SYNCFLOOD_STATUS__SyncfloodFromMCA__SHIFT 0x5
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8__SHIFT 0x8
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9__SHIFT 0x9
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10__SHIFT 0xa
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11__SHIFT 0xb
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12__SHIFT 0xc
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13__SHIFT 0xd
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14__SHIFT 0xe
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15__SHIFT 0xf
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16__SHIFT 0x10
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17__SHIFT 0x11
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18__SHIFT 0x12
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19__SHIFT 0x13
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20__SHIFT 0x14
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21__SHIFT 0x15
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22__SHIFT 0x16
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23__SHIFT 0x17
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24__SHIFT 0x18
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25__SHIFT 0x19
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26__SHIFT 0x1a
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27__SHIFT 0x1b
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28__SHIFT 0x1c
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29__SHIFT 0x1d
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30__SHIFT 0x1e
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31__SHIFT 0x1f
+#define SYNCFLOOD_STATUS__SyncfloodFromRASCntl_MASK 0x00000001L
+#define SYNCFLOOD_STATUS__SyncfloodFromAPML_MASK 0x00000002L
+#define SYNCFLOOD_STATUS__SyncfloodFromPin_MASK 0x00000004L
+#define SYNCFLOOD_STATUS__SyncfloodFromPrivate_MASK 0x00000010L
+#define SYNCFLOOD_STATUS__SyncfloodFromMCA_MASK 0x00000020L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_8_MASK 0x00000100L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_9_MASK 0x00000200L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_10_MASK 0x00000400L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_11_MASK 0x00000800L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_12_MASK 0x00001000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_13_MASK 0x00002000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_14_MASK 0x00004000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_15_MASK 0x00008000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_16_MASK 0x00010000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_17_MASK 0x00020000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_18_MASK 0x00040000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_19_MASK 0x00080000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_20_MASK 0x00100000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_21_MASK 0x00200000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_22_MASK 0x00400000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_23_MASK 0x00800000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_24_MASK 0x01000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_25_MASK 0x02000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_26_MASK 0x04000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_27_MASK 0x08000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_28_MASK 0x10000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_29_MASK 0x20000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_30_MASK 0x40000000L
+#define SYNCFLOOD_STATUS__SyncfloodFromIOHCPortN_31_MASK 0x80000000L
+//NMI_STATUS
+#define NMI_STATUS__NMIFromPin__SHIFT 0x0
+#define NMI_STATUS__NMIFromPin_MASK 0x00000001L
+//POISON_ACTION_CONTROL
+#define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn__SHIFT 0x0
+#define POISON_ACTION_CONTROL__IntPoisonIntrGenSel__SHIFT 0x1
+#define POISON_ACTION_CONTROL__IntPoisonLinkDisEn__SHIFT 0x3
+#define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn__SHIFT 0x4
+#define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn__SHIFT 0x8
+#define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel__SHIFT 0x9
+#define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn__SHIFT 0xb
+#define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn__SHIFT 0xc
+#define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn__SHIFT 0x10
+#define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel__SHIFT 0x11
+#define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn__SHIFT 0x13
+#define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn__SHIFT 0x14
+#define POISON_ACTION_CONTROL__IntPoisonAPMLErrEn_MASK 0x00000001L
+#define POISON_ACTION_CONTROL__IntPoisonIntrGenSel_MASK 0x00000006L
+#define POISON_ACTION_CONTROL__IntPoisonLinkDisEn_MASK 0x00000008L
+#define POISON_ACTION_CONTROL__IntPoisonSyncFloodEn_MASK 0x00000010L
+#define POISON_ACTION_CONTROL__EgressPoisonLSAPMLErrEn_MASK 0x00000100L
+#define POISON_ACTION_CONTROL__EgressPoisonLSIntrGenSel_MASK 0x00000600L
+#define POISON_ACTION_CONTROL__EgressPoisonLSLinkDisEn_MASK 0x00000800L
+#define POISON_ACTION_CONTROL__EgressPoisonLSSyncFloodEn_MASK 0x00001000L
+#define POISON_ACTION_CONTROL__EgressPoisonHSAPMLErrEn_MASK 0x00010000L
+#define POISON_ACTION_CONTROL__EgressPoisonHSIntrGenSel_MASK 0x00060000L
+#define POISON_ACTION_CONTROL__EgressPoisonHSLinkDisEn_MASK 0x00080000L
+#define POISON_ACTION_CONTROL__EgressPoisonHSSyncFloodEn_MASK 0x00100000L
+//EGRESS_POISON_STATUS_LO
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0__SHIFT 0x0
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1__SHIFT 0x1
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2__SHIFT 0x2
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3__SHIFT 0x3
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4__SHIFT 0x4
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5__SHIFT 0x5
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6__SHIFT 0x6
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7__SHIFT 0x7
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8__SHIFT 0x8
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9__SHIFT 0x9
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10__SHIFT 0xa
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11__SHIFT 0xb
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12__SHIFT 0xc
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13__SHIFT 0xd
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14__SHIFT 0xe
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15__SHIFT 0xf
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16__SHIFT 0x10
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17__SHIFT 0x11
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18__SHIFT 0x12
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19__SHIFT 0x13
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20__SHIFT 0x14
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21__SHIFT 0x15
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22__SHIFT 0x16
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23__SHIFT 0x17
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24__SHIFT 0x18
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25__SHIFT 0x19
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26__SHIFT 0x1a
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27__SHIFT 0x1b
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28__SHIFT 0x1c
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29__SHIFT 0x1d
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30__SHIFT 0x1e
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31__SHIFT 0x1f
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_0_MASK 0x00000001L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_1_MASK 0x00000002L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_2_MASK 0x00000004L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_3_MASK 0x00000008L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_4_MASK 0x00000010L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_5_MASK 0x00000020L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_6_MASK 0x00000040L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_7_MASK 0x00000080L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_8_MASK 0x00000100L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_9_MASK 0x00000200L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_10_MASK 0x00000400L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_11_MASK 0x00000800L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_12_MASK 0x00001000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_13_MASK 0x00002000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_14_MASK 0x00004000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_15_MASK 0x00008000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_16_MASK 0x00010000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_17_MASK 0x00020000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_18_MASK 0x00040000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_19_MASK 0x00080000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_20_MASK 0x00100000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_21_MASK 0x00200000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_22_MASK 0x00400000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_23_MASK 0x00800000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_24_MASK 0x01000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_25_MASK 0x02000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_26_MASK 0x04000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_27_MASK 0x08000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_28_MASK 0x10000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_29_MASK 0x20000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_30_MASK 0x40000000L
+#define EGRESS_POISON_STATUS_LO__EgressPoisonStatusLo_31_MASK 0x80000000L
+//EGRESS_POISON_STATUS_HI
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0__SHIFT 0x0
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1__SHIFT 0x1
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2__SHIFT 0x2
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3__SHIFT 0x3
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4__SHIFT 0x4
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5__SHIFT 0x5
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6__SHIFT 0x6
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7__SHIFT 0x7
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8__SHIFT 0x8
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9__SHIFT 0x9
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10__SHIFT 0xa
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11__SHIFT 0xb
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12__SHIFT 0xc
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13__SHIFT 0xd
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14__SHIFT 0xe
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15__SHIFT 0xf
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16__SHIFT 0x10
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17__SHIFT 0x11
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18__SHIFT 0x12
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19__SHIFT 0x13
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20__SHIFT 0x14
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21__SHIFT 0x15
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22__SHIFT 0x16
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23__SHIFT 0x17
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24__SHIFT 0x18
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25__SHIFT 0x19
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26__SHIFT 0x1a
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27__SHIFT 0x1b
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28__SHIFT 0x1c
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29__SHIFT 0x1d
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30__SHIFT 0x1e
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31__SHIFT 0x1f
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_0_MASK 0x00000001L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_1_MASK 0x00000002L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_2_MASK 0x00000004L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_3_MASK 0x00000008L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_4_MASK 0x00000010L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_5_MASK 0x00000020L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_6_MASK 0x00000040L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_7_MASK 0x00000080L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_8_MASK 0x00000100L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_9_MASK 0x00000200L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_10_MASK 0x00000400L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_11_MASK 0x00000800L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_12_MASK 0x00001000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_13_MASK 0x00002000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_14_MASK 0x00004000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_15_MASK 0x00008000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_16_MASK 0x00010000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_17_MASK 0x00020000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_18_MASK 0x00040000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_19_MASK 0x00080000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_20_MASK 0x00100000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_21_MASK 0x00200000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_22_MASK 0x00400000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_23_MASK 0x00800000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_24_MASK 0x01000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_25_MASK 0x02000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_26_MASK 0x04000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_27_MASK 0x08000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_28_MASK 0x10000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_29_MASK 0x20000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_30_MASK 0x40000000L
+#define EGRESS_POISON_STATUS_HI__EgressPoisonStatusHi_31_MASK 0x80000000L
+//EGRESS_POISON_MASK_LO
+#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo__SHIFT 0x0
+#define EGRESS_POISON_MASK_LO__EgressPoisonMaskLo_MASK 0xFFFFFFFFL
+//EGRESS_POISON_MASK_HI
+#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi__SHIFT 0x0
+#define EGRESS_POISON_MASK_HI__EgressPoisonMaskHi_MASK 0xFFFFFFFFL
+//EGRESS_POISON_SEVERITY_DOWN
+#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown__SHIFT 0x0
+#define EGRESS_POISON_SEVERITY_DOWN__EgressPoisonSeverityDown_MASK 0xFFFFFFFFL
+//EGRESS_POISON_SEVERITY_UPPER
+#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper__SHIFT 0x0
+#define EGRESS_POISON_SEVERITY_UPPER__EgressPoisonSeverityUpper_MASK 0xFFFFFFFFL
+//APML_STATUS
+#define APML_STATUS__APML_Corr__SHIFT 0x0
+#define APML_STATUS__APML_NonFatal__SHIFT 0x1
+#define APML_STATUS__APML_Fatal__SHIFT 0x2
+#define APML_STATUS__APML_Serr__SHIFT 0x3
+#define APML_STATUS__APML_IntPoisonErr__SHIFT 0x4
+#define APML_STATUS__APML_EgressPoisonErrLo__SHIFT 0x5
+#define APML_STATUS__APML_EgressPoisonErrHi__SHIFT 0x6
+#define APML_STATUS__APML_Corr_MASK 0x00000001L
+#define APML_STATUS__APML_NonFatal_MASK 0x00000002L
+#define APML_STATUS__APML_Fatal_MASK 0x00000004L
+#define APML_STATUS__APML_Serr_MASK 0x00000008L
+#define APML_STATUS__APML_IntPoisonErr_MASK 0x00000010L
+#define APML_STATUS__APML_EgressPoisonErrLo_MASK 0x00000020L
+#define APML_STATUS__APML_EgressPoisonErrHi_MASK 0x00000040L
+//APML_CONTROL
+#define APML_CONTROL__APML_NMI_En__SHIFT 0x0
+#define APML_CONTROL__APML_SyncFlood_En__SHIFT 0x1
+#define APML_CONTROL__APML_OutputDis__SHIFT 0x8
+#define APML_CONTROL__APML_NMI_En_MASK 0x00000001L
+#define APML_CONTROL__APML_SyncFlood_En_MASK 0x00000002L
+#define APML_CONTROL__APML_OutputDis_MASK 0x00000100L
+//APML_TRIGGER
+#define APML_TRIGGER__APML_NMI_TRIGGER__SHIFT 0x0
+#define APML_TRIGGER__APML_NMI_TRIGGER_MASK 0x00000001L
+
+
+
+
+
+
+
+
+
+
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF2_MM_INDEX
+#define BIF_BX_PF2_MM_INDEX__MM_OFFSET__SHIFT 0x0
+#define BIF_BX_PF2_MM_INDEX__MM_APER__SHIFT 0x1f
+#define BIF_BX_PF2_MM_INDEX__MM_OFFSET_MASK 0x7FFFFFFFL
+#define BIF_BX_PF2_MM_INDEX__MM_APER_MASK 0x80000000L
+//BIF_BX_PF2_MM_DATA
+#define BIF_BX_PF2_MM_DATA__MM_DATA__SHIFT 0x0
+#define BIF_BX_PF2_MM_DATA__MM_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF2_MM_INDEX_HI
+#define BIF_BX_PF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
+#define BIF_BX_PF2_MM_INDEX_HI__MM_OFFSET_HI_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_SYSDEC
+//BIF_BX2_PCIE_INDEX
+#define BIF_BX2_PCIE_INDEX__PCIE_INDEX__SHIFT 0x0
+#define BIF_BX2_PCIE_INDEX__PCIE_INDEX_MASK 0xFFFFFFFFL
+//BIF_BX2_PCIE_DATA
+#define BIF_BX2_PCIE_DATA__PCIE_DATA__SHIFT 0x0
+#define BIF_BX2_PCIE_DATA__PCIE_DATA_MASK 0xFFFFFFFFL
+//BIF_BX2_PCIE_INDEX2
+#define BIF_BX2_PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0
+#define BIF_BX2_PCIE_INDEX2__PCIE_INDEX2_MASK 0xFFFFFFFFL
+//BIF_BX2_PCIE_DATA2
+#define BIF_BX2_PCIE_DATA2__PCIE_DATA2__SHIFT 0x0
+#define BIF_BX2_PCIE_DATA2__PCIE_DATA2_MASK 0xFFFFFFFFL
+//BIF_BX2_SBIOS_SCRATCH_0
+#define BIF_BX2_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX2_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX2_SBIOS_SCRATCH_1
+#define BIF_BX2_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX2_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX2_SBIOS_SCRATCH_2
+#define BIF_BX2_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX2_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX2_SBIOS_SCRATCH_3
+#define BIF_BX2_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0
+#define BIF_BX2_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_0
+#define BIF_BX2_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_1
+#define BIF_BX2_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_2
+#define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_3
+#define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_4
+#define BIF_BX2_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_5
+#define BIF_BX2_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_6
+#define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_7
+#define BIF_BX2_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_8
+#define BIF_BX2_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_9
+#define BIF_BX2_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_10
+#define BIF_BX2_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_11
+#define BIF_BX2_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_12
+#define BIF_BX2_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_13
+#define BIF_BX2_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_14
+#define BIF_BX2_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK 0xFFFFFFFFL
+//BIF_BX2_BIOS_SCRATCH_15
+#define BIF_BX2_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0
+#define BIF_BX2_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK 0xFFFFFFFFL
+//BIF_BX2_BIF_RLC_INTR_CNTL
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX2_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX2_BIF_VCE_INTR_CNTL
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX2_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK 0x00000008L
+//BIF_BX2_BIF_UVD_INTR_CNTL
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_INST_SEL__SHIFT 0x1c
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK 0x00000001L
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK 0x00000002L
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK 0x00000004L
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK 0x00000008L
+#define BIF_BX2_BIF_UVD_INTR_CNTL__UVD_INST_SEL_MASK 0xF0000000L
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK 0x000FFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX2_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK 0x000000FFL
+//BIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK 0xFFFFFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX2_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK 0xFFFFFFFFL
+//BIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0
+#define BIF_BX2_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_syshub_mmreg_syshubdec
+
+
+// addressBlock: nbio_nbif0_rcc_strap_BIFDEC1
+//RCC_STRAP3_RCC_BIF_STRAP0
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT 0x0
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT 0x2
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT 0x3
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT 0x6
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT 0x8
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT 0x9
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT 0xa
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT 0xb
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT 0xc
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT 0xd
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0xe
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0xf
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT 0x10
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT 0x11
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT 0x18
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT 0x19
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT 0x1a
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT 0x1b
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT 0x1d
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT 0x1e
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT 0x1f
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK 0x00000001L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK 0x00000004L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK 0x00000038L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK 0x00000040L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK 0x00000100L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK 0x00000200L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK 0x00000400L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK 0x00000800L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK 0x00001000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK 0x00002000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00004000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00008000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK 0x00010000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK 0x00020000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK 0x01000000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK 0x02000000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK 0x04000000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK 0x08000000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK 0x20000000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK 0x40000000L
+#define RCC_STRAP3_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK 0x80000000L
+//RCC_STRAP3_RCC_BIF_STRAP1
+#define RCC_STRAP3_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT 0x1
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT 0x3
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT 0x5
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT 0x6
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT 0x7
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT 0x8
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT 0x9
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT 0xa
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT 0xc
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT 0xd
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT 0xf
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT 0x11
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT 0x12
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT 0x13
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT 0x14
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT 0x15
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT 0x16
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT 0x17
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT 0x1a
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT 0x1b
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT 0x1d
+#define RCC_STRAP3_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK 0x00000002L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK 0x00000008L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK 0x00000020L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK 0x00000040L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK 0x00000080L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK 0x00000100L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK 0x00000200L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK 0x00000C00L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK 0x00001000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK 0x00006000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK 0x00018000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK 0x00020000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK 0x00040000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK 0x00080000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK 0x00100000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK 0x00200000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK 0x00400000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK 0x00800000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK 0x04000000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK 0x18000000L
+#define RCC_STRAP3_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK 0x20000000L
+//RCC_STRAP3_RCC_BIF_STRAP2
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT 0x0
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT 0x3
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT 0x4
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT 0x5
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT 0x6
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT 0x8
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT 0x9
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT 0xa
+#define RCC_STRAP3_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT 0xd
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT 0xe
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT 0xf
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT 0x10
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT 0x18
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT 0x1f
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK 0x00000001L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK 0x00000008L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK 0x00000010L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK 0x00000020L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK 0x00000040L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK 0x00000100L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK 0x00000200L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK 0x00000C00L
+#define RCC_STRAP3_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK 0x00002000L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK 0x00008000L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK 0x00FF0000L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK 0x01000000L
+#define RCC_STRAP3_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK 0x80000000L
+//RCC_STRAP3_RCC_BIF_STRAP3
+#define RCC_STRAP3_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
+#define RCC_STRAP3_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
+#define RCC_STRAP3_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP3_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP3_RCC_BIF_STRAP4
+#define RCC_STRAP3_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT 0x0
+#define RCC_STRAP3_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT 0x10
+#define RCC_STRAP3_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP3_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK 0xFFFF0000L
+//RCC_STRAP3_RCC_BIF_STRAP5
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT 0x10
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT 0x11
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT 0x12
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT 0x13
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT 0x14
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT 0x16
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT 0x18
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x19
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1b
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT 0x1c
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK 0x00010000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK 0x00020000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK 0x00040000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK 0x00080000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK 0x00100000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK 0x00C00000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK 0x01000000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK 0x06000000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK 0x08000000L
+#define RCC_STRAP3_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK 0x70000000L
+//RCC_STRAP3_RCC_BIF_STRAP6
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK 0x00000008L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK 0x00000010L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK 0x001FFFE0L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK 0x00E00000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK 0x0E000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK 0x70000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK 0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT 0x11
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x12
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK 0x00000001L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK 0x00000002L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK 0x00000004L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK 0x00000008L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK 0x00000010L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK 0x00000040L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK 0x00000100L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK 0x00000E00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK 0x00001000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK 0x00002000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK 0x00004000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK 0x00008000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK 0x00010000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK 0x00020000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK 0x000C0000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK 0x00700000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK 0x03800000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK 0x1C000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK 0xE0000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK 0x00000002L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK 0x00000004L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK 0x00000038L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK 0x00000040L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK 0x00000080L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK 0x00000100L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK 0x00000600L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x00003800L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK 0x0003C000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK 0x001C0000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK 0x01E00000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK 0x06000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK 0x18000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK 0x80000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK 0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK 0xFF000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT 0x16
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK 0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK 0x00010000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK 0x00020000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK 0x00040000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK 0x00080000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK 0x00100000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK 0x00200000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK 0x00400000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK 0x00800000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK 0x01000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK 0x02000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK 0x04000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK 0x08000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK 0x10000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK 0x20000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK 0x40000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK 0x80000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x3
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT 0x4
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT 0x5
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x6
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT 0x7
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT 0xc
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT 0x12
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT 0x13
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK 0x00000001L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK 0x00000002L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000008L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK 0x00000010L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK 0x00000020L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000040L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK 0x00000080L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK 0x00000F00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK 0x0000F000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK 0x00030000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK 0x00040000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK 0x00080000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK 0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK 0x00000F00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK 0x0000F000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK 0x1F000000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK 0xE0000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT 0x18
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK 0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK 0x00FF0000L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK 0xFF000000L
+//RCC_STRAP3_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK 0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK 0x0000FF00L
+#define RCC_STRAP3_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK 0xFFFF0000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK 0x000F0000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK 0x00F00000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK 0x0F000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK 0xFFFF0000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK 0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK 0x0000FF00L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK 0x00FF0000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK 0x0000FFFFL
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK 0x0000003EL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK 0x00000040L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK 0x00003E00L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK 0x00004000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK 0x00008000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK 0x00010000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK 0x00020000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK 0x00800000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK 0x07000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK 0x40000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT 0x1d
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK 0x00000001L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK 0x00000002L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK 0x0003FFFCL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK 0x00E00000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK 0x01000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK 0x08000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK 0x10000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK 0x20000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK 0x40000000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK 0x000003FFL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK 0x00400000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK 0x0F800000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK 0x70000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK 0x80000000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK 0x40000000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0x4
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xd
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x17
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x1a
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00000007L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK 0x00000008L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK 0x00000070L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK 0x00000080L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK 0x00000100L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK 0x00001E00L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK 0x0000E000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK 0x00070000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK 0x00780000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK 0x03800000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK 0x04000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK 0x38000000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK 0xC0000000L
+//RCC_STRAP3_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x12
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x13
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x14
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x15
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x16
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT 0x18
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK 0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK 0x00040000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK 0x00080000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK 0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK 0x00200000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK 0x00C00000L
+#define RCC_STRAP3_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK 0x0F000000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK 0x000F0000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK 0x00F00000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP10
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP11
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP12
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK 0x000000FFL
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK 0x0000FF00L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK 0x00FF0000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP14
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK 0x0000FFFFL
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT 0x9
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK 0x00000080L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK 0x00000100L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK 0x00003E00L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK 0x00004000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK 0x00010000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK 0x00020000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK 0x00800000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK 0x07000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK 0x10000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK 0x40000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT 0x1d
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK 0x0003FFFCL
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK 0x00040000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK 0x00080000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK 0x01000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK 0x04000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK 0x08000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK 0x20000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK 0x40000000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK 0x00100000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK 0x00200000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK 0x00400000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK 0x0F800000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK 0x70000000L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK 0x80000000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT 0x1e
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK 0x0000FFFFL
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK 0x40000000L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK 0x00000001L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK 0x00000002L
+#define RCC_STRAP3_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK 0x00000004L
+//RCC_STRAP3_RCC_DEV0_EPF1_STRAP7
+
+
+// addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1
+//RCC_EP_DEV0_3_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_3_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_3_EP_PCIE_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_3_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8
+#define RCC_EP_DEV0_3_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_EP_DEV0_3_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK 0x00000080L
+#define RCC_EP_DEV0_3_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK 0x00000100L
+#define RCC_EP_DEV0_3_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_EP_DEV0_3_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK 0x00000001L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK 0x00000002L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK 0x00000004L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK 0x00000008L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK 0x00000010L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK 0x00000040L
+//RCC_EP_DEV0_3_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK 0x00000001L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK 0x00000002L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK 0x00000004L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK 0x00000008L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK 0x00000010L
+#define RCC_EP_DEV0_3_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK 0x00000040L
+//RCC_EP_DEV0_3_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK 0x00000001L
+//RCC_EP_DEV0_3_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_EP_DEV0_3_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+//RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_EP_DEV0_3_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT 0x11
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK 0x00000007L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK 0x00000038L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK 0x00000040L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK 0x00000380L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK 0x00001C00L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK 0x00002000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK 0x00004000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK 0x00008000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK 0x00010000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK 0x00020000L
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_2_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_3_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_3_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_EP_DEV0_3_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_EP_DEV0_3_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_3_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4
+#define RCC_EP_DEV0_3_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK 0x00000010L
+//RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//RCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0xFFL
+//RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK 0x001FL
+#define RCC_EP_DEV0_3_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK 0x0100L
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define RCC_EP_DEV0_3_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//RCC_EP_DEV0_3_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_3_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK 0x1FL
+//RCC_EP_DEV0_3_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_3_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK 0xFFFFFFFFL
+//RCC_EP_DEV0_3_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK 0x00000C00L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK 0x00003000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK 0x01000000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK 0x02000000L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3
+#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8
+#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK 0x00000007L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK 0x000000F8L
+#define RCC_EP_DEV0_3_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK 0x0000FF00L
+//RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK 0x00040000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x01000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK 0x02000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK 0x04000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK 0x08000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK 0x10000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK 0x20000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK 0x40000000L
+#define RCC_EP_DEV0_3_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK 0x80000000L
+//RCC_EP_DEV0_3_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK 0x00000200L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK 0x00200000L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK 0x00400000L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK 0x01000000L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK 0x02000000L
+#define RCC_EP_DEV0_3_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK 0x04000000L
+//RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_EP_DEV0_3_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1
+//RCC_DWN_DEV0_3_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_3_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0
+#define RCC_DWN_DEV0_3_DN_PCIE_RESERVED__PCIE_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_3_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_3_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0
+#define RCC_DWN_DEV0_3_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK 0xFFFFFFFFL
+//RCC_DWN_DEV0_3_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0
+#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7
+#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e
+#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK 0x00000001L
+#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK 0x00000080L
+#define RCC_DWN_DEV0_3_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK 0x40000000L
+//RCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19
+#define RCC_DWN_DEV0_3_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK 0x06000000L
+//RCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c
+#define RCC_DWN_DEV0_3_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK 0x70000000L
+//RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7
+#define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8
+#define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK 0x00000080L
+#define RCC_DWN_DEV0_3_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK 0x00000100L
+//RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT 0x3
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK 0x00000001L
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK 0x00000002L
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK 0x00000004L
+#define RCC_DWN_DEV0_3_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK 0x00000008L
+//RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK 0x00000001L
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK 0x00020000L
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK 0x00E00000L
+//RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK 0x01000000L
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK 0x20000000L
+//RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2
+#define RCC_DWN_DEV0_3_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK 0x00000004L
+
+
+// addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1
+//RCC_DWNP_DEV0_3_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK 0x00000700L
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK 0x00000800L
+#define RCC_DWNP_DEV0_3_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK 0x00020000L
+//RCC_DWNP_DEV0_3_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK 0x00000100L
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK 0x00000200L
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK 0x00100000L
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK 0x00200000L
+#define RCC_DWNP_DEV0_3_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0
+#define RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1
+#define RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT 0x2
+#define RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK 0x00000001L
+#define RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK 0x00000002L
+#define RCC_DWNP_DEV0_3_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK 0x00000004L
+//RCC_DWNP_DEV0_3_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT 0x0
+#define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b
+#define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK 0x00000001L
+#define RCC_DWNP_DEV0_3_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK 0x08000000L
+//RCC_DWNP_DEV0_3_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_3_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa
+#define RCC_DWNP_DEV0_3_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK 0x00000400L
+//RCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0
+#define RCC_DWNP_DEV0_3_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975]
+//RCC_DEV0_EPF0_1_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_1_RCC_ERR_LOG_1
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_1__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_1__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_1__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_1__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_1_RCC_ERR_LOG_2
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_2__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_2__DOORBELL_READ_ACCESS_STATUS__SHIFT 0x1
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_2__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK 0x00000001L
+#define RCC_DEV0_EPF0_1_RCC_ERR_LOG_2__DOORBELL_READ_ACCESS_STATUS_MASK 0x00000002L
+//RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_1
+#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_1__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_1__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_2
+#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_2__BIF_DOORBELL_APER_EN__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_DOORBELL_APER_EN_2__BIF_DOORBELL_APER_EN_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_1
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_1__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_1__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_2
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_2__CONFIG_MEMSIZE__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_MEMSIZE_2__CONFIG_MEMSIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_1
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_1__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_1__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_2
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_2__CONFIG_RESERVED__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_CONFIG_RESERVED_2__CONFIG_RESERVED_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000L
+//RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_1__IOV_ENABLE_MASK 0x80000000L
+//RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2__FUNC_IDENTIFIER__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2__IOV_ENABLE__SHIFT 0x1f
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2__FUNC_IDENTIFIER_MASK 0x00000001L
+#define RCC_DEV0_EPF0_1_RCC_IOV_FUNC_IDENTIFIER_2__IOV_ENABLE_MASK 0x80000000L
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1
+//RCC_DEV0_2_RCC_ERR_INT_CNTL
+#define RCC_DEV0_2_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT 0x0
+#define RCC_DEV0_2_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK 0x00000001L
+//RCC_DEV0_2_RCC_BACO_CNTL_MISC
+#define RCC_DEV0_2_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0
+#define RCC_DEV0_2_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1
+#define RCC_DEV0_2_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK 0x00000002L
+//RCC_DEV0_2_RCC_RESET_EN
+#define RCC_DEV0_2_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf
+#define RCC_DEV0_2_RCC_RESET_EN__DB_APER_RESET_EN_MASK 0x00008000L
+//RCC_DEV0_3_RCC_VDM_SUPPORT
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK 0x00000001L
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK 0x00000002L
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK 0x00000004L
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK 0x00000008L
+#define RCC_DEV0_3_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK 0x00000010L
+//RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT 0x0
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT 0x1
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT 0x2
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT 0x3
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT 0x4
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT 0x5
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT 0xb
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT 0x12
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT 0x19
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK 0x00000001L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK 0x00000002L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK 0x00000004L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK 0x00000008L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK 0x00000010L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK 0x000007E0L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK 0x0003F800L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK 0x01FC0000L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK 0xFE000000L
+//RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT 0x0
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT 0x6
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT 0xc
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT 0x11
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK 0x0000003FL
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK 0x00000FC0L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK 0x0001F000L
+#define RCC_DEV0_3_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK 0x00FE0000L
+//RCC_DEV0_2_RCC_GPUIOV_REGION
+#define RCC_DEV0_2_RCC_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define RCC_DEV0_2_RCC_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define RCC_DEV0_2_RCC_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define RCC_DEV0_2_RCC_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//RCC_DEV0_2_RCC_GPU_HOSTVM_EN
+#define RCC_DEV0_2_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT 0x0
+#define RCC_DEV0_2_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK 0x00000001L
+//RCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT 0x0
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT 0x1
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK 0x00000002L
+//RCC_DEV0_2_RCC_CONSOLE_IOV_FIRST_VF_OFFSET
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//RCC_DEV0_2_RCC_CONSOLE_IOV_VF_STRIDE
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT 0x0
+#define RCC_DEV0_2_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK 0xFFFFL
+//RCC_DEV0_2_RCC_PEER_REG_RANGE0
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE0__START_ADDR_MASK 0x0000FFFFL
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE0__END_ADDR_MASK 0xFFFF0000L
+//RCC_DEV0_2_RCC_PEER_REG_RANGE1
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE1__START_ADDR_MASK 0x0000FFFFL
+#define RCC_DEV0_2_RCC_PEER_REG_RANGE1__END_ADDR_MASK 0xFFFF0000L
+//RCC_DEV0_3_RCC_BUS_CNTL
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8
+#define RCC_DEV0_3_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc
+#define RCC_DEV0_3_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15
+#define RCC_DEV0_3_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18
+#define RCC_DEV0_3_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19
+#define RCC_DEV0_3_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c
+#define RCC_DEV0_3_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_IO_DIS_MASK 0x00000004L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_MEM_DIS_MASK 0x00000008L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_BM_DIS_MASK 0x00000010L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK 0x00000020L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK 0x00000040L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK 0x00000080L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK 0x00000100L
+#define RCC_DEV0_3_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK 0x00001000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK 0x00002000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK 0x00010000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK 0x00020000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK 0x00040000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK 0x00080000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK 0x00100000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK 0x00200000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK 0x01000000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK 0x0E000000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK 0x10000000L
+#define RCC_DEV0_3_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK 0xE0000000L
+//RCC_DEV0_2_RCC_CONFIG_CNTL
+#define RCC_DEV0_2_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
+#define RCC_DEV0_2_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
+#define RCC_DEV0_2_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
+#define RCC_DEV0_2_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x00000001L
+#define RCC_DEV0_2_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x00000004L
+#define RCC_DEV0_2_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK 0x00000018L
+//RCC_DEV0_2_RCC_CONFIG_F0_BASE
+#define RCC_DEV0_2_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
+#define RCC_DEV0_2_RCC_CONFIG_F0_BASE__F0_BASE_MASK 0xFFFFFFFFL
+//RCC_DEV0_2_RCC_CONFIG_APER_SIZE
+#define RCC_DEV0_2_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
+#define RCC_DEV0_2_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK 0xFFFFFFFFL
+//RCC_DEV0_2_RCC_CONFIG_REG_APER_SIZE
+#define RCC_DEV0_2_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
+#define RCC_DEV0_2_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0x07FFFFFFL
+//RCC_DEV0_2_RCC_XDMA_LO
+#define RCC_DEV0_2_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0
+#define RCC_DEV0_2_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f
+#define RCC_DEV0_2_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK 0x7FFFFFFFL
+#define RCC_DEV0_2_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK 0x80000000L
+//RCC_DEV0_2_RCC_XDMA_HI
+#define RCC_DEV0_2_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0
+#define RCC_DEV0_2_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK 0x7FFFFFFFL
+//RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT 0x7
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT 0x13
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK 0x00000080L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK 0x00000100L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK 0x00000200L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK 0x00000400L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK 0x00000800L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK 0x00001000L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK 0x00002000L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK 0x00004000L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK 0x00010000L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK 0x00020000L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK 0x00040000L
+#define RCC_DEV0_3_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK 0x00080000L
+//RCC_DEV0_2_RCC_BUSNUM_CNTL1
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL1__ID_MASK_MASK 0x000000FFL
+//RCC_DEV0_2_RCC_BUSNUM_LIST0
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID0__SHIFT 0x0
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID1__SHIFT 0x8
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID2__SHIFT 0x10
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID3__SHIFT 0x18
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID0_MASK 0x000000FFL
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID1_MASK 0x0000FF00L
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID2_MASK 0x00FF0000L
+#define RCC_DEV0_2_RCC_BUSNUM_LIST0__ID3_MASK 0xFF000000L
+//RCC_DEV0_2_RCC_BUSNUM_LIST1
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID4__SHIFT 0x0
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID5__SHIFT 0x8
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID6__SHIFT 0x10
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID7__SHIFT 0x18
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID4_MASK 0x000000FFL
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID5_MASK 0x0000FF00L
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID6_MASK 0x00FF0000L
+#define RCC_DEV0_2_RCC_BUSNUM_LIST1__ID7_MASK 0xFF000000L
+//RCC_DEV0_2_RCC_BUSNUM_CNTL2
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000FFL
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L
+#define RCC_DEV0_2_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L
+//RCC_DEV0_2_RCC_CAPTURE_HOST_BUSNUM
+#define RCC_DEV0_2_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0
+#define RCC_DEV0_2_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK 0x00000001L
+//RCC_DEV0_2_RCC_HOST_BUSNUM
+#define RCC_DEV0_2_RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0
+#define RCC_DEV0_2_RCC_HOST_BUSNUM__HOST_ID_MASK 0x0000FFFFL
+//RCC_DEV0_2_RCC_PEER0_FB_OFFSET_HI
+#define RCC_DEV0_2_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_2_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO
+#define RCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_2_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK 0x80000000L
+//RCC_DEV0_2_RCC_PEER1_FB_OFFSET_HI
+#define RCC_DEV0_2_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_2_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO
+#define RCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_2_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK 0x80000000L
+//RCC_DEV0_2_RCC_PEER2_FB_OFFSET_HI
+#define RCC_DEV0_2_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_2_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO
+#define RCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_2_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK 0x80000000L
+//RCC_DEV0_2_RCC_PEER3_FB_OFFSET_HI
+#define RCC_DEV0_2_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0
+#define RCC_DEV0_2_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK 0x000FFFFFL
+//RCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO
+#define RCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0
+#define RCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f
+#define RCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK 0x000FFFFFL
+#define RCC_DEV0_2_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK 0x80000000L
+//RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK 0x000000FFL
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK 0x0000FF00L
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK 0x00FF0000L
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK 0xFF000000L
+//RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK 0x000000FFL
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK 0x0000FF00L
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK 0x00FF0000L
+#define RCC_DEV0_2_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK 0xFF000000L
+//RCC_DEV0_3_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_3_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0
+#define RCC_DEV0_3_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8
+#define RCC_DEV0_3_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK 0x00000001L
+#define RCC_DEV0_3_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK 0x00000100L
+//RCC_DEV0_3_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT 0x10
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK 0x00000001L
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK 0x00000002L
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK 0x00000004L
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK 0x00000008L
+#define RCC_DEV0_3_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK 0xFFFF0000L
+//RCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0
+#define RCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8
+#define RCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK 0x000000FFL
+#define RCC_DEV0_3_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK 0x00001F00L
+//RCC_DEV0_3_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_3_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0
+#define RCC_DEV0_3_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK 0x000003FFL
+//RCC_DEV0_3_RCC_MH_ARB_CNTL
+#define RCC_DEV0_3_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0
+#define RCC_DEV0_3_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1
+#define RCC_DEV0_3_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK 0x00000001L
+#define RCC_DEV0_3_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK 0x00007FFEL
+
+
+// addressBlock: nbio_nbif0_bif_bx_BIFDEC1
+//BIF_BX2_CC_BIF_BX_STRAP0
+#define BIF_BX2_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT 0x19
+#define BIF_BX2_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK 0xFE000000L
+//BIF_BX2_CC_BIF_BX_PINSTRAP0
+//BIF_BX2_BIF_MM_INDACCESS_CNTL
+#define BIF_BX2_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
+#define BIF_BX2_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x00000002L
+//BIF_BX2_BUS_CNTL
+#define BIF_BX2_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
+#define BIF_BX2_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
+#define BIF_BX2_BUS_CNTL__SET_AZ_TC__SHIFT 0xa
+#define BIF_BX2_BUS_CNTL__SET_MC_TC__SHIFT 0xd
+#define BIF_BX2_BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
+#define BIF_BX2_BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
+#define BIF_BX2_BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
+#define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT 0x18
+#define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT 0x19
+#define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT 0x1a
+#define BIF_BX2_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT 0x1b
+#define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT 0x1c
+#define BIF_BX2_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT 0x1d
+#define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT 0x1e
+#define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT 0x1f
+#define BIF_BX2_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x00000040L
+#define BIF_BX2_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x00000080L
+#define BIF_BX2_BUS_CNTL__SET_AZ_TC_MASK 0x00001C00L
+#define BIF_BX2_BUS_CNTL__SET_MC_TC_MASK 0x0000E000L
+#define BIF_BX2_BUS_CNTL__ZERO_BE_WR_EN_MASK 0x00010000L
+#define BIF_BX2_BUS_CNTL__ZERO_BE_RD_EN_MASK 0x00020000L
+#define BIF_BX2_BUS_CNTL__RD_STALL_IO_WR_MASK 0x00040000L
+#define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK 0x01000000L
+#define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK 0x02000000L
+#define BIF_BX2_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK 0x04000000L
+#define BIF_BX2_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK 0x08000000L
+#define BIF_BX2_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK 0x10000000L
+#define BIF_BX2_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK 0x20000000L
+#define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK 0x40000000L
+#define BIF_BX2_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK 0x80000000L
+//BIF_BX2_BIF_SCRATCH0
+#define BIF_BX2_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
+#define BIF_BX2_BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xFFFFFFFFL
+//BIF_BX2_BIF_SCRATCH1
+#define BIF_BX2_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
+#define BIF_BX2_BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xFFFFFFFFL
+//BIF_BX2_BX_RESET_EN
+#define BIF_BX2_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10
+#define BIF_BX2_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK 0x00010000L
+//BIF_BX2_MM_CFGREGS_CNTL
+#define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
+#define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6
+#define BIF_BX2_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f
+#define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x00000007L
+#define BIF_BX2_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK 0x000000C0L
+#define BIF_BX2_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x80000000L
+//BIF_BX2_BX_RESET_CNTL
+#define BIF_BX2_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0
+#define BIF_BX2_BX_RESET_CNTL__LINK_TRAIN_EN_MASK 0x00000001L
+//BIF_BX2_INTERRUPT_CNTL
+#define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0
+#define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1
+#define BIF_BX2_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3
+#define BIF_BX2_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4
+#define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf
+#define BIF_BX2_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT 0x10
+#define BIF_BX2_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT 0x11
+#define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT 0x12
+#define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK 0x00000001L
+#define BIF_BX2_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK 0x00000002L
+#define BIF_BX2_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x00000008L
+#define BIF_BX2_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK 0x000000F0L
+#define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK 0x00008000L
+#define BIF_BX2_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK 0x00010000L
+#define BIF_BX2_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK 0x00020000L
+#define BIF_BX2_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK 0x00040000L
+//BIF_BX2_INTERRUPT_CNTL2
+#define BIF_BX2_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0
+#define BIF_BX2_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK 0xFFFFFFFFL
+//BIF_BX2_CLKREQB_PAD_CNTL
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK 0x00000001L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK 0x00000002L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK 0x00000004L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK 0x00000018L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK 0x00000020L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK 0x00000040L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK 0x00000080L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK 0x00000100L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK 0x00000200L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK 0x00000400L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK 0x00000800L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK 0x00001000L
+#define BIF_BX2_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK 0x00002000L
+//BIF_BX2_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT 0xb
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT 0x10
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK 0x00000001L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK 0x00000002L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK 0x00000004L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK 0x00000008L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK 0x00000800L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK 0x00001000L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK 0x00002000L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK 0x00008000L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK 0x00FF0000L
+#define BIF_BX2_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK 0x01000000L
+//BIF_BX2_BIF_DOORBELL_CNTL
+#define BIF_BX2_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0
+#define BIF_BX2_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1
+#define BIF_BX2_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2
+#define BIF_BX2_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3
+#define BIF_BX2_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b
+#define BIF_BX2_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK 0x00000001L
+#define BIF_BX2_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK 0x00000002L
+#define BIF_BX2_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK 0x00000004L
+#define BIF_BX2_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK 0x00000008L
+#define BIF_BX2_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK 0x00000010L
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK 0x01000000L
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK 0x02000000L
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK 0x04000000L
+#define BIF_BX2_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK 0x08000000L
+//BIF_BX2_BIF_DOORBELL_INT_CNTL
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT 0x1
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT 0x2
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT 0x11
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT 0x12
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT 0x19
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT 0x1a
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1c
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1d
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT 0x1e
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK 0x00000001L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK 0x00000002L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK 0x00000004L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK 0x00010000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK 0x00020000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK 0x00040000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK 0x02000000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK 0x04000000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x10000000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x20000000L
+#define BIF_BX2_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK 0x40000000L
+//BIF_BX2_BIF_FB_EN
+#define BIF_BX2_BIF_FB_EN__FB_READ_EN__SHIFT 0x0
+#define BIF_BX2_BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1
+#define BIF_BX2_BIF_FB_EN__FB_READ_EN_MASK 0x00000001L
+#define BIF_BX2_BIF_FB_EN__FB_WRITE_EN_MASK 0x00000002L
+//BIF_BX2_BIF_INTR_CNTL
+#define BIF_BX2_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT 0x0
+#define BIF_BX2_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK 0x00000001L
+//BIF_BX2_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX2_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX2_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK 0x7FFFFFFFL
+//BIF_BX2_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX2_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX2_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK 0x7FFFFFFFL
+//BIF_BX2_BACO_CNTL
+#define BIF_BX2_BACO_CNTL__BACO_EN__SHIFT 0x0
+#define BIF_BX2_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1
+#define BIF_BX2_BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2
+#define BIF_BX2_BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3
+#define BIF_BX2_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5
+#define BIF_BX2_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6
+#define BIF_BX2_BACO_CNTL__BACO_MODE__SHIFT 0x8
+#define BIF_BX2_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9
+#define BIF_BX2_BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f
+#define BIF_BX2_BACO_CNTL__BACO_EN_MASK 0x00000001L
+#define BIF_BX2_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK 0x00000002L
+#define BIF_BX2_BACO_CNTL__BACO_DUMMY_EN_MASK 0x00000004L
+#define BIF_BX2_BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L
+#define BIF_BX2_BACO_CNTL__BACO_DSTATE_BYPASS_MASK 0x00000020L
+#define BIF_BX2_BACO_CNTL__BACO_RST_INTR_MASK_MASK 0x00000040L
+#define BIF_BX2_BACO_CNTL__BACO_MODE_MASK 0x00000100L
+#define BIF_BX2_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000200L
+#define BIF_BX2_BACO_CNTL__BACO_AUTO_EXIT_MASK 0x80000000L
+//BIF_BX2_BIF_BACO_EXIT_TIME0
+#define BIF_BX2_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX2_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX2_BIF_BACO_EXIT_TIMER1
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT 0x18
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK 0x000FFFFFL
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK 0x01000000L
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK 0x04000000L
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK 0x08000000L
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK 0x10000000L
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK 0x60000000L
+#define BIF_BX2_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK 0x80000000L
+//BIF_BX2_BIF_BACO_EXIT_TIMER2
+#define BIF_BX2_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0
+#define BIF_BX2_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK 0x000FFFFFL
+//BIF_BX2_BIF_BACO_EXIT_TIMER3
+#define BIF_BX2_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX2_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX2_BIF_BACO_EXIT_TIMER4
+#define BIF_BX2_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0
+#define BIF_BX2_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK 0x000FFFFFL
+//BIF_BX2_MEM_TYPE_CNTL
+#define BIF_BX2_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0
+#define BIF_BX2_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK 0x00000001L
+//BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT 0x1
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT 0x8
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK 0x00000001L
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK 0x00000002L
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK 0x00000100L
+//BIF_BX2_NBIF_GFX_ADDR_LUT_0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_0__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_1
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_1__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_2
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_2__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_3
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_3__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_4
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_4__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_5
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_5__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_6
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_6__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_7
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_7__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_8
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_8__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_9
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_9__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_10
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_10__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_11
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_11__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_12
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_12__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_13
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_13__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_14
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_14__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_NBIF_GFX_ADDR_LUT_15
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT 0x0
+#define BIF_BX2_NBIF_GFX_ADDR_LUT_15__ADDR_MASK 0x00FFFFFFL
+//BIF_BX2_VF_REGWR_EN
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT 0x0
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT 0x1
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT 0x2
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT 0x3
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT 0x4
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT 0x5
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT 0x6
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT 0x7
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT 0x8
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT 0x9
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT 0xa
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT 0xb
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT 0xc
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT 0xd
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT 0xe
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT 0xf
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT 0x10
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT 0x11
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT 0x12
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT 0x13
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT 0x14
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT 0x15
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT 0x16
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT 0x17
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT 0x18
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT 0x19
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT 0x1a
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT 0x1b
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT 0x1c
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT 0x1d
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT 0x1e
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK 0x00000001L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK 0x00000002L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK 0x00000004L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK 0x00000008L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK 0x00000010L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK 0x00000020L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK 0x00000040L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK 0x00000080L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK 0x00000100L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK 0x00000200L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK 0x00000400L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK 0x00000800L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK 0x00001000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK 0x00002000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK 0x00004000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK 0x00008000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK 0x00010000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK 0x00020000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK 0x00040000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK 0x00080000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK 0x00100000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK 0x00200000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK 0x00400000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK 0x00800000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK 0x01000000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK 0x02000000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK 0x04000000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK 0x08000000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK 0x10000000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK 0x20000000L
+#define BIF_BX2_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK 0x40000000L
+//BIF_BX2_VF_DOORBELL_EN
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT 0x0
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT 0x1
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT 0x2
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT 0x3
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT 0x4
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT 0x5
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT 0x6
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT 0x7
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT 0x8
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT 0x9
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT 0xa
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT 0xb
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT 0xc
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT 0xd
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT 0xe
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT 0xf
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT 0x10
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT 0x11
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT 0x12
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT 0x13
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT 0x14
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT 0x15
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT 0x16
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT 0x17
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT 0x18
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT 0x19
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT 0x1a
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT 0x1b
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT 0x1c
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT 0x1d
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT 0x1e
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT 0x1f
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK 0x00000001L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK 0x00000002L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK 0x00000004L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK 0x00000008L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK 0x00000010L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK 0x00000020L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK 0x00000040L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK 0x00000080L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK 0x00000100L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK 0x00000200L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK 0x00000400L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK 0x00000800L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK 0x00001000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK 0x00002000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK 0x00004000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK 0x00008000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK 0x00010000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK 0x00020000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK 0x00040000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK 0x00080000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK 0x00100000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK 0x00200000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK 0x00400000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK 0x00800000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK 0x01000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK 0x02000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK 0x04000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK 0x08000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK 0x10000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK 0x20000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK 0x40000000L
+#define BIF_BX2_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK 0x80000000L
+//BIF_BX2_VF_FB_EN
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF0__SHIFT 0x0
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF1__SHIFT 0x1
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF2__SHIFT 0x2
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF3__SHIFT 0x3
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF4__SHIFT 0x4
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF5__SHIFT 0x5
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF6__SHIFT 0x6
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF7__SHIFT 0x7
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF8__SHIFT 0x8
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF9__SHIFT 0x9
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF10__SHIFT 0xa
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF11__SHIFT 0xb
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF12__SHIFT 0xc
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF13__SHIFT 0xd
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF14__SHIFT 0xe
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF15__SHIFT 0xf
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF16__SHIFT 0x10
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF17__SHIFT 0x11
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF18__SHIFT 0x12
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF19__SHIFT 0x13
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF20__SHIFT 0x14
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF21__SHIFT 0x15
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF22__SHIFT 0x16
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF23__SHIFT 0x17
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF24__SHIFT 0x18
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF25__SHIFT 0x19
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF26__SHIFT 0x1a
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF27__SHIFT 0x1b
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF28__SHIFT 0x1c
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF29__SHIFT 0x1d
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF30__SHIFT 0x1e
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF0_MASK 0x00000001L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF1_MASK 0x00000002L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF2_MASK 0x00000004L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF3_MASK 0x00000008L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF4_MASK 0x00000010L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF5_MASK 0x00000020L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF6_MASK 0x00000040L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF7_MASK 0x00000080L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF8_MASK 0x00000100L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF9_MASK 0x00000200L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF10_MASK 0x00000400L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF11_MASK 0x00000800L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF12_MASK 0x00001000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF13_MASK 0x00002000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF14_MASK 0x00004000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF15_MASK 0x00008000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF16_MASK 0x00010000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF17_MASK 0x00020000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF18_MASK 0x00040000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF19_MASK 0x00080000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF20_MASK 0x00100000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF21_MASK 0x00200000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF22_MASK 0x00400000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF23_MASK 0x00800000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF24_MASK 0x01000000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF25_MASK 0x02000000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF26_MASK 0x04000000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF27_MASK 0x08000000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF28_MASK 0x10000000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF29_MASK 0x20000000L
+#define BIF_BX2_VF_FB_EN__VF_FB_EN_VF30_MASK 0x40000000L
+//BIF_BX2_VF_REGWR_STATUS
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT 0x0
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT 0x1
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT 0x2
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT 0x3
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT 0x4
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT 0x5
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT 0x6
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT 0x7
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT 0x8
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT 0x9
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT 0xa
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT 0xb
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT 0xc
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT 0xd
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT 0xe
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT 0xf
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT 0x10
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT 0x11
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT 0x12
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT 0x13
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT 0x14
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT 0x15
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT 0x16
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT 0x17
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT 0x18
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT 0x19
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT 0x1a
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT 0x1b
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT 0x1c
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT 0x1d
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT 0x1e
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK 0x00000001L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK 0x00000002L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK 0x00000004L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK 0x00000008L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK 0x00000010L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK 0x00000020L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK 0x00000040L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK 0x00000080L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK 0x00000100L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK 0x00000200L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK 0x00000400L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK 0x00000800L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK 0x00001000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK 0x00002000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK 0x00004000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK 0x00008000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK 0x00010000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK 0x00020000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK 0x00040000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK 0x00080000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK 0x00100000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK 0x00200000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK 0x00400000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK 0x00800000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK 0x01000000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK 0x02000000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK 0x04000000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK 0x08000000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK 0x10000000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK 0x20000000L
+#define BIF_BX2_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK 0x40000000L
+//BIF_BX2_VF_DOORBELL_STATUS
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT 0x0
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT 0x1
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT 0x2
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT 0x3
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT 0x4
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT 0x5
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT 0x6
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT 0x7
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT 0x8
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT 0x9
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT 0xa
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT 0xb
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT 0xc
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT 0xd
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT 0xe
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT 0xf
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT 0x10
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT 0x11
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT 0x12
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT 0x13
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT 0x14
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT 0x15
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT 0x16
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT 0x17
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT 0x18
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT 0x19
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT 0x1a
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT 0x1b
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT 0x1c
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT 0x1d
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT 0x1e
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK 0x00000001L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK 0x00000002L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK 0x00000004L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK 0x00000008L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK 0x00000010L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK 0x00000020L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK 0x00000040L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK 0x00000080L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK 0x00000100L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK 0x00000200L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK 0x00000400L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK 0x00000800L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK 0x00001000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK 0x00002000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK 0x00004000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK 0x00008000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK 0x00010000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK 0x00020000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK 0x00040000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK 0x00080000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK 0x00100000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK 0x00200000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK 0x00400000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK 0x00800000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK 0x01000000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK 0x02000000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK 0x04000000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK 0x08000000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK 0x10000000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK 0x20000000L
+#define BIF_BX2_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK 0x40000000L
+//BIF_BX2_VF_FB_STATUS
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT 0x0
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT 0x1
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT 0x2
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT 0x3
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT 0x4
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT 0x5
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT 0x6
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT 0x7
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT 0x8
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT 0x9
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT 0xa
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT 0xb
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT 0xc
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT 0xd
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT 0xe
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT 0xf
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT 0x10
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT 0x11
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT 0x12
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT 0x13
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT 0x14
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT 0x15
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT 0x16
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT 0x17
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT 0x18
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT 0x19
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT 0x1a
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT 0x1b
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT 0x1c
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT 0x1d
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT 0x1e
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK 0x00000001L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK 0x00000002L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK 0x00000004L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK 0x00000008L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK 0x00000010L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK 0x00000020L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK 0x00000040L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK 0x00000080L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK 0x00000100L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK 0x00000200L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK 0x00000400L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK 0x00000800L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK 0x00001000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK 0x00002000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK 0x00004000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK 0x00008000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK 0x00010000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK 0x00020000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK 0x00040000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK 0x00080000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK 0x00100000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK 0x00200000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK 0x00400000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK 0x00800000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK 0x01000000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK 0x02000000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK 0x04000000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK 0x08000000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK 0x10000000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK 0x20000000L
+#define BIF_BX2_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK 0x40000000L
+//BIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX2_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX2_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX2_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2
+#define BIF_BX2_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK 0x0007FFFCL
+//BIF_BX2_BIF_RB_CNTL
+#define BIF_BX2_BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0
+#define BIF_BX2_BIF_RB_CNTL__RB_SIZE__SHIFT 0x1
+#define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8
+#define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9
+#define BIF_BX2_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11
+#define BIF_BX2_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT 0x1a
+#define BIF_BX2_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT 0x1d
+#define BIF_BX2_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT 0x1e
+#define BIF_BX2_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f
+#define BIF_BX2_BIF_RB_CNTL__RB_ENABLE_MASK 0x00000001L
+#define BIF_BX2_BIF_RB_CNTL__RB_SIZE_MASK 0x0000003EL
+#define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L
+#define BIF_BX2_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x00003E00L
+#define BIF_BX2_BIF_RB_CNTL__BIF_RB_TRAN_MASK 0x00020000L
+#define BIF_BX2_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK 0x1C000000L
+#define BIF_BX2_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK 0x20000000L
+#define BIF_BX2_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK 0x40000000L
+#define BIF_BX2_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L
+//BIF_BX2_BIF_RB_BASE
+#define BIF_BX2_BIF_RB_BASE__ADDR__SHIFT 0x0
+#define BIF_BX2_BIF_RB_BASE__ADDR_MASK 0xFFFFFFFFL
+//BIF_BX2_BIF_RB_RPTR
+#define BIF_BX2_BIF_RB_RPTR__OFFSET__SHIFT 0x2
+#define BIF_BX2_BIF_RB_RPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX2_BIF_RB_WPTR
+#define BIF_BX2_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0
+#define BIF_BX2_BIF_RB_WPTR__OFFSET__SHIFT 0x2
+#define BIF_BX2_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK 0x00000001L
+#define BIF_BX2_BIF_RB_WPTR__OFFSET_MASK 0x0003FFFCL
+//BIF_BX2_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX2_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0
+#define BIF_BX2_BIF_RB_WPTR_ADDR_HI__ADDR_MASK 0x000000FFL
+//BIF_BX2_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX2_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2
+#define BIF_BX2_BIF_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL
+//BIF_BX2_MAILBOX_INDEX
+#define BIF_BX2_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0
+#define BIF_BX2_MAILBOX_INDEX__MAILBOX_INDEX_MASK 0x0000001FL
+//BIF_BX2_BIF_VCN0_GPUIOV_CFG_SIZE
+#define BIF_BX2_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX2_BIF_VCN0_GPUIOV_CFG_SIZE__VCN0_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX2_BIF_VCN1_GPUIOV_CFG_SIZE
+#define BIF_BX2_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX2_BIF_VCN1_GPUIOV_CFG_SIZE__VCN1_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE
+#define BIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0
+#define BIF_BX2_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK 0x0000000FL
+//BIF_BX2_BIF_PERSTB_PAD_CNTL
+#define BIF_BX2_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX2_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK 0x0000FFFFL
+//BIF_BX2_BIF_PX_EN_PAD_CNTL
+#define BIF_BX2_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX2_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX2_BIF_REFPADKIN_PAD_CNTL
+#define BIF_BX2_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0
+#define BIF_BX2_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX2_BIF_CLKREQB_PAD_CNTL
+#define BIF_BX2_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0
+#define BIF_BX2_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK 0x00FFFFFFL
+//BIF_BX2_BIF_PWRBRK_PAD_CNTL
+#define BIF_BX2_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT 0x0
+#define BIF_BX2_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK 0x000000FFL
+//BIF_BX2_BIF_WAKEB_PAD_CNTL
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL__SHIFT 0x0
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN__SHIFT 0x1
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IPD__SHIFT 0x2
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IPU__SHIFT 0x3
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN__SHIFT 0x4
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0__SHIFT 0x5
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1__SHIFT 0x6
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED__SHIFT 0x7
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_ITXIMPSEL_MASK 0x00000001L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_ICTFEN_MASK 0x00000002L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IPD_MASK 0x00000004L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IPU_MASK 0x00000008L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IRXEN_MASK 0x00000010L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL0_MASK 0x00000020L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_IRXSEL1_MASK 0x00000040L
+#define BIF_BX2_BIF_WAKEB_PAD_CNTL__GPIO33_RESERVED_MASK 0x00000080L
+//BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD__SHIFT 0x0
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU__SHIFT 0x1
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN__SHIFT 0x2
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0__SHIFT 0x3
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1__SHIFT 0x4
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL__SHIFT 0x5
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPD_MASK 0x00000001L
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IPU_MASK 0x00000002L
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXEN_MASK 0x00000004L
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL0_MASK 0x00000008L
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_IRXSEL1_MASK 0x00000010L
+#define BIF_BX2_BIF_VAUX_PRESENT_PAD_CNTL__GPIO_ITXIMPSEL_MASK 0x00000020L
+//BIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL
+#define BIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID__SHIFT 0x0
+#define BIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH__SHIFT 0x1
+#define BIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_VALID_MASK 0x00000001L
+#define BIF_BX2_PCIE_PAR_SAVE_RESTORE_CNTL__PCIE_PAR_SAVE_SCRATCH_MASK 0xFFFFFFFEL
+//BIF_BX2_BIF_S5_MEM_POWER_CTRL0
+#define BIF_BX2_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0__SHIFT 0x0
+#define BIF_BX2_BIF_S5_MEM_POWER_CTRL0__MEM_POWER_CTRL_S5_31_0_MASK 0xFFFFFFFFL
+//BIF_BX2_BIF_S5_MEM_POWER_CTRL1
+#define BIF_BX2_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32__SHIFT 0x0
+#define BIF_BX2_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL__SHIFT 0xa
+#define BIF_BX2_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_S5_41_32_MASK 0x000003FFL
+#define BIF_BX2_BIF_S5_MEM_POWER_CTRL1__MEM_POWER_CTRL_SEL_MASK 0x00000400L
+//BIF_BX2_BIF_S5_DUMMY_REGS
+#define BIF_BX2_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS__SHIFT 0x0
+#define BIF_BX2_BIF_S5_DUMMY_REGS__BIF_S5_DUMMY_REGS_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF2_BIF_BME_STATUS
+#define BIF_BX_PF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
+#define BIF_BX_PF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
+#define BIF_BX_PF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x00000001L
+#define BIF_BX_PF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x00010000L
+//BIF_BX_PF2_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT 0x2
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT 0x3
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT 0x12
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT 0x13
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x00000001L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x00000002L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK 0x00000004L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK 0x00000008L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x00010000L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x00020000L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK 0x00040000L
+#define BIF_BX_PF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK 0x00080000L
+//BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK 0xFFFFFFFFL
+//BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK 0xFFFFFFFFL
+//BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT 0x1
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK 0x00000001L
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK 0x00000002L
+#define BIF_BX_PF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK 0x000FFF00L
+//BIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0
+#define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK 0x00000001L
+//BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_PF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT 0x0
+#define BIF_BX_PF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK 0x00000001L
+//BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_ONLY_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF2_GPU_HDP_INVALIDATE_ONLY_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF2_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP0_MASK 0x00000001L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP1_MASK 0x00000002L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP2_MASK 0x00000004L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP3_MASK 0x00000008L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP4_MASK 0x00000010L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP5_MASK 0x00000020L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP6_MASK 0x00000040L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP7_MASK 0x00000080L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP8_MASK 0x00000100L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__CP9_MASK 0x00000200L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF2_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT 0xc
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT 0xd
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT 0xe
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT 0xf
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT 0x10
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT 0x11
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT 0x12
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT 0x13
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT 0x14
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT 0x15
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT 0x16
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT 0x17
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT 0x18
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT 0x19
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT 0x1a
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT 0x1b
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT 0x1c
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT 0x1d
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT 0x1e
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT 0x1f
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP0_MASK 0x00000001L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP1_MASK 0x00000002L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP2_MASK 0x00000004L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP3_MASK 0x00000008L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP4_MASK 0x00000010L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP5_MASK 0x00000020L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP6_MASK 0x00000040L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP7_MASK 0x00000080L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP8_MASK 0x00000100L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__CP9_MASK 0x00000200L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK 0x00000400L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK 0x00000800L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK 0x00200000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK 0x00400000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK 0x00800000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK 0x01000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK 0x02000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK 0x04000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK 0x08000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK 0x10000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK 0x20000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK 0x40000000L
+#define BIF_BX_PF2_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK 0x80000000L
+//BIF_BX_PF2_BIF_TRANS_PENDING
+#define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0
+#define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1
+#define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK 0x00000001L
+#define BIF_BX_PF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK 0x00000002L
+//BIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT 0x0
+#define BIF_BX_PF2_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK 0x00000001L
+//BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0
+#define BIF_BX_PF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK 0xFFFFFFFFL
+//BIF_BX_PF2_MAILBOX_CONTROL
+#define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0
+#define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1
+#define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8
+#define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9
+#define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK 0x00000001L
+#define BIF_BX_PF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK 0x00000002L
+#define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK 0x00000100L
+#define BIF_BX_PF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK 0x00000200L
+//BIF_BX_PF2_MAILBOX_INT_CNTL
+#define BIF_BX_PF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0
+#define BIF_BX_PF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1
+#define BIF_BX_PF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK 0x00000001L
+#define BIF_BX_PF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK 0x00000002L
+//BIF_BX_PF2_BIF_VMHV_MAILBOX
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK 0x00000001L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK 0x00000002L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK 0x00800000L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK 0x01000000L
+#define BIF_BX_PF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK 0x02000000L
+
+
+// addressBlock: nbio_nbif0_gdc_GDCDEC
+//GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN0_FAST_WRITE_RESPONSE_EN__SHIFT 0x0
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN1_FAST_WRITE_RESPONSE_EN__SHIFT 0x1
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN2_FAST_WRITE_RESPONSE_EN__SHIFT 0x2
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN3_FAST_WRITE_RESPONSE_EN__SHIFT 0x3
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__FWR_NORMAL_ARB_MODE__SHIFT 0x10
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN0_FAST_WRITE_RESPONSE_EN_MASK 0x00000001L
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN1_FAST_WRITE_RESPONSE_EN_MASK 0x00000002L
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN2_FAST_WRITE_RESPONSE_EN_MASK 0x00000004L
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__LOGAN3_FAST_WRITE_RESPONSE_EN_MASK 0x00000008L
+#define GDC1_LOGAN_FAST_WRITE_RESPONSE_CNTL__FWR_NORMAL_ARB_MODE_MASK 0x00010000L
+//GDC1_NGDC_SDP_PORT_CTRL
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0
+#define GDC1_NGDC_SDP_PORT_CTRL__NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN__SHIFT 0xf
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT 0x10
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK 0x000000FFL
+#define GDC1_NGDC_SDP_PORT_CTRL__NGDC_OBFF_HW_URGENT_EARLY_WAKEUP_EN_MASK 0x00008000L
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK 0x000F0000L
+//GDC1_SHUB_REGS_IF_CTL
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK 0x00000001L
+//GDC1_NGDC_MP4SDP_CTRL
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN__SHIFT 0x0
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL__SHIFT 0x1
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN__SHIFT 0x4
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL__SHIFT 0x5
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN__SHIFT 0x8
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL__SHIFT 0x9
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN_MASK 0x00000001L
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL_MASK 0x00000006L
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN_MASK 0x00000010L
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL_MASK 0x00000060L
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN_MASK 0x00000100L
+#define GDC1_NGDC_MP4SDP_CTRL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL_MASK 0x00000600L
+//GDC1_NGDC_MGCG_CTRL
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT 0xa
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT 0xb
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT 0xc
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT 0xd
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK 0x00000001L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK 0x00000002L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK 0x000003FCL
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK 0x00000400L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK 0x00000800L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK 0x00001000L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK 0x00002000L
+//GDC1_NGDC_RESERVED_0
+#define GDC1_NGDC_RESERVED_0__RESERVED__SHIFT 0x0
+#define GDC1_NGDC_RESERVED_0__RESERVED_MASK 0xFFFFFFFFL
+//GDC1_NGDC_RESERVED_1
+#define GDC1_NGDC_RESERVED_1__RESERVED__SHIFT 0x0
+#define GDC1_NGDC_RESERVED_1__RESERVED_MASK 0xFFFFFFFFL
+//GDC1_NGDC_SDP_PORT_CTRL_SOCCLK
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT 0x0
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_POOL_NUM_SOCCLK__SHIFT 0x8
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC0_RSV__SHIFT 0x10
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC5_RSV__SHIFT 0x14
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC6_RSV__SHIFT 0x18
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_H__SHIFT 0x1c
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK 0x000000FFL
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_POOL_NUM_SOCCLK_MASK 0x0000FF00L
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC0_RSV_MASK 0x000F0000L
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC5_RSV_MASK 0x00F00000L
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__ATDMA_RDRSP_CRDT_VC6_RSV_MASK 0x0F000000L
+#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_H_MASK 0xF0000000L
+//GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC0_RSV__SHIFT 0x0
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC1_RSV__SHIFT 0x4
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC5_RSV__SHIFT 0x8
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC6_RSV__SHIFT 0xc
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC0_RSV__SHIFT 0x10
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC1_RSV__SHIFT 0x14
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC0_RSV_MASK 0x0000000FL
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC1_RSV_MASK 0x000000F0L
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC5_RSV_MASK 0x00000F00L
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_REQ_CRDT_VC6_RSV_MASK 0x0000F000L
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC0_RSV_MASK 0x000F0000L
+#define GDC1_NGDC_SDP_PORT_CTRL1_SOCCLK__ATDMA_ORIGDATA_CRDT_VC1_RSV_MASK 0x00F00000L
+//GDC1_NBIF_GFX_DOORBELL_STATUS
+#define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT 0x0
+#define GDC1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK 0x00000001L
+//GDC1_BIF_SDMA0_DOORBELL_RANGE
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_SDMA1_DOORBELL_RANGE
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_IH_DOORBELL_RANGE
+#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_VCN0_DOORBELL_RANGE
+#define GDC1_BIF_VCN0_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_VCN0_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_VCN0_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_VCN0_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_RLC_DOORBELL_RANGE
+#define GDC1_BIF_RLC_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_RLC_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_RLC_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_RLC_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_SDMA2_DOORBELL_RANGE
+#define GDC1_BIF_SDMA2_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_SDMA2_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_SDMA2_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_SDMA2_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_SDMA3_DOORBELL_RANGE
+#define GDC1_BIF_SDMA3_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_SDMA3_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_SDMA3_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_SDMA3_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_VCN1_DOORBELL_RANGE
+#define GDC1_BIF_VCN1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_VCN1_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_VCN1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_VCN1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_SDMA4_DOORBELL_RANGE
+#define GDC1_BIF_SDMA4_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_SDMA4_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_SDMA4_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_SDMA4_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_BIF_SDMA5_DOORBELL_RANGE
+#define GDC1_BIF_SDMA5_DOORBELL_RANGE__OFFSET__SHIFT 0x2
+#define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE__SHIFT 0x10
+#define GDC1_BIF_SDMA5_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
+#define GDC1_BIF_SDMA5_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
+//GDC1_ATDMA_MISC_CNTL
+#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE__SHIFT 0x0
+#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN__SHIFT 0x1
+#define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE__SHIFT 0x2
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT__SHIFT 0x8
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT__SHIFT 0x10
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT__SHIFT 0x18
+#define GDC1_ATDMA_MISC_CNTL__WRR_ARB_MODE_MASK 0x00000001L
+#define GDC1_ATDMA_MISC_CNTL__INSERT_RD_ON_2ND_WDAT_EN_MASK 0x00000002L
+#define GDC1_ATDMA_MISC_CNTL__RDRSP_ARB_MODE_MASK 0x0000000CL
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC6_WEIGHT_MASK 0x0000FF00L
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC0_WEIGHT_MASK 0x00FF0000L
+#define GDC1_ATDMA_MISC_CNTL__WRR_VC1_WEIGHT_MASK 0xFF000000L
+//GDC1_BIF_DOORBELL_FENCE_CNTL
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE__SHIFT 0x0
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE__SHIFT 0x1
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE__SHIFT 0x2
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE__SHIFT 0x4
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE__SHIFT 0x5
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE__SHIFT 0x6
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE__SHIFT 0x7
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE__SHIFT 0x8
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT 0x10
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_CP_ENABLE_MASK 0x00000001L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA0_ENABLE_MASK 0x00000002L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA1_ENABLE_MASK 0x00000004L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_RLC_ENABLE_MASK 0x00000010L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA2_ENABLE_MASK 0x00000020L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA3_ENABLE_MASK 0x00000040L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA4_ENABLE_MASK 0x00000080L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_SDMA5_ENABLE_MASK 0x00000100L
+#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK 0x00010000L
+//GDC1_S2A_MISC_CNTL
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS__SHIFT 0x5
+#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT 0x8
+#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT 0xa
+#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT 0xc
+#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT 0x10
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS__SHIFT 0x18
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS__SHIFT 0x19
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS__SHIFT 0x1a
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS__SHIFT 0x1b
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK 0x00000001L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK 0x00000002L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK 0x00000004L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_RLC_DIS_MASK 0x00000020L
+#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK 0x00000300L
+#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK 0x00000C00L
+#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK 0x00003000L
+#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK 0x000F0000L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA2_DIS_MASK 0x01000000L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA3_DIS_MASK 0x02000000L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA4_DIS_MASK 0x04000000L
+#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA5_DIS_MASK 0x08000000L
+//GDC1_NGDC_EARLY_WAKEUP_CTRL
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT 0x0
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT 0x1
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT 0x2
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK 0x00000001L
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK 0x00000002L
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK 0x00000004L
+//GDC1_NGDC_PG_MISC_CTRL
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY__SHIFT 0xa
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1__SHIFT 0xd
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS__SHIFT 0xe
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2__SHIFT 0x10
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT 0x18
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE__SHIFT 0x1f
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_ENDP_D3_ONLY_MASK 0x00000400L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM1_MASK 0x00002000L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_DS_ALLOW_DIS_MASK 0x00004000L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_PG_CLK_PERM2_MASK 0x00010000L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_REFCLK_CYCLE_FOR_200NS_MASK 0x3F000000L
+#define GDC1_NGDC_PG_MISC_CTRL__NGDC_CFG_PG_EXIT_OVERRIDE_MASK 0x80000000L
+//GDC1_NGDC_PGMST_CTRL
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS__SHIFT 0x0
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN__SHIFT 0x8
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN__SHIFT 0xa
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN__SHIFT 0xe
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_HYSTERESIS_MASK 0x000000FFL
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_PG_EN_MASK 0x00000100L
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_IDLENESS_COUNT_EN_MASK 0x00003C00L
+#define GDC1_NGDC_PGMST_CTRL__NGDC_CFG_FW_PG_EXIT_EN_MASK 0x0000C000L
+//GDC1_NGDC_PGSLV_CTRL
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT 0x0
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT 0x5
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS__SHIFT 0xa
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_2_IDLE_HYSTERESIS__SHIFT 0xf
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_3_IDLE_HYSTERESIS__SHIFT 0x14
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK 0x0000001FL
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK 0x000003E0L
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_GDCCLK_IDLE_HYSTERESIS_MASK 0x00007C00L
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_2_IDLE_HYSTERESIS_MASK 0x000F8000L
+#define GDC1_NGDC_PGSLV_CTRL__NGDC_CFG_SHUBCLK_3_IDLE_HYSTERESIS_MASK 0x01F00000L
+//GDC1_SHUBCLK_DPM_CTRL
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_MODE__SHIFT 0x0
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_ENABLE__SHIFT 0x1
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMAWR_QUANT__SHIFT 0x2
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMARD_QUANT__SHIFT 0xa
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_CLEAR__SHIFT 0x12
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_MODE_MASK 0x00000001L
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_ENABLE_MASK 0x00000002L
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMAWR_QUANT_MASK 0x000003FCL
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_DMARD_QUANT_MASK 0x0003FC00L
+#define GDC1_SHUBCLK_DPM_CTRL__SHUBCLK_DPM_CLEAR_MASK 0x00040000L
+//GDC1_SHUBCLK_DPM_WR_WEIGHT
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_4B__SHIFT 0x0
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_8B__SHIFT 0x5
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_16B__SHIFT 0xa
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_32B__SHIFT 0xf
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_64B__SHIFT 0x14
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_4B_MASK 0x0000001FL
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_8B_MASK 0x000003E0L
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_16B_MASK 0x00007C00L
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_32B_MASK 0x000F8000L
+#define GDC1_SHUBCLK_DPM_WR_WEIGHT__SHUBCLK_DPM_WR_WEIGHT_64B_MASK 0x01F00000L
+//GDC1_SHUBCLK_DPM_RD_WEIGHT
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_4B__SHIFT 0x0
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_8B__SHIFT 0x5
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_16B__SHIFT 0xa
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_32B__SHIFT 0xf
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_64B__SHIFT 0x14
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_4B_MASK 0x0000001FL
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_8B_MASK 0x000003E0L
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_16B_MASK 0x00007C00L
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_32B_MASK 0x000F8000L
+#define GDC1_SHUBCLK_DPM_RD_WEIGHT__SHUBCLK_DPM_RD_WEIGHT_64B_MASK 0x01F00000L
+//GDC1_SHUBCLK_DPM_WR_CNT
+#define GDC1_SHUBCLK_DPM_WR_CNT__SHUBCLK_DPM_WR_COUNTER__SHIFT 0x0
+#define GDC1_SHUBCLK_DPM_WR_CNT__SHUBCLK_DPM_WR_COUNTER_MASK 0xFFFFFFFFL
+//GDC1_SHUBCLK_DPM_RD_CNT
+#define GDC1_SHUBCLK_DPM_RD_CNT__SHUBCLK_DPM_RD_COUNTER__SHIFT 0x0
+#define GDC1_SHUBCLK_DPM_RD_CNT__SHUBCLK_DPM_RD_COUNTER_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_1__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_1__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_2__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_LO_2__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_1__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_1__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_2__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_ADDR_HI_2__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_1__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_1__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_2__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_MSG_DATA_2__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_1__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_1__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_2__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT0_CONTROL_2__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_1__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_1__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_2__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_LO_2__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_1__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_1__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_2__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_ADDR_HI_2__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_1__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_1__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_2__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_MSG_DATA_2__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_1__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_1__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_2__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT1_CONTROL_2__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_1__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_1__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_2__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_LO_2__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_1__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_1__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_2__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_ADDR_HI_2__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_1__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_1__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_2__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_MSG_DATA_2__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_1__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_1__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_2__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT2_CONTROL_2__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_1__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_1__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_2__MSG_ADDR_LO__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_LO_2__MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_1__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_1__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_2__MSG_ADDR_HI__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_ADDR_HI_2__MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_1__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_1__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_2__MSG_DATA__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_MSG_DATA_2__MSG_DATA_MASK 0xFFFFFFFFL
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_1__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_1__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_2__MASK_BIT__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_VECT3_CONTROL_2__MASK_BIT_MASK 0x00000001L
+//RCC_DEV0_EPF0_1_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK 0x00000008L
+//RCC_DEV0_EPF0_1_GFXMSIX_PBA_1
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_1__MSIX_PENDING_BITS_3_MASK 0x00000008L
+//RCC_DEV0_EPF0_1_GFXMSIX_PBA_2
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_0__SHIFT 0x0
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_1__SHIFT 0x1
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_2__SHIFT 0x2
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_3__SHIFT 0x3
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_0_MASK 0x00000001L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_1_MASK 0x00000002L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_2_MASK 0x00000004L
+#define RCC_DEV0_EPF0_1_GFXMSIX_PBA_2__MSIX_PENDING_BITS_3_MASK 0x00000008L
+
+
+// addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec
+
+
+
+
+
+
+
+
+// addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec
+
+
+// addressBlock: nbio_pcie0_bifplr0_cfgdecp
+//BIFPLR0_1_VENDOR_ID
+#define BIFPLR0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR0_1_DEVICE_ID
+#define BIFPLR0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR0_1_COMMAND
+#define BIFPLR0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR0_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR0_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR0_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR0_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR0_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR0_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR0_1_STATUS
+#define BIFPLR0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR0_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR0_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR0_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR0_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR0_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR0_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR0_1_REVISION_ID
+#define BIFPLR0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR0_1_PROG_INTERFACE
+#define BIFPLR0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR0_1_SUB_CLASS
+#define BIFPLR0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR0_1_BASE_CLASS
+#define BIFPLR0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR0_1_CACHE_LINE
+#define BIFPLR0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR0_1_LATENCY
+#define BIFPLR0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR0_1_HEADER
+#define BIFPLR0_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR0_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR0_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR0_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR0_1_BIST
+#define BIFPLR0_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR0_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR0_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR0_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR0_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR0_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR0_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR0_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR0_1_IO_BASE_LIMIT
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR0_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR0_1_SECONDARY_STATUS
+#define BIFPLR0_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR0_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR0_1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR0_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR0_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR0_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR0_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR0_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR0_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR0_1_MEM_BASE_LIMIT
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR0_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR0_1_PREF_BASE_LIMIT
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR0_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR0_1_PREF_BASE_UPPER
+#define BIFPLR0_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR0_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PREF_LIMIT_UPPER
+#define BIFPLR0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR0_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR0_1_IO_BASE_LIMIT_HI
+#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR0_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR0_1_CAP_PTR
+#define BIFPLR0_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR0_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR0_1_ROM_BASE_ADDR
+#define BIFPLR0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_INTERRUPT_LINE
+#define BIFPLR0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR0_1_INTERRUPT_PIN
+#define BIFPLR0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR0_1_IRQ_BRIDGE_CNTL
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR0_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR0_1_EXT_BRIDGE_CNTL
+#define BIFPLR0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR0_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR0_1_VENDOR_CAP_LIST
+#define BIFPLR0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR0_1_ADAPTER_ID_W
+#define BIFPLR0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR0_1_PMI_CAP_LIST
+#define BIFPLR0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_1_PMI_CAP
+#define BIFPLR0_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR0_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR0_1_PMI_STATUS_CNTL
+#define BIFPLR0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR0_1_PCIE_CAP_LIST
+#define BIFPLR0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_1_PCIE_CAP
+#define BIFPLR0_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR0_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR0_1_DEVICE_CAP
+#define BIFPLR0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR0_1_DEVICE_CNTL
+#define BIFPLR0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR0_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR0_1_DEVICE_STATUS
+#define BIFPLR0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR0_1_LINK_CAP
+#define BIFPLR0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR0_1_LINK_CNTL
+#define BIFPLR0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR0_1_LINK_STATUS
+#define BIFPLR0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR0_1_SLOT_CAP
+#define BIFPLR0_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR0_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR0_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR0_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR0_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR0_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR0_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR0_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR0_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR0_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR0_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR0_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR0_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR0_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR0_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR0_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR0_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR0_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR0_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR0_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR0_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR0_1_SLOT_CNTL
+#define BIFPLR0_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR0_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR0_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR0_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR0_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR0_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR0_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR0_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR0_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR0_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR0_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR0_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR0_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR0_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR0_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR0_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR0_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR0_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR0_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR0_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR0_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR0_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR0_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR0_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR0_1_SLOT_STATUS
+#define BIFPLR0_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR0_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR0_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR0_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR0_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR0_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR0_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR0_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR0_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR0_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR0_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR0_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR0_1_ROOT_CNTL
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR0_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR0_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR0_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR0_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR0_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR0_1_ROOT_CAP
+#define BIFPLR0_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR0_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR0_1_ROOT_STATUS
+#define BIFPLR0_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR0_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR0_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR0_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR0_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR0_1_DEVICE_CAP2
+#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR0_1_DEVICE_CNTL2
+#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR0_1_DEVICE_STATUS2
+#define BIFPLR0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_1_LINK_CAP2
+#define BIFPLR0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR0_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR0_1_LINK_CNTL2
+#define BIFPLR0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR0_1_LINK_STATUS2
+#define BIFPLR0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR0_1_SLOT_CAP2
+#define BIFPLR0_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR0_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_1_SLOT_CNTL2
+#define BIFPLR0_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR0_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_1_SLOT_STATUS2
+#define BIFPLR0_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR0_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR0_1_MSI_CAP_LIST
+#define BIFPLR0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_1_MSI_MSG_CNTL
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR0_1_MSI_MSG_ADDR_LO
+#define BIFPLR0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR0_1_MSI_MSG_ADDR_HI
+#define BIFPLR0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_1_MSI_MSG_DATA
+#define BIFPLR0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR0_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR0_1_MSI_MSG_DATA_64
+#define BIFPLR0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR0_1_SSID_CAP_LIST
+#define BIFPLR0_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_1_SSID_CAP
+#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR0_1_MSI_MAP_CAP_LIST
+#define BIFPLR0_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR0_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR0_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR0_1_MSI_MAP_CAP
+#define BIFPLR0_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR0_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR0_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR0_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR0_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR0_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR0_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_1_PCIE_PORT_VC_CNTL
+#define BIFPLR0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR0_1_PCIE_PORT_VC_STATUS
+#define BIFPLR0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR0_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR0_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR0_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR0_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR0_1_PCIE_CORR_ERR_MASK
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR0_1_PCIE_HDR_LOG0
+#define BIFPLR0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_HDR_LOG1
+#define BIFPLR0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_HDR_LOG2
+#define BIFPLR0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_HDR_LOG3
+#define BIFPLR0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR0_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR0_1_PCIE_ERR_SRC_ID
+#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR0_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_LINK_CNTL3
+#define BIFPLR0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR0_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_ACS_CAP
+#define BIFPLR0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR0_1_PCIE_ACS_CNTL
+#define BIFPLR0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR0_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_MC_CAP
+#define BIFPLR0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR0_1_PCIE_MC_CNTL
+#define BIFPLR0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR0_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR0_1_PCIE_MC_ADDR0
+#define BIFPLR0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR0_1_PCIE_MC_ADDR1
+#define BIFPLR0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_RCV0
+#define BIFPLR0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_RCV1
+#define BIFPLR0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR0_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR0_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR0_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_DPC_CAP_LIST
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR0_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR0_1_PCIE_DPC_CNTL
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR0_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR0_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR0_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR0_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR0_1_PCIE_DPC_STATUS
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR0_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR0_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR0_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_STATUS
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_MASK
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_ESM_CAP_LIST
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_ESM_HEADER_1
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_ESM_HEADER_2
+#define BIFPLR0_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR0_1_PCIE_ESM_STATUS
+#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR0_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR0_1_PCIE_ESM_CTRL
+#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR0_1_PCIE_ESM_CAP_1
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_2
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_3
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR0_1_PCIE_ESM_CAP_4
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_5
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_6
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR0_1_PCIE_ESM_CAP_7
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR0_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR0_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_LINK_CAP_16GT
+#define BIFPLR0_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR0_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_1_LINK_CNTL_16GT
+#define BIFPLR0_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR0_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_1_LINK_STATUS_16GT
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR0_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR0_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_MARGINING_PORT_CAP
+#define BIFPLR0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR0_1_MARGINING_PORT_STATUS
+#define BIFPLR0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR0_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR0_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR0_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR0_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_CCIX_HEADER_1
+#define BIFPLR0_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR0_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR0_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR0_1_PCIE_CCIX_HEADER_2
+#define BIFPLR0_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR0_1_PCIE_CCIX_CAP
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR0_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR0_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR0_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR0_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR0_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR0_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR0_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR0_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR0_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR0_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR0_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR0_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR0_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR0_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR0_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr1_cfgdecp
+//BIFPLR1_1_VENDOR_ID
+#define BIFPLR1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR1_1_DEVICE_ID
+#define BIFPLR1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR1_1_COMMAND
+#define BIFPLR1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR1_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR1_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR1_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR1_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR1_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR1_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR1_1_STATUS
+#define BIFPLR1_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR1_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR1_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR1_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR1_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR1_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR1_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR1_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR1_1_REVISION_ID
+#define BIFPLR1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR1_1_PROG_INTERFACE
+#define BIFPLR1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR1_1_SUB_CLASS
+#define BIFPLR1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR1_1_BASE_CLASS
+#define BIFPLR1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR1_1_CACHE_LINE
+#define BIFPLR1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR1_1_LATENCY
+#define BIFPLR1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR1_1_HEADER
+#define BIFPLR1_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR1_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR1_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR1_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR1_1_BIST
+#define BIFPLR1_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR1_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR1_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR1_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR1_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR1_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR1_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR1_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR1_1_IO_BASE_LIMIT
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR1_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR1_1_SECONDARY_STATUS
+#define BIFPLR1_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR1_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR1_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR1_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR1_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR1_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR1_1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR1_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR1_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR1_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR1_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR1_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR1_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR1_1_MEM_BASE_LIMIT
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR1_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR1_1_PREF_BASE_LIMIT
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR1_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR1_1_PREF_BASE_UPPER
+#define BIFPLR1_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR1_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PREF_LIMIT_UPPER
+#define BIFPLR1_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR1_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR1_1_IO_BASE_LIMIT_HI
+#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR1_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR1_1_CAP_PTR
+#define BIFPLR1_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR1_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR1_1_ROM_BASE_ADDR
+#define BIFPLR1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_INTERRUPT_LINE
+#define BIFPLR1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR1_1_INTERRUPT_PIN
+#define BIFPLR1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR1_1_IRQ_BRIDGE_CNTL
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR1_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR1_1_EXT_BRIDGE_CNTL
+#define BIFPLR1_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR1_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR1_1_VENDOR_CAP_LIST
+#define BIFPLR1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR1_1_ADAPTER_ID_W
+#define BIFPLR1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR1_1_PMI_CAP_LIST
+#define BIFPLR1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_1_PMI_CAP
+#define BIFPLR1_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR1_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR1_1_PMI_STATUS_CNTL
+#define BIFPLR1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR1_1_PCIE_CAP_LIST
+#define BIFPLR1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_1_PCIE_CAP
+#define BIFPLR1_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR1_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR1_1_DEVICE_CAP
+#define BIFPLR1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR1_1_DEVICE_CNTL
+#define BIFPLR1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR1_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR1_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR1_1_DEVICE_STATUS
+#define BIFPLR1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR1_1_LINK_CAP
+#define BIFPLR1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR1_1_LINK_CNTL
+#define BIFPLR1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR1_1_LINK_STATUS
+#define BIFPLR1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR1_1_SLOT_CAP
+#define BIFPLR1_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR1_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR1_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR1_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR1_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR1_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR1_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR1_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR1_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR1_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR1_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR1_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR1_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR1_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR1_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR1_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR1_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR1_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR1_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR1_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR1_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR1_1_SLOT_CNTL
+#define BIFPLR1_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR1_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR1_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR1_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR1_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR1_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR1_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR1_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR1_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR1_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR1_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR1_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR1_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR1_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR1_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR1_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR1_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR1_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR1_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR1_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR1_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR1_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR1_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR1_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR1_1_SLOT_STATUS
+#define BIFPLR1_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR1_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR1_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR1_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR1_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR1_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR1_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR1_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR1_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR1_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR1_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR1_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR1_1_ROOT_CNTL
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR1_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR1_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR1_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR1_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR1_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR1_1_ROOT_CAP
+#define BIFPLR1_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR1_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR1_1_ROOT_STATUS
+#define BIFPLR1_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR1_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR1_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR1_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR1_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR1_1_DEVICE_CAP2
+#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR1_1_DEVICE_CNTL2
+#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR1_1_DEVICE_STATUS2
+#define BIFPLR1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_1_LINK_CAP2
+#define BIFPLR1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR1_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR1_1_LINK_CNTL2
+#define BIFPLR1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR1_1_LINK_STATUS2
+#define BIFPLR1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR1_1_SLOT_CAP2
+#define BIFPLR1_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR1_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_1_SLOT_CNTL2
+#define BIFPLR1_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR1_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_1_SLOT_STATUS2
+#define BIFPLR1_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR1_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR1_1_MSI_CAP_LIST
+#define BIFPLR1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_1_MSI_MSG_CNTL
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR1_1_MSI_MSG_ADDR_LO
+#define BIFPLR1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR1_1_MSI_MSG_ADDR_HI
+#define BIFPLR1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_1_MSI_MSG_DATA
+#define BIFPLR1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR1_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR1_1_MSI_MSG_DATA_64
+#define BIFPLR1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR1_1_SSID_CAP_LIST
+#define BIFPLR1_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_1_SSID_CAP
+#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR1_1_MSI_MAP_CAP_LIST
+#define BIFPLR1_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR1_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR1_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR1_1_MSI_MAP_CAP
+#define BIFPLR1_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR1_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR1_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR1_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR1_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR1_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR1_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_1_PCIE_PORT_VC_CNTL
+#define BIFPLR1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR1_1_PCIE_PORT_VC_STATUS
+#define BIFPLR1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR1_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR1_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR1_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR1_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR1_1_PCIE_CORR_ERR_MASK
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR1_1_PCIE_HDR_LOG0
+#define BIFPLR1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_HDR_LOG1
+#define BIFPLR1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_HDR_LOG2
+#define BIFPLR1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_HDR_LOG3
+#define BIFPLR1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR1_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR1_1_PCIE_ERR_SRC_ID
+#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR1_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_LINK_CNTL3
+#define BIFPLR1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR1_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_ACS_CAP
+#define BIFPLR1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR1_1_PCIE_ACS_CNTL
+#define BIFPLR1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR1_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_MC_CAP
+#define BIFPLR1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR1_1_PCIE_MC_CNTL
+#define BIFPLR1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR1_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR1_1_PCIE_MC_ADDR0
+#define BIFPLR1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR1_1_PCIE_MC_ADDR1
+#define BIFPLR1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_RCV0
+#define BIFPLR1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_RCV1
+#define BIFPLR1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR1_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR1_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR1_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_DPC_CAP_LIST
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR1_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR1_1_PCIE_DPC_CNTL
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR1_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR1_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR1_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR1_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR1_1_PCIE_DPC_STATUS
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR1_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR1_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR1_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_STATUS
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_MASK
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_ESM_CAP_LIST
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_ESM_HEADER_1
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_ESM_HEADER_2
+#define BIFPLR1_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR1_1_PCIE_ESM_STATUS
+#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR1_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR1_1_PCIE_ESM_CTRL
+#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR1_1_PCIE_ESM_CAP_1
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_2
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_3
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR1_1_PCIE_ESM_CAP_4
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_5
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_6
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR1_1_PCIE_ESM_CAP_7
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR1_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR1_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_LINK_CAP_16GT
+#define BIFPLR1_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR1_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_1_LINK_CNTL_16GT
+#define BIFPLR1_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR1_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_1_LINK_STATUS_16GT
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR1_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR1_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_MARGINING_PORT_CAP
+#define BIFPLR1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR1_1_MARGINING_PORT_STATUS
+#define BIFPLR1_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR1_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR1_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR1_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR1_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR1_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_CCIX_HEADER_1
+#define BIFPLR1_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR1_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR1_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR1_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR1_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR1_1_PCIE_CCIX_HEADER_2
+#define BIFPLR1_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR1_1_PCIE_CCIX_CAP
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR1_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR1_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR1_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR1_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR1_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR1_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR1_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR1_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR1_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR1_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR1_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR1_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR1_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR1_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR1_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR1_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr2_cfgdecp
+//BIFPLR2_1_VENDOR_ID
+#define BIFPLR2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR2_1_DEVICE_ID
+#define BIFPLR2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR2_1_COMMAND
+#define BIFPLR2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR2_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR2_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR2_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR2_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR2_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR2_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR2_1_STATUS
+#define BIFPLR2_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR2_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR2_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR2_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR2_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR2_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR2_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR2_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR2_1_REVISION_ID
+#define BIFPLR2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR2_1_PROG_INTERFACE
+#define BIFPLR2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR2_1_SUB_CLASS
+#define BIFPLR2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR2_1_BASE_CLASS
+#define BIFPLR2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR2_1_CACHE_LINE
+#define BIFPLR2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR2_1_LATENCY
+#define BIFPLR2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR2_1_HEADER
+#define BIFPLR2_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR2_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR2_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR2_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR2_1_BIST
+#define BIFPLR2_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR2_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR2_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR2_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR2_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR2_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR2_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR2_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR2_1_IO_BASE_LIMIT
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR2_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR2_1_SECONDARY_STATUS
+#define BIFPLR2_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR2_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR2_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR2_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR2_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR2_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR2_1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR2_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR2_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR2_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR2_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR2_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR2_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR2_1_MEM_BASE_LIMIT
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR2_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR2_1_PREF_BASE_LIMIT
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR2_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR2_1_PREF_BASE_UPPER
+#define BIFPLR2_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR2_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PREF_LIMIT_UPPER
+#define BIFPLR2_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR2_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR2_1_IO_BASE_LIMIT_HI
+#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR2_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR2_1_CAP_PTR
+#define BIFPLR2_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR2_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR2_1_ROM_BASE_ADDR
+#define BIFPLR2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_INTERRUPT_LINE
+#define BIFPLR2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR2_1_INTERRUPT_PIN
+#define BIFPLR2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR2_1_IRQ_BRIDGE_CNTL
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR2_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR2_1_EXT_BRIDGE_CNTL
+#define BIFPLR2_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR2_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR2_1_VENDOR_CAP_LIST
+#define BIFPLR2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR2_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR2_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR2_1_ADAPTER_ID_W
+#define BIFPLR2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR2_1_PMI_CAP_LIST
+#define BIFPLR2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_1_PMI_CAP
+#define BIFPLR2_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR2_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR2_1_PMI_STATUS_CNTL
+#define BIFPLR2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR2_1_PCIE_CAP_LIST
+#define BIFPLR2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_1_PCIE_CAP
+#define BIFPLR2_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR2_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR2_1_DEVICE_CAP
+#define BIFPLR2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR2_1_DEVICE_CNTL
+#define BIFPLR2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR2_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR2_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR2_1_DEVICE_STATUS
+#define BIFPLR2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR2_1_LINK_CAP
+#define BIFPLR2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR2_1_LINK_CNTL
+#define BIFPLR2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR2_1_LINK_STATUS
+#define BIFPLR2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR2_1_SLOT_CAP
+#define BIFPLR2_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR2_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR2_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR2_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR2_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR2_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR2_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR2_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR2_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR2_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR2_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR2_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR2_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR2_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR2_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR2_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR2_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR2_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR2_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR2_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR2_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR2_1_SLOT_CNTL
+#define BIFPLR2_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR2_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR2_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR2_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR2_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR2_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR2_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR2_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR2_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR2_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR2_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR2_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR2_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR2_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR2_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR2_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR2_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR2_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR2_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR2_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR2_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR2_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR2_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR2_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR2_1_SLOT_STATUS
+#define BIFPLR2_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR2_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR2_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR2_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR2_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR2_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR2_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR2_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR2_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR2_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR2_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR2_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR2_1_ROOT_CNTL
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR2_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR2_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR2_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR2_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR2_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR2_1_ROOT_CAP
+#define BIFPLR2_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR2_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR2_1_ROOT_STATUS
+#define BIFPLR2_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR2_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR2_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR2_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR2_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR2_1_DEVICE_CAP2
+#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR2_1_DEVICE_CNTL2
+#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR2_1_DEVICE_STATUS2
+#define BIFPLR2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_1_LINK_CAP2
+#define BIFPLR2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR2_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR2_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR2_1_LINK_CNTL2
+#define BIFPLR2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR2_1_LINK_STATUS2
+#define BIFPLR2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR2_1_SLOT_CAP2
+#define BIFPLR2_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR2_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_1_SLOT_CNTL2
+#define BIFPLR2_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR2_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_1_SLOT_STATUS2
+#define BIFPLR2_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR2_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR2_1_MSI_CAP_LIST
+#define BIFPLR2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_1_MSI_MSG_CNTL
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR2_1_MSI_MSG_ADDR_LO
+#define BIFPLR2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR2_1_MSI_MSG_ADDR_HI
+#define BIFPLR2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_1_MSI_MSG_DATA
+#define BIFPLR2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR2_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR2_1_MSI_MSG_DATA_64
+#define BIFPLR2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR2_1_SSID_CAP_LIST
+#define BIFPLR2_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_1_SSID_CAP
+#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR2_1_MSI_MAP_CAP_LIST
+#define BIFPLR2_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR2_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR2_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR2_1_MSI_MAP_CAP
+#define BIFPLR2_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR2_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR2_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR2_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR2_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR2_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR2_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_1_PCIE_PORT_VC_CNTL
+#define BIFPLR2_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR2_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR2_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR2_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR2_1_PCIE_PORT_VC_STATUS
+#define BIFPLR2_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR2_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR2_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR2_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR2_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR2_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR2_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR2_1_PCIE_CORR_ERR_MASK
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR2_1_PCIE_HDR_LOG0
+#define BIFPLR2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_HDR_LOG1
+#define BIFPLR2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_HDR_LOG2
+#define BIFPLR2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_HDR_LOG3
+#define BIFPLR2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR2_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR2_1_PCIE_ERR_SRC_ID
+#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR2_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_LINK_CNTL3
+#define BIFPLR2_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR2_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR2_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_ACS_CAP
+#define BIFPLR2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR2_1_PCIE_ACS_CNTL
+#define BIFPLR2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR2_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_MC_CAP
+#define BIFPLR2_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR2_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR2_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR2_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR2_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR2_1_PCIE_MC_CNTL
+#define BIFPLR2_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR2_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR2_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR2_1_PCIE_MC_ADDR0
+#define BIFPLR2_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR2_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR2_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR2_1_PCIE_MC_ADDR1
+#define BIFPLR2_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_RCV0
+#define BIFPLR2_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_RCV1
+#define BIFPLR2_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR2_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR2_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR2_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR2_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR2_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_DPC_CAP_LIST
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR2_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR2_1_PCIE_DPC_CNTL
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR2_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR2_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR2_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR2_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR2_1_PCIE_DPC_STATUS
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR2_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR2_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR2_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_STATUS
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_MASK
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_ESM_CAP_LIST
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_ESM_HEADER_1
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_ESM_HEADER_2
+#define BIFPLR2_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR2_1_PCIE_ESM_STATUS
+#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR2_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR2_1_PCIE_ESM_CTRL
+#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR2_1_PCIE_ESM_CAP_1
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_2
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_3
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR2_1_PCIE_ESM_CAP_4
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_5
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_6
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR2_1_PCIE_ESM_CAP_7
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR2_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR2_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR2_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR2_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR2_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR2_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR2_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR2_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR2_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR2_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_LINK_CAP_16GT
+#define BIFPLR2_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR2_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_1_LINK_CNTL_16GT
+#define BIFPLR2_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR2_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_1_LINK_STATUS_16GT
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR2_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR2_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR2_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR2_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR2_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR2_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR2_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR2_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_MARGINING_PORT_CAP
+#define BIFPLR2_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR2_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR2_1_MARGINING_PORT_STATUS
+#define BIFPLR2_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR2_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR2_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR2_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR2_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR2_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR2_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR2_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR2_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_CCIX_HEADER_1
+#define BIFPLR2_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR2_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR2_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR2_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR2_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR2_1_PCIE_CCIX_HEADER_2
+#define BIFPLR2_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR2_1_PCIE_CCIX_CAP
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR2_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR2_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR2_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR2_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR2_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR2_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR2_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR2_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR2_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR2_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR2_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR2_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR2_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR2_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR2_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR2_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr3_cfgdecp
+//BIFPLR3_1_VENDOR_ID
+#define BIFPLR3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR3_1_DEVICE_ID
+#define BIFPLR3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR3_1_COMMAND
+#define BIFPLR3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR3_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR3_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR3_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR3_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR3_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR3_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR3_1_STATUS
+#define BIFPLR3_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR3_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR3_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR3_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR3_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR3_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR3_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR3_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR3_1_REVISION_ID
+#define BIFPLR3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR3_1_PROG_INTERFACE
+#define BIFPLR3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR3_1_SUB_CLASS
+#define BIFPLR3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR3_1_BASE_CLASS
+#define BIFPLR3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR3_1_CACHE_LINE
+#define BIFPLR3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR3_1_LATENCY
+#define BIFPLR3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR3_1_HEADER
+#define BIFPLR3_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR3_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR3_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR3_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR3_1_BIST
+#define BIFPLR3_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR3_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR3_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR3_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR3_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR3_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR3_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR3_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR3_1_IO_BASE_LIMIT
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR3_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR3_1_SECONDARY_STATUS
+#define BIFPLR3_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR3_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR3_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR3_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR3_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR3_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR3_1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR3_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR3_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR3_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR3_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR3_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR3_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR3_1_MEM_BASE_LIMIT
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR3_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR3_1_PREF_BASE_LIMIT
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR3_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR3_1_PREF_BASE_UPPER
+#define BIFPLR3_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR3_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PREF_LIMIT_UPPER
+#define BIFPLR3_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR3_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR3_1_IO_BASE_LIMIT_HI
+#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR3_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR3_1_CAP_PTR
+#define BIFPLR3_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR3_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR3_1_ROM_BASE_ADDR
+#define BIFPLR3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR3_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_INTERRUPT_LINE
+#define BIFPLR3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR3_1_INTERRUPT_PIN
+#define BIFPLR3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR3_1_IRQ_BRIDGE_CNTL
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR3_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR3_1_EXT_BRIDGE_CNTL
+#define BIFPLR3_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR3_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR3_1_VENDOR_CAP_LIST
+#define BIFPLR3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR3_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR3_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR3_1_ADAPTER_ID_W
+#define BIFPLR3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR3_1_PMI_CAP_LIST
+#define BIFPLR3_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_1_PMI_CAP
+#define BIFPLR3_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR3_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR3_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR3_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR3_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR3_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR3_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR3_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR3_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR3_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR3_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR3_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR3_1_PMI_STATUS_CNTL
+#define BIFPLR3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR3_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR3_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR3_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR3_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR3_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR3_1_PCIE_CAP_LIST
+#define BIFPLR3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_1_PCIE_CAP
+#define BIFPLR3_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR3_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR3_1_DEVICE_CAP
+#define BIFPLR3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR3_1_DEVICE_CNTL
+#define BIFPLR3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR3_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR3_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR3_1_DEVICE_STATUS
+#define BIFPLR3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR3_1_LINK_CAP
+#define BIFPLR3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR3_1_LINK_CNTL
+#define BIFPLR3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR3_1_LINK_STATUS
+#define BIFPLR3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR3_1_SLOT_CAP
+#define BIFPLR3_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR3_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR3_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR3_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR3_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR3_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR3_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR3_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR3_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR3_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR3_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR3_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR3_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR3_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR3_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR3_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR3_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR3_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR3_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR3_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR3_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR3_1_SLOT_CNTL
+#define BIFPLR3_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR3_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR3_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR3_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR3_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR3_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR3_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR3_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR3_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR3_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR3_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR3_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR3_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR3_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR3_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR3_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR3_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR3_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR3_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR3_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR3_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR3_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR3_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR3_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR3_1_SLOT_STATUS
+#define BIFPLR3_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR3_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR3_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR3_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR3_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR3_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR3_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR3_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR3_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR3_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR3_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR3_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR3_1_ROOT_CNTL
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR3_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR3_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR3_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR3_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR3_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR3_1_ROOT_CAP
+#define BIFPLR3_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR3_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR3_1_ROOT_STATUS
+#define BIFPLR3_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR3_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR3_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR3_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR3_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR3_1_DEVICE_CAP2
+#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR3_1_DEVICE_CNTL2
+#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR3_1_DEVICE_STATUS2
+#define BIFPLR3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_1_LINK_CAP2
+#define BIFPLR3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR3_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR3_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR3_1_LINK_CNTL2
+#define BIFPLR3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR3_1_LINK_STATUS2
+#define BIFPLR3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR3_1_SLOT_CAP2
+#define BIFPLR3_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR3_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_1_SLOT_CNTL2
+#define BIFPLR3_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR3_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_1_SLOT_STATUS2
+#define BIFPLR3_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR3_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR3_1_MSI_CAP_LIST
+#define BIFPLR3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_1_MSI_MSG_CNTL
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR3_1_MSI_MSG_ADDR_LO
+#define BIFPLR3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR3_1_MSI_MSG_ADDR_HI
+#define BIFPLR3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_1_MSI_MSG_DATA
+#define BIFPLR3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR3_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR3_1_MSI_MSG_DATA_64
+#define BIFPLR3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR3_1_SSID_CAP_LIST
+#define BIFPLR3_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_1_SSID_CAP
+#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR3_1_MSI_MAP_CAP_LIST
+#define BIFPLR3_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR3_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR3_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR3_1_MSI_MAP_CAP
+#define BIFPLR3_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR3_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR3_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR3_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR3_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR3_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR3_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_1_PCIE_PORT_VC_CNTL
+#define BIFPLR3_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR3_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR3_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR3_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR3_1_PCIE_PORT_VC_STATUS
+#define BIFPLR3_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR3_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR3_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR3_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR3_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR3_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR3_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR3_1_PCIE_CORR_ERR_MASK
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR3_1_PCIE_HDR_LOG0
+#define BIFPLR3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_HDR_LOG1
+#define BIFPLR3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_HDR_LOG2
+#define BIFPLR3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_HDR_LOG3
+#define BIFPLR3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR3_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR3_1_PCIE_ERR_SRC_ID
+#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR3_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_LINK_CNTL3
+#define BIFPLR3_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR3_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR3_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_ACS_CAP
+#define BIFPLR3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR3_1_PCIE_ACS_CNTL
+#define BIFPLR3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR3_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_MC_CAP
+#define BIFPLR3_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR3_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR3_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR3_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR3_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR3_1_PCIE_MC_CNTL
+#define BIFPLR3_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR3_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR3_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR3_1_PCIE_MC_ADDR0
+#define BIFPLR3_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR3_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR3_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR3_1_PCIE_MC_ADDR1
+#define BIFPLR3_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_RCV0
+#define BIFPLR3_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_RCV1
+#define BIFPLR3_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR3_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR3_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR3_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR3_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR3_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_DPC_CAP_LIST
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR3_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR3_1_PCIE_DPC_CNTL
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR3_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR3_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR3_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR3_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR3_1_PCIE_DPC_STATUS
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR3_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR3_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR3_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_STATUS
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_MASK
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_ESM_CAP_LIST
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_ESM_HEADER_1
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_ESM_HEADER_2
+#define BIFPLR3_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR3_1_PCIE_ESM_STATUS
+#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR3_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR3_1_PCIE_ESM_CTRL
+#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR3_1_PCIE_ESM_CAP_1
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_2
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_3
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR3_1_PCIE_ESM_CAP_4
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_5
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_6
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR3_1_PCIE_ESM_CAP_7
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR3_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR3_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR3_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR3_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR3_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR3_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR3_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR3_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR3_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR3_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_LINK_CAP_16GT
+#define BIFPLR3_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR3_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_1_LINK_CNTL_16GT
+#define BIFPLR3_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR3_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_1_LINK_STATUS_16GT
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR3_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR3_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR3_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR3_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR3_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR3_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR3_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR3_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_MARGINING_PORT_CAP
+#define BIFPLR3_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR3_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR3_1_MARGINING_PORT_STATUS
+#define BIFPLR3_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR3_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR3_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR3_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR3_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR3_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR3_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR3_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR3_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_CCIX_HEADER_1
+#define BIFPLR3_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR3_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR3_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR3_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR3_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR3_1_PCIE_CCIX_HEADER_2
+#define BIFPLR3_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR3_1_PCIE_CCIX_CAP
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR3_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR3_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR3_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR3_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR3_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR3_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR3_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR3_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR3_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR3_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR3_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR3_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR3_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR3_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR3_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR3_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr4_cfgdecp
+//BIFPLR4_1_VENDOR_ID
+#define BIFPLR4_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR4_1_DEVICE_ID
+#define BIFPLR4_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR4_1_COMMAND
+#define BIFPLR4_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR4_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR4_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR4_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR4_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR4_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR4_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR4_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR4_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR4_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR4_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR4_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR4_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR4_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR4_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR4_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR4_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR4_1_STATUS
+#define BIFPLR4_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR4_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR4_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR4_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR4_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR4_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR4_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR4_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR4_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR4_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR4_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR4_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR4_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR4_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR4_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR4_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR4_1_REVISION_ID
+#define BIFPLR4_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR4_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR4_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR4_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR4_1_PROG_INTERFACE
+#define BIFPLR4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR4_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR4_1_SUB_CLASS
+#define BIFPLR4_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR4_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR4_1_BASE_CLASS
+#define BIFPLR4_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR4_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR4_1_CACHE_LINE
+#define BIFPLR4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR4_1_LATENCY
+#define BIFPLR4_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR4_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR4_1_HEADER
+#define BIFPLR4_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR4_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR4_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR4_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR4_1_BIST
+#define BIFPLR4_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR4_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR4_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR4_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR4_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR4_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR4_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR4_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR4_1_IO_BASE_LIMIT
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR4_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR4_1_SECONDARY_STATUS
+#define BIFPLR4_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR4_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR4_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR4_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR4_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR4_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR4_1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR4_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR4_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR4_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR4_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR4_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR4_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR4_1_MEM_BASE_LIMIT
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR4_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR4_1_PREF_BASE_LIMIT
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR4_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR4_1_PREF_BASE_UPPER
+#define BIFPLR4_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR4_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PREF_LIMIT_UPPER
+#define BIFPLR4_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR4_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR4_1_IO_BASE_LIMIT_HI
+#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR4_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR4_1_CAP_PTR
+#define BIFPLR4_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR4_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR4_1_ROM_BASE_ADDR
+#define BIFPLR4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR4_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_INTERRUPT_LINE
+#define BIFPLR4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR4_1_INTERRUPT_PIN
+#define BIFPLR4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR4_1_IRQ_BRIDGE_CNTL
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR4_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR4_1_EXT_BRIDGE_CNTL
+#define BIFPLR4_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR4_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR4_1_VENDOR_CAP_LIST
+#define BIFPLR4_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR4_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR4_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR4_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR4_1_ADAPTER_ID_W
+#define BIFPLR4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR4_1_PMI_CAP_LIST
+#define BIFPLR4_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_1_PMI_CAP
+#define BIFPLR4_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR4_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR4_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR4_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR4_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR4_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR4_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR4_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR4_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR4_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR4_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR4_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR4_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR4_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR4_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR4_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR4_1_PMI_STATUS_CNTL
+#define BIFPLR4_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR4_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR4_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR4_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR4_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR4_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR4_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR4_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR4_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR4_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR4_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR4_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR4_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR4_1_PCIE_CAP_LIST
+#define BIFPLR4_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_1_PCIE_CAP
+#define BIFPLR4_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR4_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR4_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR4_1_DEVICE_CAP
+#define BIFPLR4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR4_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR4_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR4_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR4_1_DEVICE_CNTL
+#define BIFPLR4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR4_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR4_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR4_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR4_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR4_1_DEVICE_STATUS
+#define BIFPLR4_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR4_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR4_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR4_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR4_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR4_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR4_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR4_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR4_1_LINK_CAP
+#define BIFPLR4_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR4_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR4_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR4_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR4_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR4_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR4_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR4_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR4_1_LINK_CNTL
+#define BIFPLR4_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR4_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR4_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR4_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR4_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR4_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR4_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR4_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR4_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR4_1_LINK_STATUS
+#define BIFPLR4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR4_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR4_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR4_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR4_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR4_1_SLOT_CAP
+#define BIFPLR4_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR4_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR4_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR4_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR4_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR4_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR4_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR4_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR4_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR4_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR4_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR4_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR4_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR4_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR4_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR4_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR4_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR4_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR4_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR4_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR4_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR4_1_SLOT_CNTL
+#define BIFPLR4_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR4_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR4_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR4_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR4_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR4_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR4_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR4_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR4_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR4_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR4_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR4_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR4_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR4_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR4_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR4_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR4_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR4_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR4_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR4_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR4_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR4_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR4_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR4_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR4_1_SLOT_STATUS
+#define BIFPLR4_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR4_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR4_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR4_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR4_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR4_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR4_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR4_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR4_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR4_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR4_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR4_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR4_1_ROOT_CNTL
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR4_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR4_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR4_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR4_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR4_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR4_1_ROOT_CAP
+#define BIFPLR4_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR4_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR4_1_ROOT_STATUS
+#define BIFPLR4_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR4_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR4_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR4_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR4_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR4_1_DEVICE_CAP2
+#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR4_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR4_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR4_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR4_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR4_1_DEVICE_CNTL2
+#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR4_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR4_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR4_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR4_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR4_1_DEVICE_STATUS2
+#define BIFPLR4_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR4_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_1_LINK_CAP2
+#define BIFPLR4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR4_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR4_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR4_1_LINK_CNTL2
+#define BIFPLR4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR4_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR4_1_LINK_STATUS2
+#define BIFPLR4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR4_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR4_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR4_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR4_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR4_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR4_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR4_1_SLOT_CAP2
+#define BIFPLR4_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR4_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_1_SLOT_CNTL2
+#define BIFPLR4_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR4_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_1_SLOT_STATUS2
+#define BIFPLR4_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR4_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR4_1_MSI_CAP_LIST
+#define BIFPLR4_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_1_MSI_MSG_CNTL
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR4_1_MSI_MSG_ADDR_LO
+#define BIFPLR4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR4_1_MSI_MSG_ADDR_HI
+#define BIFPLR4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_1_MSI_MSG_DATA
+#define BIFPLR4_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR4_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR4_1_MSI_MSG_DATA_64
+#define BIFPLR4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR4_1_SSID_CAP_LIST
+#define BIFPLR4_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_1_SSID_CAP
+#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR4_1_MSI_MAP_CAP_LIST
+#define BIFPLR4_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR4_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR4_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR4_1_MSI_MAP_CAP
+#define BIFPLR4_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR4_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR4_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR4_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR4_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR4_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR4_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_1_PCIE_PORT_VC_CNTL
+#define BIFPLR4_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR4_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR4_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR4_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR4_1_PCIE_PORT_VC_STATUS
+#define BIFPLR4_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR4_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR4_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR4_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR4_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR4_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR4_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR4_1_PCIE_CORR_ERR_MASK
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR4_1_PCIE_HDR_LOG0
+#define BIFPLR4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_HDR_LOG1
+#define BIFPLR4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_HDR_LOG2
+#define BIFPLR4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_HDR_LOG3
+#define BIFPLR4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR4_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR4_1_PCIE_ERR_SRC_ID
+#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR4_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_LINK_CNTL3
+#define BIFPLR4_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR4_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR4_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_ACS_CAP
+#define BIFPLR4_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR4_1_PCIE_ACS_CNTL
+#define BIFPLR4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR4_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_MC_CAP
+#define BIFPLR4_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR4_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR4_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR4_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR4_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR4_1_PCIE_MC_CNTL
+#define BIFPLR4_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR4_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR4_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR4_1_PCIE_MC_ADDR0
+#define BIFPLR4_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR4_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR4_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR4_1_PCIE_MC_ADDR1
+#define BIFPLR4_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_RCV0
+#define BIFPLR4_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_RCV1
+#define BIFPLR4_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR4_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR4_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR4_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR4_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR4_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_DPC_CAP_LIST
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR4_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR4_1_PCIE_DPC_CNTL
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR4_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR4_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR4_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR4_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR4_1_PCIE_DPC_STATUS
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR4_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR4_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR4_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_STATUS
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_MASK
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_ESM_CAP_LIST
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_ESM_HEADER_1
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_ESM_HEADER_2
+#define BIFPLR4_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR4_1_PCIE_ESM_STATUS
+#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR4_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR4_1_PCIE_ESM_CTRL
+#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR4_1_PCIE_ESM_CAP_1
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_2
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_3
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR4_1_PCIE_ESM_CAP_4
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_5
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_6
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR4_1_PCIE_ESM_CAP_7
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR4_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR4_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR4_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR4_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR4_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR4_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR4_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR4_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR4_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR4_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_LINK_CAP_16GT
+#define BIFPLR4_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR4_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_1_LINK_CNTL_16GT
+#define BIFPLR4_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR4_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_1_LINK_STATUS_16GT
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR4_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR4_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR4_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR4_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR4_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR4_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR4_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR4_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_MARGINING_PORT_CAP
+#define BIFPLR4_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR4_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR4_1_MARGINING_PORT_STATUS
+#define BIFPLR4_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR4_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR4_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR4_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR4_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR4_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR4_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR4_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR4_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_CCIX_HEADER_1
+#define BIFPLR4_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR4_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR4_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR4_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR4_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR4_1_PCIE_CCIX_HEADER_2
+#define BIFPLR4_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR4_1_PCIE_CCIX_CAP
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR4_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR4_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR4_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR4_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR4_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR4_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR4_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR4_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR4_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR4_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR4_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR4_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR4_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR4_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR4_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR4_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr5_cfgdecp
+//BIFPLR5_1_VENDOR_ID
+#define BIFPLR5_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR5_1_DEVICE_ID
+#define BIFPLR5_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR5_1_COMMAND
+#define BIFPLR5_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR5_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR5_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR5_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR5_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR5_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR5_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR5_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR5_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR5_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR5_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR5_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR5_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR5_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR5_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR5_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR5_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR5_1_STATUS
+#define BIFPLR5_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR5_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR5_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR5_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR5_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR5_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR5_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR5_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR5_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR5_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR5_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR5_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR5_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR5_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR5_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR5_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR5_1_REVISION_ID
+#define BIFPLR5_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR5_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR5_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR5_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR5_1_PROG_INTERFACE
+#define BIFPLR5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR5_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR5_1_SUB_CLASS
+#define BIFPLR5_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR5_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR5_1_BASE_CLASS
+#define BIFPLR5_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR5_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR5_1_CACHE_LINE
+#define BIFPLR5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR5_1_LATENCY
+#define BIFPLR5_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR5_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR5_1_HEADER
+#define BIFPLR5_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR5_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR5_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR5_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR5_1_BIST
+#define BIFPLR5_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR5_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR5_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR5_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR5_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR5_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR5_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR5_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR5_1_IO_BASE_LIMIT
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR5_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR5_1_SECONDARY_STATUS
+#define BIFPLR5_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR5_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR5_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR5_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR5_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR5_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR5_1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR5_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR5_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR5_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR5_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR5_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR5_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR5_1_MEM_BASE_LIMIT
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR5_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR5_1_PREF_BASE_LIMIT
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR5_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR5_1_PREF_BASE_UPPER
+#define BIFPLR5_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR5_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PREF_LIMIT_UPPER
+#define BIFPLR5_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR5_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR5_1_IO_BASE_LIMIT_HI
+#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR5_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR5_1_CAP_PTR
+#define BIFPLR5_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR5_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR5_1_ROM_BASE_ADDR
+#define BIFPLR5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR5_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_INTERRUPT_LINE
+#define BIFPLR5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR5_1_INTERRUPT_PIN
+#define BIFPLR5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR5_1_IRQ_BRIDGE_CNTL
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR5_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR5_1_EXT_BRIDGE_CNTL
+#define BIFPLR5_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR5_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR5_1_VENDOR_CAP_LIST
+#define BIFPLR5_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR5_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR5_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR5_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR5_1_ADAPTER_ID_W
+#define BIFPLR5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR5_1_PMI_CAP_LIST
+#define BIFPLR5_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_1_PMI_CAP
+#define BIFPLR5_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR5_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR5_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR5_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR5_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR5_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR5_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR5_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR5_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR5_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR5_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR5_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR5_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR5_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR5_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR5_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR5_1_PMI_STATUS_CNTL
+#define BIFPLR5_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR5_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR5_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR5_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR5_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR5_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR5_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR5_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR5_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR5_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR5_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR5_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR5_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR5_1_PCIE_CAP_LIST
+#define BIFPLR5_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_1_PCIE_CAP
+#define BIFPLR5_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR5_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR5_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR5_1_DEVICE_CAP
+#define BIFPLR5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR5_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR5_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR5_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR5_1_DEVICE_CNTL
+#define BIFPLR5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR5_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR5_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR5_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR5_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR5_1_DEVICE_STATUS
+#define BIFPLR5_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR5_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR5_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR5_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR5_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR5_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR5_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR5_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR5_1_LINK_CAP
+#define BIFPLR5_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR5_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR5_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR5_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR5_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR5_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR5_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR5_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR5_1_LINK_CNTL
+#define BIFPLR5_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR5_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR5_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR5_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR5_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR5_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR5_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR5_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR5_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR5_1_LINK_STATUS
+#define BIFPLR5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR5_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR5_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR5_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR5_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR5_1_SLOT_CAP
+#define BIFPLR5_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR5_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR5_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR5_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR5_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR5_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR5_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR5_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR5_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR5_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR5_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR5_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR5_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR5_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR5_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR5_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR5_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR5_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR5_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR5_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR5_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR5_1_SLOT_CNTL
+#define BIFPLR5_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR5_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR5_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR5_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR5_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR5_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR5_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR5_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR5_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR5_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR5_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR5_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR5_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR5_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR5_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR5_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR5_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR5_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR5_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR5_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR5_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR5_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR5_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR5_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR5_1_SLOT_STATUS
+#define BIFPLR5_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR5_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR5_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR5_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR5_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR5_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR5_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR5_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR5_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR5_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR5_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR5_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR5_1_ROOT_CNTL
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR5_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR5_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR5_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR5_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR5_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR5_1_ROOT_CAP
+#define BIFPLR5_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR5_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR5_1_ROOT_STATUS
+#define BIFPLR5_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR5_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR5_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR5_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR5_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR5_1_DEVICE_CAP2
+#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR5_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR5_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR5_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR5_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR5_1_DEVICE_CNTL2
+#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR5_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR5_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR5_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR5_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR5_1_DEVICE_STATUS2
+#define BIFPLR5_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR5_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_1_LINK_CAP2
+#define BIFPLR5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR5_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR5_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR5_1_LINK_CNTL2
+#define BIFPLR5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR5_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR5_1_LINK_STATUS2
+#define BIFPLR5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR5_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR5_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR5_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR5_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR5_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR5_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR5_1_SLOT_CAP2
+#define BIFPLR5_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR5_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_1_SLOT_CNTL2
+#define BIFPLR5_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR5_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_1_SLOT_STATUS2
+#define BIFPLR5_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR5_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR5_1_MSI_CAP_LIST
+#define BIFPLR5_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_1_MSI_MSG_CNTL
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR5_1_MSI_MSG_ADDR_LO
+#define BIFPLR5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR5_1_MSI_MSG_ADDR_HI
+#define BIFPLR5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_1_MSI_MSG_DATA
+#define BIFPLR5_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR5_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR5_1_MSI_MSG_DATA_64
+#define BIFPLR5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR5_1_SSID_CAP_LIST
+#define BIFPLR5_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_1_SSID_CAP
+#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR5_1_MSI_MAP_CAP_LIST
+#define BIFPLR5_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR5_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR5_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR5_1_MSI_MAP_CAP
+#define BIFPLR5_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR5_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR5_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR5_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR5_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR5_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR5_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_1_PCIE_PORT_VC_CNTL
+#define BIFPLR5_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR5_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR5_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR5_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR5_1_PCIE_PORT_VC_STATUS
+#define BIFPLR5_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR5_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR5_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR5_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR5_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR5_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR5_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR5_1_PCIE_CORR_ERR_MASK
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR5_1_PCIE_HDR_LOG0
+#define BIFPLR5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_HDR_LOG1
+#define BIFPLR5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_HDR_LOG2
+#define BIFPLR5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_HDR_LOG3
+#define BIFPLR5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR5_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR5_1_PCIE_ERR_SRC_ID
+#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR5_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_LINK_CNTL3
+#define BIFPLR5_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR5_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR5_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_ACS_CAP
+#define BIFPLR5_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR5_1_PCIE_ACS_CNTL
+#define BIFPLR5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR5_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_MC_CAP
+#define BIFPLR5_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR5_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR5_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR5_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR5_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR5_1_PCIE_MC_CNTL
+#define BIFPLR5_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR5_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR5_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR5_1_PCIE_MC_ADDR0
+#define BIFPLR5_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR5_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR5_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR5_1_PCIE_MC_ADDR1
+#define BIFPLR5_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_RCV0
+#define BIFPLR5_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_RCV1
+#define BIFPLR5_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR5_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR5_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR5_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR5_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR5_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_DPC_CAP_LIST
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR5_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR5_1_PCIE_DPC_CNTL
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR5_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR5_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR5_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR5_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR5_1_PCIE_DPC_STATUS
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR5_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR5_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR5_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_STATUS
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_MASK
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_ESM_CAP_LIST
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_ESM_HEADER_1
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_ESM_HEADER_2
+#define BIFPLR5_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR5_1_PCIE_ESM_STATUS
+#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR5_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR5_1_PCIE_ESM_CTRL
+#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR5_1_PCIE_ESM_CAP_1
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_2
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_3
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR5_1_PCIE_ESM_CAP_4
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_5
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_6
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR5_1_PCIE_ESM_CAP_7
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR5_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR5_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR5_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR5_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR5_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR5_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR5_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR5_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR5_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR5_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_LINK_CAP_16GT
+#define BIFPLR5_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR5_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_1_LINK_CNTL_16GT
+#define BIFPLR5_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR5_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_1_LINK_STATUS_16GT
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR5_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR5_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR5_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR5_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR5_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR5_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR5_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR5_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_MARGINING_PORT_CAP
+#define BIFPLR5_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR5_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR5_1_MARGINING_PORT_STATUS
+#define BIFPLR5_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR5_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR5_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR5_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR5_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR5_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR5_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR5_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR5_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_CCIX_HEADER_1
+#define BIFPLR5_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR5_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR5_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR5_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR5_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR5_1_PCIE_CCIX_HEADER_2
+#define BIFPLR5_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR5_1_PCIE_CCIX_CAP
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR5_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR5_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR5_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR5_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR5_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR5_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR5_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR5_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR5_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR5_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR5_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR5_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR5_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR5_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR5_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR5_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_pcie0_bifplr6_cfgdecp
+//BIFPLR6_1_VENDOR_ID
+#define BIFPLR6_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIFPLR6_1_DEVICE_ID
+#define BIFPLR6_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIFPLR6_1_COMMAND
+#define BIFPLR6_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIFPLR6_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIFPLR6_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIFPLR6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIFPLR6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIFPLR6_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIFPLR6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIFPLR6_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIFPLR6_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIFPLR6_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIFPLR6_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIFPLR6_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIFPLR6_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIFPLR6_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIFPLR6_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIFPLR6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIFPLR6_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIFPLR6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIFPLR6_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIFPLR6_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIFPLR6_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIFPLR6_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIFPLR6_1_STATUS
+#define BIFPLR6_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIFPLR6_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIFPLR6_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIFPLR6_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR6_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR6_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR6_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIFPLR6_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIFPLR6_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIFPLR6_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR6_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR6_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR6_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR6_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR6_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR6_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR6_1_REVISION_ID
+#define BIFPLR6_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIFPLR6_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIFPLR6_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIFPLR6_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIFPLR6_1_PROG_INTERFACE
+#define BIFPLR6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIFPLR6_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIFPLR6_1_SUB_CLASS
+#define BIFPLR6_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIFPLR6_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIFPLR6_1_BASE_CLASS
+#define BIFPLR6_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIFPLR6_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIFPLR6_1_CACHE_LINE
+#define BIFPLR6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIFPLR6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIFPLR6_1_LATENCY
+#define BIFPLR6_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIFPLR6_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIFPLR6_1_HEADER
+#define BIFPLR6_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIFPLR6_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIFPLR6_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIFPLR6_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIFPLR6_1_BIST
+#define BIFPLR6_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIFPLR6_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIFPLR6_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIFPLR6_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIFPLR6_1_BIST__BIST_STRT_MASK 0x40L
+#define BIFPLR6_1_BIST__BIST_CAP_MASK 0x80L
+//BIFPLR6_1_SUB_BUS_NUMBER_LATENCY
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIFPLR6_1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIFPLR6_1_IO_BASE_LIMIT
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIFPLR6_1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIFPLR6_1_SECONDARY_STATUS
+#define BIFPLR6_1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIFPLR6_1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIFPLR6_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIFPLR6_1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIFPLR6_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIFPLR6_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIFPLR6_1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIFPLR6_1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIFPLR6_1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIFPLR6_1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIFPLR6_1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIFPLR6_1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIFPLR6_1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIFPLR6_1_MEM_BASE_LIMIT
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR6_1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR6_1_PREF_BASE_LIMIT
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIFPLR6_1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIFPLR6_1_PREF_BASE_UPPER
+#define BIFPLR6_1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIFPLR6_1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PREF_LIMIT_UPPER
+#define BIFPLR6_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIFPLR6_1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIFPLR6_1_IO_BASE_LIMIT_HI
+#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIFPLR6_1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIFPLR6_1_CAP_PTR
+#define BIFPLR6_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIFPLR6_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIFPLR6_1_ROM_BASE_ADDR
+#define BIFPLR6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIFPLR6_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_INTERRUPT_LINE
+#define BIFPLR6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIFPLR6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIFPLR6_1_INTERRUPT_PIN
+#define BIFPLR6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIFPLR6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIFPLR6_1_IRQ_BRIDGE_CNTL
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIFPLR6_1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIFPLR6_1_EXT_BRIDGE_CNTL
+#define BIFPLR6_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIFPLR6_1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIFPLR6_1_VENDOR_CAP_LIST
+#define BIFPLR6_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIFPLR6_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIFPLR6_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIFPLR6_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIFPLR6_1_ADAPTER_ID_W
+#define BIFPLR6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR6_1_PMI_CAP_LIST
+#define BIFPLR6_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_1_PMI_CAP
+#define BIFPLR6_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIFPLR6_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIFPLR6_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIFPLR6_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIFPLR6_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIFPLR6_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIFPLR6_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIFPLR6_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIFPLR6_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIFPLR6_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIFPLR6_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIFPLR6_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIFPLR6_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIFPLR6_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIFPLR6_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIFPLR6_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIFPLR6_1_PMI_STATUS_CNTL
+#define BIFPLR6_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIFPLR6_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIFPLR6_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIFPLR6_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIFPLR6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIFPLR6_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIFPLR6_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIFPLR6_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIFPLR6_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIFPLR6_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIFPLR6_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIFPLR6_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIFPLR6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIFPLR6_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIFPLR6_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIFPLR6_1_PCIE_CAP_LIST
+#define BIFPLR6_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_1_PCIE_CAP
+#define BIFPLR6_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIFPLR6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIFPLR6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIFPLR6_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIFPLR6_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIFPLR6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIFPLR6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIFPLR6_1_DEVICE_CAP
+#define BIFPLR6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIFPLR6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIFPLR6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIFPLR6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIFPLR6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIFPLR6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIFPLR6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIFPLR6_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIFPLR6_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIFPLR6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIFPLR6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIFPLR6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIFPLR6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIFPLR6_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIFPLR6_1_DEVICE_CNTL
+#define BIFPLR6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIFPLR6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIFPLR6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIFPLR6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIFPLR6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIFPLR6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIFPLR6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIFPLR6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIFPLR6_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIFPLR6_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR6_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIFPLR6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIFPLR6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIFPLR6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIFPLR6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIFPLR6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIFPLR6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIFPLR6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIFPLR6_1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIFPLR6_1_DEVICE_STATUS
+#define BIFPLR6_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIFPLR6_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIFPLR6_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIFPLR6_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIFPLR6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIFPLR6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIFPLR6_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIFPLR6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIFPLR6_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIFPLR6_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIFPLR6_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIFPLR6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIFPLR6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIFPLR6_1_LINK_CAP
+#define BIFPLR6_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIFPLR6_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIFPLR6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIFPLR6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIFPLR6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIFPLR6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIFPLR6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIFPLR6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIFPLR6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIFPLR6_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIFPLR6_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIFPLR6_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIFPLR6_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIFPLR6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIFPLR6_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIFPLR6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIFPLR6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIFPLR6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIFPLR6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIFPLR6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIFPLR6_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIFPLR6_1_LINK_CNTL
+#define BIFPLR6_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIFPLR6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIFPLR6_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIFPLR6_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIFPLR6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIFPLR6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIFPLR6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIFPLR6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIFPLR6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIFPLR6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIFPLR6_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIFPLR6_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIFPLR6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIFPLR6_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIFPLR6_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIFPLR6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIFPLR6_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIFPLR6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIFPLR6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIFPLR6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIFPLR6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIFPLR6_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIFPLR6_1_LINK_STATUS
+#define BIFPLR6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIFPLR6_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIFPLR6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIFPLR6_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIFPLR6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIFPLR6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIFPLR6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIFPLR6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIFPLR6_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIFPLR6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIFPLR6_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIFPLR6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIFPLR6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIFPLR6_1_SLOT_CAP
+#define BIFPLR6_1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIFPLR6_1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIFPLR6_1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIFPLR6_1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIFPLR6_1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIFPLR6_1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIFPLR6_1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIFPLR6_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIFPLR6_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIFPLR6_1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIFPLR6_1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIFPLR6_1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIFPLR6_1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIFPLR6_1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIFPLR6_1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIFPLR6_1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIFPLR6_1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIFPLR6_1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIFPLR6_1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIFPLR6_1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIFPLR6_1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIFPLR6_1_SLOT_CNTL
+#define BIFPLR6_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIFPLR6_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIFPLR6_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIFPLR6_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIFPLR6_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIFPLR6_1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIFPLR6_1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIFPLR6_1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIFPLR6_1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIFPLR6_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIFPLR6_1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIFPLR6_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIFPLR6_1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIFPLR6_1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIFPLR6_1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIFPLR6_1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIFPLR6_1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIFPLR6_1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIFPLR6_1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIFPLR6_1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIFPLR6_1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIFPLR6_1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIFPLR6_1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIFPLR6_1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIFPLR6_1_SLOT_STATUS
+#define BIFPLR6_1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIFPLR6_1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIFPLR6_1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIFPLR6_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIFPLR6_1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIFPLR6_1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIFPLR6_1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIFPLR6_1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIFPLR6_1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIFPLR6_1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIFPLR6_1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIFPLR6_1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIFPLR6_1_ROOT_CNTL
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIFPLR6_1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIFPLR6_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIFPLR6_1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIFPLR6_1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIFPLR6_1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIFPLR6_1_ROOT_CAP
+#define BIFPLR6_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIFPLR6_1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIFPLR6_1_ROOT_STATUS
+#define BIFPLR6_1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIFPLR6_1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIFPLR6_1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIFPLR6_1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIFPLR6_1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIFPLR6_1_DEVICE_CAP2
+#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIFPLR6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIFPLR6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIFPLR6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIFPLR6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIFPLR6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIFPLR6_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIFPLR6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIFPLR6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIFPLR6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIFPLR6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIFPLR6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIFPLR6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIFPLR6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIFPLR6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIFPLR6_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIFPLR6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIFPLR6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIFPLR6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIFPLR6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIFPLR6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIFPLR6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIFPLR6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIFPLR6_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIFPLR6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIFPLR6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIFPLR6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIFPLR6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIFPLR6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIFPLR6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIFPLR6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIFPLR6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIFPLR6_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR6_1_DEVICE_CNTL2
+#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIFPLR6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIFPLR6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIFPLR6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIFPLR6_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIFPLR6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIFPLR6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIFPLR6_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIFPLR6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIFPLR6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIFPLR6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIFPLR6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIFPLR6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIFPLR6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIFPLR6_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIFPLR6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIFPLR6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIFPLR6_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIFPLR6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIFPLR6_1_DEVICE_STATUS2
+#define BIFPLR6_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR6_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_1_LINK_CAP2
+#define BIFPLR6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIFPLR6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIFPLR6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIFPLR6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIFPLR6_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIFPLR6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIFPLR6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIFPLR6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIFPLR6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIFPLR6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIFPLR6_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIFPLR6_1_LINK_CNTL2
+#define BIFPLR6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIFPLR6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIFPLR6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIFPLR6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIFPLR6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIFPLR6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIFPLR6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIFPLR6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIFPLR6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIFPLR6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIFPLR6_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIFPLR6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIFPLR6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIFPLR6_1_LINK_STATUS2
+#define BIFPLR6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIFPLR6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIFPLR6_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIFPLR6_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIFPLR6_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIFPLR6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIFPLR6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIFPLR6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIFPLR6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIFPLR6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIFPLR6_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIFPLR6_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIFPLR6_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIFPLR6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIFPLR6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIFPLR6_1_SLOT_CAP2
+#define BIFPLR6_1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIFPLR6_1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_1_SLOT_CNTL2
+#define BIFPLR6_1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIFPLR6_1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_1_SLOT_STATUS2
+#define BIFPLR6_1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIFPLR6_1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIFPLR6_1_MSI_CAP_LIST
+#define BIFPLR6_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_1_MSI_MSG_CNTL
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIFPLR6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+//BIFPLR6_1_MSI_MSG_ADDR_LO
+#define BIFPLR6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIFPLR6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIFPLR6_1_MSI_MSG_ADDR_HI
+#define BIFPLR6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIFPLR6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_1_MSI_MSG_DATA
+#define BIFPLR6_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIFPLR6_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIFPLR6_1_MSI_MSG_DATA_64
+#define BIFPLR6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIFPLR6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIFPLR6_1_SSID_CAP_LIST
+#define BIFPLR6_1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_1_SSID_CAP
+#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIFPLR6_1_MSI_MAP_CAP_LIST
+#define BIFPLR6_1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIFPLR6_1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIFPLR6_1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIFPLR6_1_MSI_MAP_CAP
+#define BIFPLR6_1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIFPLR6_1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIFPLR6_1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIFPLR6_1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIFPLR6_1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIFPLR6_1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_VENDOR_SPECIFIC1
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_VENDOR_SPECIFIC2
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_VC_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_PORT_VC_CAP_REG1
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIFPLR6_1_PCIE_PORT_VC_CAP_REG2
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_1_PCIE_PORT_VC_CNTL
+#define BIFPLR6_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIFPLR6_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIFPLR6_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIFPLR6_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIFPLR6_1_PCIE_PORT_VC_STATUS
+#define BIFPLR6_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIFPLR6_1_PCIE_VC0_RESOURCE_CAP
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR6_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR6_1_PCIE_VC1_RESOURCE_CAP
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIFPLR6_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_UNCORR_ERR_STATUS
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIFPLR6_1_PCIE_UNCORR_ERR_MASK
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIFPLR6_1_PCIE_CORR_ERR_STATUS
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIFPLR6_1_PCIE_CORR_ERR_MASK
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIFPLR6_1_PCIE_HDR_LOG0
+#define BIFPLR6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_HDR_LOG1
+#define BIFPLR6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_HDR_LOG2
+#define BIFPLR6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_HDR_LOG3
+#define BIFPLR6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_ROOT_ERR_CMD
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIFPLR6_1_PCIE_ROOT_ERR_STATUS
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIFPLR6_1_PCIE_ERR_SRC_ID
+#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIFPLR6_1_PCIE_TLP_PREFIX_LOG0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_TLP_PREFIX_LOG1
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_TLP_PREFIX_LOG2
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_TLP_PREFIX_LOG3
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_LINK_CNTL3
+#define BIFPLR6_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIFPLR6_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIFPLR6_1_PCIE_LANE_ERROR_STATUS
+#define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK 0x000FL
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK 0x0070L
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK 0x7000L
+//BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_ACS_CAP
+#define BIFPLR6_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIFPLR6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIFPLR6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIFPLR6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIFPLR6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIFPLR6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIFPLR6_1_PCIE_ACS_CNTL
+#define BIFPLR6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIFPLR6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIFPLR6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIFPLR6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIFPLR6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIFPLR6_1_PCIE_MC_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_MC_CAP
+#define BIFPLR6_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIFPLR6_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIFPLR6_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIFPLR6_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIFPLR6_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIFPLR6_1_PCIE_MC_CNTL
+#define BIFPLR6_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIFPLR6_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIFPLR6_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIFPLR6_1_PCIE_MC_ADDR0
+#define BIFPLR6_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIFPLR6_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIFPLR6_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIFPLR6_1_PCIE_MC_ADDR1
+#define BIFPLR6_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_RCV0
+#define BIFPLR6_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_RCV1
+#define BIFPLR6_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_BLOCK_ALL0
+#define BIFPLR6_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_BLOCK_ALL1
+#define BIFPLR6_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_MC_OVERLAY_BAR0
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT 0x6
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK 0x0000003FL
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK 0xFFFFFFC0L
+//BIFPLR6_1_PCIE_MC_OVERLAY_BAR1
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_L1_PM_SUB_CAP
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT 0x1
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT 0x2
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT 0x3
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT 0x4
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT 0x10
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT 0x13
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK 0x00030000L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK 0x00F80000L
+//BIFPLR6_1_PCIE_L1_PM_SUB_CNTL
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT 0x0
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT 0x1
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT 0x2
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT 0x3
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT 0x8
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT 0x10
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK 0x0000FF00L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK 0x03FF0000L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK 0xE0000000L
+//BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT 0x0
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT 0x3
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK 0x00000003L
+#define BIFPLR6_1_PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK 0x000000F8L
+//BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_DPC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_DPC_CAP_LIST
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC__SHIFT 0x5
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED__SHIFT 0x6
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED__SHIFT 0x7
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE__SHIFT 0x8
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED__SHIFT 0xc
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_INTR_MSG_NUM_MASK 0x001FL
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_EXTENSIONS_FOR_DPC_MASK 0x0020L
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__POISONED_TLP_EGRESS_BLOCKING_SUPPORTED_MASK 0x0040L
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DPC_SOFTWARE_TRIGGERING_SUPPORTED_MASK 0x0080L
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__RP_PIO_LOG_SIZE_MASK 0x0F00L
+#define BIFPLR6_1_PCIE_DPC_CAP_LIST__DL_ACTIVE_ERR_COR_SIGNALING_SUPPORTED_MASK 0x1000L
+//BIFPLR6_1_PCIE_DPC_CNTL
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL__SHIFT 0x2
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE__SHIFT 0x3
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE__SHIFT 0x4
+#define BIFPLR6_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE__SHIFT 0x5
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER__SHIFT 0x6
+#define BIFPLR6_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE__SHIFT 0x7
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_TRIGGER_ENABLE_MASK 0x0003L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_COMPLETION_CONTROL_MASK 0x0004L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_INTERRUPT_ENABLE_MASK 0x0008L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_ERR_COR_ENABLE_MASK 0x0010L
+#define BIFPLR6_1_PCIE_DPC_CNTL__POISONED_TLP_EGRESS_BLOCKING_ENABLE_MASK 0x0020L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DPC_SOFTWARE_TRIGGER_MASK 0x0040L
+#define BIFPLR6_1_PCIE_DPC_CNTL__DL_ACTIVE_ERR_COR_ENABLE_MASK 0x0080L
+//BIFPLR6_1_PCIE_DPC_STATUS
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON__SHIFT 0x1
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS__SHIFT 0x3
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_RP_BUSY__SHIFT 0x4
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION__SHIFT 0x5
+#define BIFPLR6_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER__SHIFT 0x8
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_STATUS_MASK 0x0001L
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_MASK 0x0006L
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_INTERRUPT_STATUS_MASK 0x0008L
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_RP_BUSY_MASK 0x0010L
+#define BIFPLR6_1_PCIE_DPC_STATUS__DPC_TRIGGER_REASON_EXTENSION_MASK 0x0060L
+#define BIFPLR6_1_PCIE_DPC_STATUS__RP_PIO_FIRST_ERROR_POINTER_MASK 0x1F00L
+//BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID
+#define BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID__DPC_ERROR_SOURCE_ID_MASK 0xFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_STATUS
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CTO__SHIFT 0xa
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_STATUS__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_MASK
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CTO__SHIFT 0xa
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_MASK__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_SEVERITY
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CTO__SHIFT 0xa
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_SEVERITY__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_SYSERROR
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CTO__SHIFT 0xa
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_SYSERROR__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_EXCEPTION
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL__SHIFT 0x1
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO__SHIFT 0x2
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL__SHIFT 0x8
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL__SHIFT 0x9
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CTO__SHIFT 0xa
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL__SHIFT 0x10
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL__SHIFT 0x11
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO__SHIFT 0x12
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_UR_CPL_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CA_CPL_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__CFG_CTO_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_UR_CPL_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CA_CPL_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__IO_CTO_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_UR_CPL_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CA_CPL_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_RP_PIO_EXCEPTION__MEM_CTO_MASK 0x00040000L
+//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_ESM_CAP_LIST
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_ESM_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_ESM_HEADER_1
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_ESM_HEADER_2
+#define BIFPLR6_1_PCIE_ESM_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR6_1_PCIE_ESM_STATUS
+#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK 0x01FFL
+#define BIFPLR6_1_PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK 0x0E00L
+//BIFPLR6_1_PCIE_ESM_CTRL
+#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_ENABLED__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CTRL__ESM_ENABLED_MASK 0x8000L
+//BIFPLR6_1_PCIE_ESM_CAP_1
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P0G__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P1G__SHIFT 0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P2G__SHIFT 0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P3G__SHIFT 0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P4G__SHIFT 0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P5G__SHIFT 0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P6G__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P7G__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P8G__SHIFT 0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P9G__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_8P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_9P9G_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P0G_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P1G_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P2G_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P3G_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P4G_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P5G_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P6G_MASK 0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P7G_MASK 0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P8G_MASK 0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_1__ESM_10P9G_MASK 0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_2
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P0G__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P1G__SHIFT 0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P2G__SHIFT 0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P3G__SHIFT 0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P4G__SHIFT 0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P5G__SHIFT 0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P6G__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P7G__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P8G__SHIFT 0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P9G__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_11P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_12P9G_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P0G_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P1G_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P2G_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P3G_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P4G_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P5G_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P6G_MASK 0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P7G_MASK 0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P8G_MASK 0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_2__ESM_13P9G_MASK 0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_3
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_14P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_3__ESM_15P9G_MASK 0x00080000L
+//BIFPLR6_1_PCIE_ESM_CAP_4
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P0G__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P1G__SHIFT 0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P2G__SHIFT 0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P3G__SHIFT 0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P4G__SHIFT 0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P5G__SHIFT 0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P6G__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P7G__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P8G__SHIFT 0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P9G__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_16P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_17P9G_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P0G_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P1G_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P2G_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P3G_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P4G_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P5G_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P6G_MASK 0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P7G_MASK 0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P8G_MASK 0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_4__ESM_18P9G_MASK 0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_5
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P0G__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P1G__SHIFT 0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P2G__SHIFT 0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P3G__SHIFT 0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P4G__SHIFT 0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P5G__SHIFT 0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P6G__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P7G__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P8G__SHIFT 0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P9G__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_19P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_20P9G_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P0G_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P1G_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P2G_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P3G_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P4G_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P5G_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P6G_MASK 0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P7G_MASK 0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P8G_MASK 0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_5__ESM_21P9G_MASK 0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_6
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P0G__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P1G__SHIFT 0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P2G__SHIFT 0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P3G__SHIFT 0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P4G__SHIFT 0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P5G__SHIFT 0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P6G__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P7G__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P8G__SHIFT 0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P9G__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_22P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_23P9G_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P0G_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P1G_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P2G_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P3G_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P4G_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P5G_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P6G_MASK 0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P7G_MASK 0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P8G_MASK 0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_6__ESM_24P9G_MASK 0x20000000L
+//BIFPLR6_1_PCIE_ESM_CAP_7
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P0G__SHIFT 0x0
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P1G__SHIFT 0x1
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P2G__SHIFT 0x2
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P3G__SHIFT 0x3
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P4G__SHIFT 0x4
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P5G__SHIFT 0x5
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P6G__SHIFT 0x6
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P7G__SHIFT 0x7
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P8G__SHIFT 0x8
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P9G__SHIFT 0x9
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P0G__SHIFT 0xa
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P1G__SHIFT 0xb
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P2G__SHIFT 0xc
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P3G__SHIFT 0xd
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P4G__SHIFT 0xe
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P5G__SHIFT 0xf
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P6G__SHIFT 0x10
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P7G__SHIFT 0x11
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P8G__SHIFT 0x12
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P9G__SHIFT 0x13
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P0G__SHIFT 0x14
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P1G__SHIFT 0x15
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P2G__SHIFT 0x16
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P3G__SHIFT 0x17
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P4G__SHIFT 0x18
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P5G__SHIFT 0x19
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P6G__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P7G__SHIFT 0x1b
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P8G__SHIFT 0x1c
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P9G__SHIFT 0x1d
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_28P0G__SHIFT 0x1e
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P0G_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P1G_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P2G_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P3G_MASK 0x00000008L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P4G_MASK 0x00000010L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P5G_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P6G_MASK 0x00000040L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P7G_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P8G_MASK 0x00000100L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_25P9G_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P0G_MASK 0x00000400L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P1G_MASK 0x00000800L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P2G_MASK 0x00001000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P3G_MASK 0x00002000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P4G_MASK 0x00004000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P5G_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P6G_MASK 0x00010000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P7G_MASK 0x00020000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P8G_MASK 0x00040000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_26P9G_MASK 0x00080000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P0G_MASK 0x00100000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P1G_MASK 0x00200000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P2G_MASK 0x00400000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P3G_MASK 0x00800000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P4G_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P5G_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P6G_MASK 0x04000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P7G_MASK 0x08000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P8G_MASK 0x10000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_27P9G_MASK 0x20000000L
+#define BIFPLR6_1_PCIE_ESM_CAP_7__ESM_28P0G_MASK 0x40000000L
+//BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_DATA_LINK_FEATURE_CAP
+#define BIFPLR6_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1__SHIFT 0x1
+#define BIFPLR6_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIFPLR6_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SCALED_FLOW_CONTROL_SUPPORTED_MASK 0x00000001L
+#define BIFPLR6_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_22_1_MASK 0x007FFFFEL
+#define BIFPLR6_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIFPLR6_1_DATA_LINK_FEATURE_STATUS
+#define BIFPLR6_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIFPLR6_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIFPLR6_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_LINK_CAP_16GT
+#define BIFPLR6_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR6_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_1_LINK_CNTL_16GT
+#define BIFPLR6_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIFPLR6_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_1_LINK_STATUS_16GT
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIFPLR6_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIFPLR6_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIFPLR6_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIFPLR6_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR6_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR6_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIFPLR6_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIFPLR6_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_MARGINING_PORT_CAP
+#define BIFPLR6_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIFPLR6_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIFPLR6_1_MARGINING_PORT_STATUS
+#define BIFPLR6_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIFPLR6_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIFPLR6_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIFPLR6_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIFPLR6_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIFPLR6_1_PCIE_CCIX_CAP_LIST
+#define BIFPLR6_1_PCIE_CCIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CCIX_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIFPLR6_1_PCIE_CCIX_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIFPLR6_1_PCIE_CCIX_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_CCIX_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_CCIX_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_CCIX_HEADER_1
+#define BIFPLR6_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV__SHIFT 0x10
+#define BIFPLR6_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN__SHIFT 0x14
+#define BIFPLR6_1_PCIE_CCIX_HEADER_1__CCIX_VENDOR_ID_MASK 0x0000FFFFL
+#define BIFPLR6_1_PCIE_CCIX_HEADER_1__CCIX_CAP_REV_MASK 0x000F0000L
+#define BIFPLR6_1_PCIE_CCIX_HEADER_1__CCIX_CAP_LEN_MASK 0xFFF00000L
+//BIFPLR6_1_PCIE_CCIX_HEADER_2
+#define BIFPLR6_1_PCIE_CCIX_HEADER_2__CAP_ID__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CCIX_HEADER_2__CAP_ID_MASK 0xFFFFL
+//BIFPLR6_1_PCIE_CCIX_CAP
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY__SHIFT 0x1
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE__SHIFT 0x3
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME__SHIFT 0x4
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT__SHIFT 0x8
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_MODE_SUPPORTED_MASK 0x0001L
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_PHY_REACH_LENGTH_CAPABILITY_MASK 0x0006L
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_RECALIBRATION_NEEDED_ON_ESM_DATA_RATE_UPDATE_MASK 0x0008L
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_CALIBRATION_TIME_MASK 0x0070L
+#define BIFPLR6_1_PCIE_CCIX_CAP__ESM_QUICK_EQUALIZATION_TIMEOUT_MASK 0x0700L
+//BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT__SHIFT 0x1
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT__SHIFT 0x2
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT__SHIFT 0x5
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT__SHIFT 0x9
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT__SHIFT 0xe
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_2P5GT_MASK 0x00000001L
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_5GT_MASK 0x00000002L
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_8GT_MASK 0x00000004L
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_16GT_MASK 0x00000020L
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_20GT_MASK 0x00000200L
+#define BIFPLR6_1_PCIE_CCIX_ESM_REQD_CAP__ESM_SUPPORT_25GT_MASK 0x00004000L
+//BIFPLR6_1_PCIE_CCIX_ESM_OPTL_CAP
+#define BIFPLR6_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CCIX_ESM_OPTL_CAP__RESERVED_MASK 0xFFFFFFFFL
+//BIFPLR6_1_PCIE_CCIX_ESM_STATUS
+#define BIFPLR6_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE__SHIFT 0x7
+#define BIFPLR6_1_PCIE_CCIX_ESM_STATUS__ESM_CURRENT_DATA_RATE_MASK 0x0000007FL
+#define BIFPLR6_1_PCIE_CCIX_ESM_STATUS__ESM_CALIBRATION_COMPLETE_MASK 0x00000080L
+//BIFPLR6_1_PCIE_CCIX_ESM_CNTL
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION__SHIFT 0x7
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1__SHIFT 0x8
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE__SHIFT 0xf
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT__SHIFT 0x10
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT__SHIFT 0x14
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET__SHIFT 0x18
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT__SHIFT 0x19
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT__SHIFT 0x1a
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE0_MASK 0x0000007FL
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_PERFORM_CALIBRATION_MASK 0x00000080L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_DATA_RATE1_MASK 0x00007F00L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_ENABLE_MASK 0x00008000L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE2_TIMEOUT_MASK 0x00070000L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_EXTENDED_EQUALIZATION_PHASE3_TIMEOUT_MASK 0x00700000L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__LINK_REACH_TARGET_MASK 0x01000000L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__RETIMER_PRESENT_MASK 0x02000000L
+#define BIFPLR6_1_PCIE_CCIX_ESM_CNTL__ESM_QUICK_EQUALIZATION_TIMEOUT_SELECT_MASK 0x1C000000L
+//BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT__ESM_LANE_0_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT__ESM_LANE_1_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT__ESM_LANE_2_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT__ESM_LANE_3_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT__ESM_LANE_4_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT__ESM_LANE_5_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT__ESM_LANE_6_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT__ESM_LANE_7_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT__ESM_LANE_8_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT__ESM_LANE_9_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT__ESM_LANE_10_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT__ESM_LANE_11_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT__ESM_LANE_12_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT__ESM_LANE_13_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT__ESM_LANE_14_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_DSP_20GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT__ESM_LANE_15_USP_20GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT__ESM_LANE_0_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT__ESM_LANE_1_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT__ESM_LANE_2_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT__ESM_LANE_3_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT__ESM_LANE_4_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT__ESM_LANE_5_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT__ESM_LANE_6_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT__ESM_LANE_7_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT__ESM_LANE_8_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT__ESM_LANE_9_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT__ESM_LANE_10_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT__ESM_LANE_11_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT__ESM_LANE_12_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT__ESM_LANE_13_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT__ESM_LANE_14_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET__SHIFT 0x0
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET__SHIFT 0x4
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_DSP_25GT_TX_PRESET_MASK 0x0FL
+#define BIFPLR6_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT__ESM_LANE_15_USP_25GT_TX_PRESET_MASK 0xF0L
+//BIFPLR6_1_PCIE_CCIX_TRANS_CAP
+#define BIFPLR6_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CCIX_TRANS_CAP__CCIX_OPTIMIZED_TLP_FORMAT_SUPPORT_MASK 0x00000001L
+//BIFPLR6_1_PCIE_CCIX_TRANS_CNTL
+#define BIFPLR6_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE__SHIFT 0x0
+#define BIFPLR6_1_PCIE_CCIX_TRANS_CNTL__CCIX_OPTIMIZED_TLP_FORMAT_ENABLE_MASK 0x00000001L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+//BIF_CFG_DEV0_RC1_VENDOR_ID
+#define BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_DEVICE_ID
+#define BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_COMMAND
+#define BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_RC1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_RC1_STATUS
+#define BIF_CFG_DEV0_RC1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_RC1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_REVISION_ID
+#define BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_PROG_INTERFACE
+#define BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_SUB_CLASS
+#define BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_BASE_CLASS
+#define BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_CACHE_LINE
+#define BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_LATENCY
+#define BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_HEADER
+#define BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_RC1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_RC1_BIST
+#define BIF_CFG_DEV0_RC1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_RC1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_RC1_BASE_ADDR_1
+#define BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_BASE_ADDR_2
+#define BIF_CFG_DEV0_RC1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC1_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV0_RC1_SECONDARY_STATUS
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC1_CAP_PTR
+#define BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV0_RC1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_PMI_CAP
+#define BIF_CFG_DEV0_RC1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_PCIE_CAP
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_RC1_DEVICE_CAP
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_RC1_DEVICE_CNTL
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_DEVICE_STATUS
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_RC1_LINK_CAP
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC1_LINK_CNTL
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_RC1_LINK_STATUS
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_SLOT_CAP
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV0_RC1_SLOT_CNTL
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIF_CFG_DEV0_RC1_SLOT_STATUS
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV0_RC1_ROOT_CNTL
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV0_RC1_ROOT_CAP
+#define BIF_CFG_DEV0_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV0_RC1_ROOT_STATUS
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV0_RC1_DEVICE_CAP2
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_RC1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_LINK_CAP2
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_RC1_LINK_CNTL2
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_RC1_LINK_STATUS2
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_RC1_SLOT_CAP2
+#define BIF_CFG_DEV0_RC1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_SLOT_CNTL2
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_SLOT_STATUS2
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_RC1_SSID_CAP_LIST
+#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_SSID_CAP
+#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_MSI_MAP_CAP
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_LINK_CAP_16GT
+#define BIF_CFG_DEV0_RC1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC1_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp
+//BIF_CFG_DEV1_RC1_VENDOR_ID
+#define BIF_CFG_DEV1_RC1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_DEVICE_ID
+#define BIF_CFG_DEV1_RC1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_COMMAND
+#define BIF_CFG_DEV1_RC1_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_RC1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_RC1_STATUS
+#define BIF_CFG_DEV1_RC1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_RC1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_REVISION_ID
+#define BIF_CFG_DEV1_RC1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_PROG_INTERFACE
+#define BIF_CFG_DEV1_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_SUB_CLASS
+#define BIF_CFG_DEV1_RC1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_BASE_CLASS
+#define BIF_CFG_DEV1_RC1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_CACHE_LINE
+#define BIF_CFG_DEV1_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_LATENCY
+#define BIF_CFG_DEV1_RC1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_HEADER
+#define BIF_CFG_DEV1_RC1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_RC1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_RC1_BIST
+#define BIF_CFG_DEV1_RC1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_RC1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_RC1_BASE_ADDR_1
+#define BIF_CFG_DEV1_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_BASE_ADDR_2
+#define BIF_CFG_DEV1_RC1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC1_IO_BASE_LIMIT
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV1_RC1_SECONDARY_STATUS
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PREF_BASE_UPPER
+#define BIF_CFG_DEV1_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC1_CAP_PTR
+#define BIF_CFG_DEV1_RC1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_RC1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_INTERRUPT_LINE
+#define BIF_CFG_DEV1_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_INTERRUPT_PIN
+#define BIF_CFG_DEV1_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV1_RC1_PMI_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_PMI_CAP
+#define BIF_CFG_DEV1_RC1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC1_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_PCIE_CAP
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_RC1_DEVICE_CAP
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_RC1_DEVICE_CNTL
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_DEVICE_STATUS
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV1_RC1_LINK_CAP
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_RC1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC1_LINK_CNTL
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV1_RC1_LINK_STATUS
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_SLOT_CAP
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV1_RC1_SLOT_CNTL
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIF_CFG_DEV1_RC1_SLOT_STATUS
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV1_RC1_ROOT_CNTL
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV1_RC1_ROOT_CAP
+#define BIF_CFG_DEV1_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV1_RC1_ROOT_STATUS
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV1_RC1_DEVICE_CAP2
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_RC1_DEVICE_CNTL2
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_DEVICE_STATUS2
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_LINK_CAP2
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_RC1_LINK_CNTL2
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_RC1_LINK_STATUS2
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV1_RC1_SLOT_CAP2
+#define BIF_CFG_DEV1_RC1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_SLOT_CNTL2
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_SLOT_STATUS2
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_MSI_CAP_LIST
+#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV1_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_MSI_MSG_DATA
+#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_RC1_SSID_CAP_LIST
+#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_SSID_CAP
+#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_MSI_MAP_CAP
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV1_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_LINK_CAP_16GT
+#define BIF_CFG_DEV1_RC1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_LINK_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_RC1_LINK_STATUS_16GT
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV1_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV1_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_RC1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV1_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV1_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_rc_bifcfgdecp
+//BIF_CFG_DEV2_RC1_VENDOR_ID
+#define BIF_CFG_DEV2_RC1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC1_DEVICE_ID
+#define BIF_CFG_DEV2_RC1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC1_COMMAND
+#define BIF_CFG_DEV2_RC1_COMMAND__IOEN_DN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_COMMAND__MEMEN_DN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_COMMAND__IOEN_DN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_COMMAND__MEMEN_DN_MASK 0x0002L
+#define BIF_CFG_DEV2_RC1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_RC1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV2_RC1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_RC1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_RC1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV2_RC1_STATUS
+#define BIF_CFG_DEV2_RC1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV2_RC1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV2_RC1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV2_RC1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV2_RC1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV2_RC1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV2_RC1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV2_RC1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV2_RC1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV2_RC1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV2_RC1_REVISION_ID
+#define BIF_CFG_DEV2_RC1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_PROG_INTERFACE
+#define BIF_CFG_DEV2_RC1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV2_RC1_SUB_CLASS
+#define BIF_CFG_DEV2_RC1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_RC1_BASE_CLASS
+#define BIF_CFG_DEV2_RC1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_RC1_CACHE_LINE
+#define BIF_CFG_DEV2_RC1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV2_RC1_LATENCY
+#define BIF_CFG_DEV2_RC1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV2_RC1_HEADER
+#define BIF_CFG_DEV2_RC1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV2_RC1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV2_RC1_BIST
+#define BIF_CFG_DEV2_RC1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV2_RC1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV2_RC1_BASE_ADDR_1
+#define BIF_CFG_DEV2_RC1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_BASE_ADDR_2
+#define BIF_CFG_DEV2_RC1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK 0x000000FFL
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK 0x0000FF00L
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK 0x00FF0000L
+#define BIF_CFG_DEV2_RC1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK 0xFF000000L
+//BIF_CFG_DEV2_RC1_IO_BASE_LIMIT
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_BASE__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_BASE_MASK 0x00F0L
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT__IO_LIMIT_MASK 0xF000L
+//BIF_CFG_DEV2_RC1_SECONDARY_STATUS
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV2_RC1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK 0x0000000FL
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK 0x0000FFF0L
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC1_PREF_BASE_UPPER
+#define BIF_CFG_DEV2_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV2_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_RC1_CAP_PTR
+#define BIF_CFG_DEV2_RC1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV2_RC1_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_RC1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_INTERRUPT_LINE
+#define BIF_CFG_DEV2_RC1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV2_RC1_INTERRUPT_PIN
+#define BIF_CFG_DEV2_RC1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__SERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__ISA_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__VGA_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK 0x0080L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK 0x0100L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK 0x0200L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK 0x0400L
+#define BIF_CFG_DEV2_RC1_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK 0x0800L
+//BIF_CFG_DEV2_RC1_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV2_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK 0x01L
+//BIF_CFG_DEV2_RC1_PMI_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_RC1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_PMI_CAP
+#define BIF_CFG_DEV2_RC1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV2_RC1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV2_RC1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV2_RC1_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_RC1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_PCIE_CAP
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV2_RC1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV2_RC1_DEVICE_CAP
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV2_RC1_DEVICE_CNTL
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK 0x8000L
+//BIF_CFG_DEV2_RC1_DEVICE_STATUS
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV2_RC1_LINK_CAP
+#define BIF_CFG_DEV2_RC1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV2_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV2_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV2_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV2_RC1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_RC1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV2_RC1_LINK_CNTL
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV2_RC1_LINK_STATUS
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV2_RC1_SLOT_CAP
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK 0x00000002L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK 0x00000004L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK 0x00000008L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK 0x00000010L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__HOTPLUG_SURPRISE_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__HOTPLUG_CAPABLE_MASK 0x00000040L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK 0x00007F80L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK 0x00018000L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK 0x00020000L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK 0x00040000L
+#define BIF_CFG_DEV2_RC1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK 0xFFF80000L
+//BIF_CFG_DEV2_RC1_SLOT_CNTL
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT 0xd
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK 0x00C0L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK 0x0300L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK 0x0400L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK 0x0800L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK 0x1000L
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK 0x2000L
+//BIF_CFG_DEV2_RC1_SLOT_STATUS
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK 0x0002L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK 0x0004L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__COMMAND_COMPLETED_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__MRL_SENSOR_STATE_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK 0x0080L
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS__DL_STATE_CHANGED_MASK 0x0100L
+//BIF_CFG_DEV2_RC1_ROOT_CNTL
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__PM_INTERRUPT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK 0x0010L
+//BIF_CFG_DEV2_RC1_ROOT_CAP
+#define BIF_CFG_DEV2_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK 0x0001L
+//BIF_CFG_DEV2_RC1_ROOT_STATUS
+#define BIF_CFG_DEV2_RC1_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_ROOT_STATUS__PME_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_ROOT_STATUS__PME_PENDING__SHIFT 0x11
+#define BIF_CFG_DEV2_RC1_ROOT_STATUS__PME_REQUESTOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_ROOT_STATUS__PME_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC1_ROOT_STATUS__PME_PENDING_MASK 0x00020000L
+//BIF_CFG_DEV2_RC1_DEVICE_CAP2
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_RC1_DEVICE_CNTL2
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV2_RC1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV2_RC1_DEVICE_STATUS2
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC1_LINK_CAP2
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV2_RC1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_RC1_LINK_CNTL2
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV2_RC1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV2_RC1_LINK_STATUS2
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV2_RC1_SLOT_CAP2
+#define BIF_CFG_DEV2_RC1_SLOT_CAP2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_SLOT_CAP2__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_SLOT_CNTL2
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_SLOT_CNTL2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC1_SLOT_STATUS2
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_SLOT_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC1_MSI_CAP_LIST
+#define BIF_CFG_DEV2_RC1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_RC1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV2_RC1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV2_RC1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV2_RC1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_MSI_MSG_DATA
+#define BIF_CFG_DEV2_RC1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_RC1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_RC1_SSID_CAP_LIST
+#define BIF_CFG_DEV2_RC1_SSID_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_SSID_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_RC1_SSID_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_SSID_CAP
+#define BIF_CFG_DEV2_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_SSID_CAP__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_MSI_MAP_CAP
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP__EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP__FIXD__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP__CAP_TYPE__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP__EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP__FIXD_MASK 0x0002L
+#define BIF_CFG_DEV2_RC1_MSI_MAP_CAP__CAP_TYPE_MASK 0xF800L
+//BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV2_RC1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV2_RC1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_RC1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV2_RC1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV2_RC1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK 0x00000002L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK 0x00000004L
+//BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK 0x00000002L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK 0x00000004L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK 0x00000008L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK 0x00000010L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK 0x00000020L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK 0x00000040L
+#define BIF_CFG_DEV2_RC1_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK 0xF8000000L
+//BIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_RC1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC1_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_RC1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV2_RC1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC1_LINK_CAP_16GT
+#define BIF_CFG_DEV2_RC1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_LINK_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_RC1_LINK_STATUS_16GT
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV2_RC1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV2_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_RC1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_RC1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_RC1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV2_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV2_RC1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_RC1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_COMMAND
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_1_STATUS
+#define BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_LATENCY
+#define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_HEADER
+#define BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_1_BIST
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF0_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF0_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_COMMAND
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_1_STATUS
+#define BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_LATENCY
+#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_HEADER
+#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_1_BIST
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK 0x3F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK 0x003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK 0x8000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK 0x0000003FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK 0xFFFFF000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK 0xFFE00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x0020L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK 0xFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_CMD_COMPLETE_INTR_EN_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_HANG_NEED_FLR_INTR_EN_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD1_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_CMD_COMPLETE_INTR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_HANG_NEED_FLR_INTR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD1_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK 0x02000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK 0x0001L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK 0x00000F00L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK 0x01000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT 0x1b
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT 0x1d
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x1e
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK 0x08000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK 0x10000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK 0x20000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK 0x40000000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK 0x0000007FL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK 0xFFFFFC00L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN0SCH_OFFSET_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCN1SCH_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK 0x00000070L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK 0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB__VF16_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB__VF17_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB__VF18_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB__VF19_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB__VF20_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB__VF21_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB__VF22_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB__VF23_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB__VF24_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB__VF25_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB__VF26_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB__VF27_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB__VF28_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB__VF29_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_SIZE_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB__VF30_FB_OFFSET_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0__DW0_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1__DW1_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2__DW2_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3__DW3_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4__DW4_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5__DW5_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6__DW6_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7__DW7_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8__DW8_MASK 0xFFFFFFFFL
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF2_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_COMMAND
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_1_STATUS
+#define BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_LATENCY
+#define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_HEADER
+#define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF2_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_1_BIST
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF2_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_SBRN
+#define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_FLADJ
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF2_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF2_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF2_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF2_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF2_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF2_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF3_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_COMMAND
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_1_STATUS
+#define BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_LATENCY
+#define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_HEADER
+#define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF3_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_1_BIST
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF3_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_SBRN
+#define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_FLADJ
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF3_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF3_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF3_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF3_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF3_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF3_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF3_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF4_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_COMMAND
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF4_1_STATUS
+#define BIF_CFG_DEV0_EPF4_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF4_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF4_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_LATENCY
+#define BIF_CFG_DEV0_EPF4_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_HEADER
+#define BIF_CFG_DEV0_EPF4_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF4_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF4_1_BIST
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF4_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF4_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF4_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF4_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_1_SBRN
+#define BIF_CFG_DEV0_EPF4_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_FLADJ
+#define BIF_CFG_DEV0_EPF4_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF4_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF4_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF4_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF4_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF4_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF4_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF4_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF4_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF4_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF4_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF5_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_COMMAND
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF5_1_STATUS
+#define BIF_CFG_DEV0_EPF5_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF5_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF5_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_LATENCY
+#define BIF_CFG_DEV0_EPF5_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_HEADER
+#define BIF_CFG_DEV0_EPF5_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF5_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF5_1_BIST
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF5_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF5_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF5_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF5_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_1_SBRN
+#define BIF_CFG_DEV0_EPF5_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_FLADJ
+#define BIF_CFG_DEV0_EPF5_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF5_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF5_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF5_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF5_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF5_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF5_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF5_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF5_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF5_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF5_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF6_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_COMMAND
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF6_1_STATUS
+#define BIF_CFG_DEV0_EPF6_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF6_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF6_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_LATENCY
+#define BIF_CFG_DEV0_EPF6_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_HEADER
+#define BIF_CFG_DEV0_EPF6_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF6_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF6_1_BIST
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF6_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF6_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF6_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF6_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_1_SBRN
+#define BIF_CFG_DEV0_EPF6_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_FLADJ
+#define BIF_CFG_DEV0_EPF6_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF6_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF6_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF6_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF6_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF6_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF6_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF6_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF6_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF6_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF6_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF7_1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_COMMAND
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV0_EPF7_1_STATUS
+#define BIF_CFG_DEV0_EPF7_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_1_REVISION_ID
+#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF7_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF7_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_LATENCY
+#define BIF_CFG_DEV0_EPF7_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_HEADER
+#define BIF_CFG_DEV0_EPF7_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV0_EPF7_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV0_EPF7_1_BIST
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV0_EPF7_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_CAP_PTR
+#define BIF_CFG_DEV0_EPF7_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF7_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF7_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PMI_CAP
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_1_SBRN
+#define BIF_CFG_DEV0_EPF7_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_FLADJ
+#define BIF_CFG_DEV0_EPF7_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV0_EPF7_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD
+#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV0_EPF7_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV0_EPF7_1_LINK_CAP
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV0_EPF7_1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV0_EPF7_1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV0_EPF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV0_EPF7_1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV0_EPF7_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_MASK
+#define BIF_CFG_DEV0_EPF7_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV0_EPF7_1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV0_EPF7_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp
+//BIF_CFG_DEV1_EPF0_1_VENDOR_ID
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_DEVICE_ID
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_COMMAND
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF0_1_STATUS
+#define BIF_CFG_DEV1_EPF0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_REVISION_ID
+#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_SUB_CLASS
+#define BIF_CFG_DEV1_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_CLASS
+#define BIF_CFG_DEV1_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_CACHE_LINE
+#define BIF_CFG_DEV1_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_LATENCY
+#define BIF_CFG_DEV1_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_HEADER
+#define BIF_CFG_DEV1_EPF0_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF0_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF0_1_BIST
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF0_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV1_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_CAP_PTR
+#define BIF_CFG_DEV1_EPF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_MIN_GRANT
+#define BIF_CFG_DEV1_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PMI_CAP
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_SBRN
+#define BIF_CFG_DEV1_EPF0_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_FLADJ
+#define BIF_CFG_DEV1_EPF0_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV1_EPF0_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV1_EPF0_1_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF0_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV1_EPF0_1_LINK_CAP
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_LINK_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV1_EPF0_1_LINK_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_LINK_CAP2
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_1_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF0_1_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_MASK
+#define BIF_CFG_DEV1_EPF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_PENDING
+#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF0_1_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_1_MSIX_PBA
+#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV1_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_LINK_CAP_16GT
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_LINK_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV1_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV1_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp
+//BIF_CFG_DEV1_EPF1_1_VENDOR_ID
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_DEVICE_ID
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_COMMAND
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV1_EPF1_1_STATUS
+#define BIF_CFG_DEV1_EPF1_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_1_REVISION_ID
+#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE
+#define BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_SUB_CLASS
+#define BIF_CFG_DEV1_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_CLASS
+#define BIF_CFG_DEV1_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_CACHE_LINE
+#define BIF_CFG_DEV1_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_LATENCY
+#define BIF_CFG_DEV1_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_HEADER
+#define BIF_CFG_DEV1_EPF1_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV1_EPF1_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV1_EPF1_1_BIST
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV1_EPF1_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV1_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_ADAPTER_ID
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_CAP_PTR
+#define BIF_CFG_DEV1_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE
+#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN
+#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_MIN_GRANT
+#define BIF_CFG_DEV1_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_MAX_LATENCY
+#define BIF_CFG_DEV1_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PMI_CAP
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_1_SBRN
+#define BIF_CFG_DEV1_EPF1_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_FLADJ
+#define BIF_CFG_DEV1_EPF1_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV1_EPF1_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD
+#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV1_EPF1_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_CAP
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV1_EPF1_1_LINK_CAP
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_1_LINK_CNTL
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV1_EPF1_1_LINK_STATUS
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_LINK_CAP2
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV1_EPF1_1_LINK_CNTL2
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV1_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV1_EPF1_1_LINK_STATUS2
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV1_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_MASK
+#define BIF_CFG_DEV1_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_MASK_64
+#define BIF_CFG_DEV1_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_PENDING
+#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64
+#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV1_EPF1_1_MSIX_TABLE
+#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_1_MSIX_PBA
+#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV1_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf0_bifcfgdecp
+//BIF_CFG_DEV2_EPF0_1_VENDOR_ID
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_DEVICE_ID
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_COMMAND
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF0_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV2_EPF0_1_STATUS
+#define BIF_CFG_DEV2_EPF0_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV2_EPF0_1_REVISION_ID
+#define BIF_CFG_DEV2_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_PROG_INTERFACE
+#define BIF_CFG_DEV2_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_SUB_CLASS
+#define BIF_CFG_DEV2_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_BASE_CLASS
+#define BIF_CFG_DEV2_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_CACHE_LINE
+#define BIF_CFG_DEV2_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_LATENCY
+#define BIF_CFG_DEV2_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_HEADER
+#define BIF_CFG_DEV2_EPF0_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV2_EPF0_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV2_EPF0_1_BIST
+#define BIF_CFG_DEV2_EPF0_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV2_EPF0_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV2_EPF0_1_BASE_ADDR_1
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_BASE_ADDR_2
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_BASE_ADDR_3
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_BASE_ADDR_4
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_BASE_ADDR_5
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_BASE_ADDR_6
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV2_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_ADAPTER_ID
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_CAP_PTR
+#define BIF_CFG_DEV2_EPF0_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_INTERRUPT_LINE
+#define BIF_CFG_DEV2_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_INTERRUPT_PIN
+#define BIF_CFG_DEV2_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_MIN_GRANT
+#define BIF_CFG_DEV2_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_MAX_LATENCY
+#define BIF_CFG_DEV2_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV2_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PMI_CAP
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF0_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF0_1_SBRN
+#define BIF_CFG_DEV2_EPF0_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_FLADJ
+#define BIF_CFG_DEV2_EPF0_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV2_EPF0_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV2_EPF0_1_DBESL_DBESLD
+#define BIF_CFG_DEV2_EPF0_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV2_EPF0_1_DEVICE_CAP
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV2_EPF0_1_LINK_CAP
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF0_1_LINK_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV2_EPF0_1_LINK_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS2
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_LINK_CAP2
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF0_1_LINK_CNTL2
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV2_EPF0_1_LINK_STATUS2
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_MASK
+#define BIF_CFG_DEV2_EPF0_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_MASK_64
+#define BIF_CFG_DEV2_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_PENDING
+#define BIF_CFG_DEV2_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSI_PENDING_64
+#define BIF_CFG_DEV2_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV2_EPF0_1_MSIX_TABLE
+#define BIF_CFG_DEV2_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF0_1_MSIX_PBA
+#define BIF_CFG_DEV2_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK 0x00000070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK 0x00000C00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK 0x000EL
+//BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK 0x0001L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x007F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK 0x003F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK 0x000000FEL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK 0x000E0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK 0x07000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK 0x0002L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK 0x00000002L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK 0x0F00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK 0x7000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK 0x000003FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK 0x00001C00L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK 0x03FF0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK 0x1C000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK 0x007FFFFFL
+#define BIF_CFG_DEV2_EPF0_1_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_LINK_CAP_16GT
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_CAP_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_LINK_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL_16GT__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_CNTL_16GT__RESERVED_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK 0x00000002L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK 0x00000004L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK 0x00000008L
+#define BIF_CFG_DEV2_EPF0_1_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK 0x00000010L
+//BIF_CFG_DEV2_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV2_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK 0x0000FFFFL
+//BIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK 0xF0L
+//BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_CAP
+#define BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK 0x0001L
+//BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS__MARGINING_READY_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF0_1_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK 0x0002L
+//BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK 0x0038L
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF0_1_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf1_bifcfgdecp
+//BIF_CFG_DEV2_EPF1_1_VENDOR_ID
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_DEVICE_ID
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_COMMAND
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF1_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV2_EPF1_1_STATUS
+#define BIF_CFG_DEV2_EPF1_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV2_EPF1_1_REVISION_ID
+#define BIF_CFG_DEV2_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV2_EPF1_1_PROG_INTERFACE
+#define BIF_CFG_DEV2_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_SUB_CLASS
+#define BIF_CFG_DEV2_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_BASE_CLASS
+#define BIF_CFG_DEV2_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_CACHE_LINE
+#define BIF_CFG_DEV2_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_LATENCY
+#define BIF_CFG_DEV2_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_HEADER
+#define BIF_CFG_DEV2_EPF1_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV2_EPF1_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV2_EPF1_1_BIST
+#define BIF_CFG_DEV2_EPF1_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF1_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV2_EPF1_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV2_EPF1_1_BASE_ADDR_1
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_BASE_ADDR_2
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_BASE_ADDR_3
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_BASE_ADDR_4
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_BASE_ADDR_5
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_BASE_ADDR_6
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV2_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_ADAPTER_ID
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_CAP_PTR
+#define BIF_CFG_DEV2_EPF1_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_INTERRUPT_LINE
+#define BIF_CFG_DEV2_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_INTERRUPT_PIN
+#define BIF_CFG_DEV2_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_MIN_GRANT
+#define BIF_CFG_DEV2_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_MAX_LATENCY
+#define BIF_CFG_DEV2_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV2_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PMI_CAP
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF1_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF1_1_SBRN
+#define BIF_CFG_DEV2_EPF1_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_FLADJ
+#define BIF_CFG_DEV2_EPF1_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV2_EPF1_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV2_EPF1_1_DBESL_DBESLD
+#define BIF_CFG_DEV2_EPF1_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF1_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV2_EPF1_1_DEVICE_CAP
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV2_EPF1_1_LINK_CAP
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF1_1_LINK_CNTL
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV2_EPF1_1_LINK_STATUS
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS2
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_LINK_CAP2
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF1_1_LINK_CNTL2
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV2_EPF1_1_LINK_STATUS2
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV2_EPF1_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_MASK
+#define BIF_CFG_DEV2_EPF1_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_MASK_64
+#define BIF_CFG_DEV2_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_PENDING
+#define BIF_CFG_DEV2_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSI_PENDING_64
+#define BIF_CFG_DEV2_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV2_EPF1_1_MSIX_TABLE
+#define BIF_CFG_DEV2_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF1_1_MSIX_PBA
+#define BIF_CFG_DEV2_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF1_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+// addressBlock: nbio_nbif0_bif_cfg_dev2_epf2_bifcfgdecp
+//BIF_CFG_DEV2_EPF2_1_VENDOR_ID
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_ID__VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_ID__VENDOR_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_DEVICE_ID
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_ID__DEVICE_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_ID__DEVICE_ID_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_COMMAND
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__IO_ACCESS_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__MEM_ACCESS_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__BUS_MASTER_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__PAL_SNOOP_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__AD_STEPPING__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__SERR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__FAST_B2B_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__INT_DIS__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__IO_ACCESS_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__MEM_ACCESS_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__BUS_MASTER_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__PAL_SNOOP_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__AD_STEPPING_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__SERR_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__FAST_B2B_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF2_1_COMMAND__INT_DIS_MASK 0x0400L
+//BIF_CFG_DEV2_EPF2_1_STATUS
+#define BIF_CFG_DEV2_EPF2_1_STATUS__IMMEDIATE_READINESS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_STATUS__INT_STATUS__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_STATUS__CAP_LIST__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_STATUS__PCI_66_CAP__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_STATUS__DEVSEL_TIMING__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_STATUS__IMMEDIATE_READINESS_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__INT_STATUS_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__CAP_LIST_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__PCI_66_CAP_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__FAST_BACK_CAPABLE_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__DEVSEL_TIMING_MASK 0x0600L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK 0x2000L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF2_1_STATUS__PARITY_ERROR_DETECTED_MASK 0x8000L
+//BIF_CFG_DEV2_EPF2_1_REVISION_ID
+#define BIF_CFG_DEV2_EPF2_1_REVISION_ID__MINOR_REV_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_REVISION_ID__MINOR_REV_ID_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF2_1_REVISION_ID__MAJOR_REV_ID_MASK 0xF0L
+//BIF_CFG_DEV2_EPF2_1_PROG_INTERFACE
+#define BIF_CFG_DEV2_EPF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_SUB_CLASS
+#define BIF_CFG_DEV2_EPF2_1_SUB_CLASS__SUB_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_SUB_CLASS__SUB_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_BASE_CLASS
+#define BIF_CFG_DEV2_EPF2_1_BASE_CLASS__BASE_CLASS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_CLASS__BASE_CLASS_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_CACHE_LINE
+#define BIF_CFG_DEV2_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_LATENCY
+#define BIF_CFG_DEV2_EPF2_1_LATENCY__LATENCY_TIMER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_LATENCY__LATENCY_TIMER_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_HEADER
+#define BIF_CFG_DEV2_EPF2_1_HEADER__HEADER_TYPE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_HEADER__DEVICE_TYPE__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_HEADER__HEADER_TYPE_MASK 0x7FL
+#define BIF_CFG_DEV2_EPF2_1_HEADER__DEVICE_TYPE_MASK 0x80L
+//BIF_CFG_DEV2_EPF2_1_BIST
+#define BIF_CFG_DEV2_EPF2_1_BIST__BIST_COMP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_BIST__BIST_STRT__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_BIST__BIST_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_BIST__BIST_COMP_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF2_1_BIST__BIST_STRT_MASK 0x40L
+#define BIF_CFG_DEV2_EPF2_1_BIST__BIST_CAP_MASK 0x80L
+//BIF_CFG_DEV2_EPF2_1_BASE_ADDR_1
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_1__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_BASE_ADDR_2
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_2__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_BASE_ADDR_3
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_3__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_BASE_ADDR_4
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_4__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_BASE_ADDR_5
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_5__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_BASE_ADDR_6
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_BASE_ADDR_6__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV2_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_ADAPTER_ID
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_ROM_BASE_ADDR
+#define BIF_CFG_DEV2_EPF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_CAP_PTR
+#define BIF_CFG_DEV2_EPF2_1_CAP_PTR__CAP_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_CAP_PTR__CAP_PTR_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_INTERRUPT_LINE
+#define BIF_CFG_DEV2_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_INTERRUPT_PIN
+#define BIF_CFG_DEV2_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_MIN_GRANT
+#define BIF_CFG_DEV2_EPF2_1_MIN_GRANT__MIN_GNT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MIN_GRANT__MIN_GNT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_MAX_LATENCY
+#define BIF_CFG_DEV2_EPF2_1_MAX_LATENCY__MAX_LAT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MAX_LATENCY__MAX_LAT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST__LENGTH__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST__CAP_ID_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST__NEXT_PTR_MASK 0x0000FF00L
+#define BIF_CFG_DEV2_EPF2_1_VENDOR_CAP_LIST__LENGTH_MASK 0x00FF0000L
+//BIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PMI_CAP
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__PME_CLOCK__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__AUX_CURRENT__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__D1_SUPPORT__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__D2_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__PME_SUPPORT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__VERSION_MASK 0x0007L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__PME_CLOCK_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__AUX_CURRENT_MASK 0x01C0L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__D1_SUPPORT_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__D2_SUPPORT_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF2_1_PMI_CAP__PME_SUPPORT_MASK 0xF800L
+//BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__PME_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__POWER_STATE_MASK 0x00000003L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK 0x00000008L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__PME_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__DATA_SELECT_MASK 0x00001E00L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__DATA_SCALE_MASK 0x00006000L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__PME_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF2_1_PMI_STATUS_CNTL__PMI_DATA_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF2_1_SBRN
+#define BIF_CFG_DEV2_EPF2_1_SBRN__SBRN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_SBRN__SBRN_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_FLADJ
+#define BIF_CFG_DEV2_EPF2_1_FLADJ__FLADJ__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_FLADJ__NFC__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_FLADJ__FLADJ_MASK 0x3FL
+#define BIF_CFG_DEV2_EPF2_1_FLADJ__NFC_MASK 0x40L
+//BIF_CFG_DEV2_EPF2_1_DBESL_DBESLD
+#define BIF_CFG_DEV2_EPF2_1_DBESL_DBESLD__DBESL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_DBESL_DBESLD__DBESLD__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_DBESL_DBESLD__DBESL_MASK 0x0FL
+#define BIF_CFG_DEV2_EPF2_1_DBESL_DBESLD__DBESLD_MASK 0xF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__VERSION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__VERSION_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__DEVICE_TYPE_MASK 0x00F0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK 0x3E00L
+//BIF_CFG_DEV2_EPF2_1_DEVICE_CAP
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK 0x00000018L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__EXTENDED_TAG_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK 0x000001C0L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK 0x00000E00L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK 0x03FC0000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK 0x0C000000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP__FLR_CAPABLE_MASK 0x10000000L
+//BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK 0x00E0L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK 0x7000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL__INITIATE_FLR_MASK 0x8000L
+//BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__CORR_ERR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__AUX_PWR__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__CORR_ERR_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__FATAL_ERR_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__USR_DETECTED_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__AUX_PWR_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK 0x0040L
+//BIF_CFG_DEV2_EPF2_1_LINK_CAP
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__PM_SUPPORT__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__PORT_NUMBER__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__LINK_SPEED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__LINK_WIDTH_MASK 0x000003F0L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__PM_SUPPORT_MASK 0x00000C00L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK 0x00007000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK 0x00038000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP__PORT_NUMBER_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF2_1_LINK_CNTL
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__PM_CONTROL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__LINK_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__PM_CONTROL_MASK 0x0003L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__LINK_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__RETRAIN_LINK_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__EXTENDED_SYNC_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK 0xC000L
+//BIF_CFG_DEV2_EPF2_1_LINK_STATUS
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__LINK_TRAINING__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__DL_ACTIVE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK 0x03F0L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__LINK_TRAINING_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__DL_ACTIVE_MASK 0x2000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK 0x8000L
+//BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000FL
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK 0x00000200L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK 0x00000400L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK 0x00000800L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK 0x00003000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK 0x0000C000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK 0x000C0000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK 0x00C00000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK 0x03000000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK 0x04000000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CAP2__FRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__LTR_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK 0x1000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__OBFF_EN_MASK 0x6000L
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK 0x8000L
+//BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS2
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS2__RESERVED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_DEVICE_STATUS2__RESERVED_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_LINK_CAP2
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__DRS_SUPPORTED__SHIFT 0x1f
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK 0x000000FEL
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK 0x007F0000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CAP2__DRS_SUPPORTED_MASK 0x80000000L
+//BIF_CFG_DEV2_EPF2_1_LINK_CNTL2
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK 0x000FL
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__XMIT_MARGIN_MASK 0x0380L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK 0x0400L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK 0x0800L
+#define BIF_CFG_DEV2_EPF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK 0xF000L
+//BIF_CFG_DEV2_EPF2_1_LINK_STATUS2
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK 0x0300L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK 0x7000L
+#define BIF_CFG_DEV2_EPF2_1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK 0x8000L
+//BIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_MSI_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK 0x000EL
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK 0x0070L
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK 0x0080L
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK 0x0100L
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK 0x0200L
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK 0x0400L
+//BIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK 0xFFFFFFFCL
+//BIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA__MSI_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_MASK
+#define BIF_CFG_DEV2_EPF2_1_MSI_MASK__MSI_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_MASK__MSI_MASK_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK 0xFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_MASK_64
+#define BIF_CFG_DEV2_EPF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_MASK_64__MSI_MASK_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_PENDING
+#define BIF_CFG_DEV2_EPF2_1_MSI_PENDING__MSI_PENDING__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_PENDING__MSI_PENDING_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSI_PENDING_64
+#define BIF_CFG_DEV2_EPF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST__CAP_ID_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK 0x07FFL
+#define BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK 0x4000L
+#define BIF_CFG_DEV2_EPF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK 0x8000L
+//BIF_CFG_DEV2_EPF2_1_MSIX_TABLE
+#define BIF_CFG_DEV2_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF2_1_MSIX_PBA
+#define BIF_CFG_DEV2_EPF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK 0xFFFFFFF8L
+//BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x1a
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK 0x00000010L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK 0x00000020L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK 0x00008000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK 0x00010000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK 0x00020000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK 0x00040000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK 0x00080000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK 0x00100000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK 0x00200000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK 0x00400000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK 0x00800000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK 0x01000000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK 0x02000000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK 0x04000000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK 0x00008000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK 0x00000040L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK 0x00002000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK 0x00004000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK 0x00008000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK 0x0000001FL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK 0x00000080L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK 0x00000200L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK 0x00000400L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK 0x00000800L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK 0x00001000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK 0xFFFFFFFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK 0xFFFFFFF0L
+//BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK 0x000000E0L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK 0x00003F00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK 0xFFFF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK 0x000000FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK 0x00001C00L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK 0x00006000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK 0x00038000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK 0x001C0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK 0x01L
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK 0x0000001FL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK 0x00000300L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK 0x00003000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK 0x00FF0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK 0xFF000000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK 0x000000FFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK 0x001FL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK 0x0100L
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK 0x001FL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK 0xFFL
+//BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK 0x0040L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK 0x0008L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK 0x0010L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK 0x0020L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK 0x0040L
+//BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK 0x0004L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK 0x1F00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK 0x0004L
+//BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK 0x0001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK 0x0002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK 0x0070L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK 0x0000FFFFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK 0x000F0000L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK 0xFFF00000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK 0x00000001L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK 0x00000002L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK 0x00000004L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK 0x00000100L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK 0x00000600L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK 0x07FF0000L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK 0x00000007L
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK 0x00000300L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_0__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_1__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_2__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_3__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_4__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_5__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_6__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_7__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_8__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_9__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_10__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_11__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_12__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_13__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_14__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_15__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_16__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_17__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_18__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_19__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_20__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_21__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_22__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_23__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_24__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_25__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_26__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_27__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_28__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_29__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_30__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_31__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_32__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_33__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_34__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_35__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_36__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_37__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_38__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_39__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_40__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_41__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_42__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_43__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_44__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_45__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_46__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_47__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_48__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_49__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_50__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_51__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_52__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_53__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_54__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_55__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_56__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_57__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_58__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_59__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_60__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_61__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_62__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+//BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY__SHIFT 0x0
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY__SHIFT 0x8
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_LOWER_ENTRY_MASK 0x00FFL
+#define BIF_CFG_DEV2_EPF2_1_PCIE_TPH_ST_TABLE_63__TPH_ST_UPPER_ENTRY_MASK 0xFF00L
+
+
+#endif
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